Loesung Praktikum

hardware/signal_processing/add.vhd

     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+    -- Zustände für die Zustandsmaschine zur Berechnung
+    type SigState is (
+	SIG_IDLE,
+	SIG_READ,
+	SIG_ADD,
+	SIG_WRITE
+    );
+    
+    signal current_sig_state : SigState;
+    signal next_sig_state : SigState;
+
+    signal signal_add_start : std_logic;
+    signal signal_add_done : std_logic;
+
+
 begin
+
+    u_float_add : entity work.float_add
+	port map(
+		clk => clk,
+		reset => reset,
+		start => signal_add_start,
+		done => signal_add_done,
+		A => signal_a_readdata,
+		B => signal_b_readdata,
+		sum => signal_writedata
+	);
+		    
+
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
             when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN - 1 ) then
+                if ( index = work.task.STREAM_LEN) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
             when work.task.TASK_DONE =>
         end case;
     end process task_state_transitions;
 
-    sync : process ( clk, reset ) is
+    sig_state_transitions : process (all) is
+    begin
+	next_sig_state <= current_sig_state;
+	case current_sig_state is
+		when SIG_IDLE =>
+		   if ( current_task_state = work.task.TASK_RUNNING ) then
+			next_sig_state <= SIG_READ;
+		   end if;
+		when SIG_READ =>
+			next_sig_state <= SIG_ADD;
+		when SIG_ADD =>
+		    if ( signal_add_done = '1') then
+			next_sig_state <= SIG_WRITE;
+		    end if;
+		when SIG_WRITE =>
+			next_sig_state <= SIG_IDLE;
+	end case;
+    end process sig_state_transitions;
+
+    task_sync : process ( clk, reset ) is
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
-            index <= 0;
+            --index <= 0;
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
             case next_task_state is
             when work.task.TASK_IDLE =>
-                index <= 0;
-                signal_write <= '0';
+                null;
+                -- signal_write <= '0';
             when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
+                null;
+                -- signal_write <= '1';
+                -- signal_writedata <= ( others => '0' );
             when work.task.TASK_DONE =>
-                index <= 0;
-                signal_write <= '0';
+                null;
+                -- signal_write <= '0';
+            end case;
+        end if;
+    end process task_sync;
+
+    sync : process (all) is
+    begin
+	if ( reset = '1' ) then
+            current_sig_state <= SIG_IDLE;
+	    index <= 0;
+	    signal_a_read <= '0';
+	    signal_b_read <= '0';
+	    signal_add_start <= '0';
+	    signal_write <= '0';
+        elsif ( rising_edge( clk ) ) then
+            current_sig_state <= next_sig_state;
+            signal_write <= '0';
+	    signal_a_read <= '0';
+	    signal_b_read <= '0';
+            case next_sig_state is
+		    when SIG_IDLE =>
+		        if (index = 0) then
+			   current_sig_state <= SIG_ADD;
+			end if;
+		    when SIG_READ =>
+		        signal_a_read <= '1';
+			signal_b_read <= '1';
+		    when SIG_ADD =>
+		        signal_add_start <= '1';
+		    when SIG_WRITE =>
+			signal_add_start <= '0';
+			signal_write <= '1';
+			index <= index + 1;	
             end case;
         end if;
     end process sync;

hardware/signal_processing/fft.vhd

     use work.task.all;
 	 use work.float.all;
 
+
 entity fft is
   generic (
 
     );
 end entity fft;
 
+
 architecture rtl of fft is
 
     signal current_task_state : work.task.State;
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+    component fftmain is
+           -- generic( width : integer := 32
+            --);
+            port(
+                    clock: in std_logic;
+                    reset: in std_logic;
+                    di_en: in std_logic;
+                    di_re: in std_logic_vector(input_data_width-1 downto 0);
+                    di_im: in std_logic_vector(input_data_width-1 downto 0);
+                    do_en: out std_logic;
+                    do_re: out std_logic_vector(output_data_width-1 downto 0);
+                    do_im: out std_logic_vector(output_data_width-1 downto 0)
+                );
+    end component;
+
+    -- Zustände für die Zustandsmaschine zur Berechnung
+    type SigState is (
+	SIG_IDLE,
+	SIG_READ,
+	SIG_FFTMAIN,
+	SIG_FFTMAG,
+	SIG_WRITE
+    );
+    signal current_sig_state : SigState;
+    signal next_sig_state : SigState;
+
+    signal fftmain_start : std_logic;
+    signal fftmain_done : std_logic;
+    signal fftmag_start : std_logic;
+    signal fftmag_done : std_logic;
+    signal fftmain_out_re : std_logic_vector( 31 downto 0 );
+    signal fftmain_out_im : std_logic_vector( 31 downto 0 );
+    
+    signal exp : std_logic_vector( 7 downto 0);
+    signal scaled_exp : std_logic_vector( 7 downto 0);
+    signal scaled_readdata : std_logic_vector( 31 downto 0);
+    signal exp_int : integer;
+    signal scaled_data_fixp : std_logic_vector(31 downto 0);
+
+    signal exp2 : std_logic_vector( 7 downto 0);
+    signal scaled_exp2 : std_logic_vector( 7 downto 0);
+    signal exp_int2 : integer;
+
+    signal magnitude_output : std_logic_vector( 31 downto 0 );
+    signal writedata_float : std_logic_vector( 31 downto 0 );
+
+    type std_logic_vector_array is array (0 to 1023) of std_logic_vector(31 downto 0);
+    signal my_array : std_logic_vector_array;
+
+
 begin
+
+	exp <= signal_readdata( 30 downto 23 );
+	exp_int <= to_integer(unsigned(exp));
+        scaled_exp <= std_logic_vector(to_unsigned(exp_int - 4, 8));
+	scaled_readdata <= signal_readdata( 31 ) & scaled_exp & signal_readdata( 22 downto 0 ); 
+	scaled_data_fixp <= to_fixed(scaled_readdata);
+
+	writedata_float <= to_float(magnitude_output);
+        exp2 <= writedata_float( 30 downto 23 );
+	exp_int2 <= to_integer(unsigned(exp2));
+        scaled_exp2 <= std_logic_vector(to_unsigned(exp_int2 + 5, 8));
+        my_array(1023 - index) <= writedata_float( 31 ) & scaled_exp2 & writedata_float( 22 downto 0 );
+	signal_writedata <= my_array(index);
+    
+    u_fft : fftmain
+    port map (
+	clock => clk,
+	reset => reset,
+	di_en => fftmain_start,
+	di_re => scaled_data_fixp,
+	di_im => x"00000000",
+	do_en => fftmain_done,
+	do_re => fftmain_out_re,
+	do_im => fftmain_out_im
+	);
+
+    
+    u_fft_mag_calc : entity work.fft_magnitude_calc
+    port map (
+	clk => clk,
+	reset => reset,
+	input_valid => fftmag_start,
+	input_re => fftmain_out_re,
+	input_im => fftmain_out_im,
+	output_valid => fftmag_done,
+	output_magnitude => magnitude_output
+	);
+
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
         end case;
     end process task_state_transitions;
 
+    sig_state_transitions : process (all) is
+    begin
+	next_sig_state <= current_sig_state;
+	case current_sig_state is
+		when SIG_IDLE =>
+		   if ( current_task_state = work.task.TASK_RUNNING ) then
+			next_sig_state <= SIG_READ;
+		   end if;
+		when SIG_READ =>
+			next_sig_state <= SIG_FFTMAIN;
+		when SIG_FFTMAIN =>
+		    if ( fftmain_done = '1') then
+			next_sig_state <= SIG_FFTMAG;
+		    end if;
+		when SIG_FFTMAG =>
+		    if ( fftmain_done = '0') then
+			next_sig_state <= SIG_WRITE;
+		    end if;
+		when SIG_WRITE =>
+			null;
+	end case;
+    end process sig_state_transitions;
+
     sync : process ( clk, reset ) is
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
-            index <= 0;
-        elsif ( rising_edge( clk ) ) then
-            current_task_state <= next_task_state;
+	    current_sig_state <= SIG_IDLE;
+	    index <= 0;
+	    signal_read <= '0';
+	    fftmain_start <= '0';
+	    fftmag_start <= '0';
+	    signal_write <= '0';
+        
+	elsif ( rising_edge( clk ) ) then
+	    current_task_state <= next_task_state;
             case next_task_state is
             when work.task.TASK_IDLE =>
-                index <= 0;
-                signal_write <= '0';
+                null;
             when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
+                null;
             when work.task.TASK_DONE =>
-                index <= 0;
-                signal_write <= '0';
+                null;
+            end case;
+
+	    current_sig_state <= next_sig_state;
+            case next_sig_state is
+		    when SIG_IDLE =>
+		        signal_write <= '0';
+		    when SIG_READ =>
+		        signal_read <= '1';
+		    when SIG_FFTMAIN =>
+		        fftmain_start <= '1';
+		    when SIG_FFTMAG =>
+			signal_read <= '0';
+			fftmain_start <= '0';
+		        fftmag_start <= '1';
+			signal_write <= '0';
+			index <= index + 1;
+		    when SIG_WRITE =>
+			fftmag_start <= '0';
+			signal_write <= '1';
+			
             end case;
         end if;
     end process sync;

software/signal_processing/add.c

 
 int task_add_run( void * task ) {
 
-    // TODO
+    add_config * config = (add_config *) task;
+	
+    float_word f;
+
+    for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; i++)
+    {
+	float a;
+	data_channel_read(config->sources[0], (uint32_t *) & a);
+	
+	float b;
+	data_channel_read(config->sources[1], (uint32_t *) & b);
+
+	float_word c;
+	c.value = a + b;
+	f.value = c.value;
+	data_channel_write(config->sink, c.word);	
+    }
 
     return 0;
 }

software/signal_processing/fft.c

 #include "system/data_channel.h"
 #include "system/Complex.h"
 #include "system/float_word.h"
+#include <math.h>
+#include <complex.h>
+#include <stdio.h>
 
-int task_fft_run( void * task ) {
+void fft_radix4(complex float *x) {
+    int n = DATA_CHANNEL_DEPTH;
+    int stages = log(n) / log(4);  // Anzahl der FFT-Stufen
 
-    // TODO
+    // Bit-Reversal-Rearrangement (Umordnung der Daten für FFT)
+    for (int i = 0; i < n; i++) {
+        int rev = 0, num = i;
+        for (int bit = 0; bit < stages; bit++) {
+            rev = rev * 4 + (num % 4);
+	    //printf("i: %d, rev: %d\n", i, rev);
+            num /= 4;
+        }
+        if (i < rev) {
+            complex float temp = x[i];
+            x[i] = x[rev];
+            x[rev] = temp;
+        }
+    }
 
+    // Radix-4 Butterfly-Berechnung
+    for (int s = 1; s <= stages; s++) {
+        int m = pow(4, s);      // Gruppengröße (4^s)
+        int quarter_m = m / 4;  // Viertel der Gruppengröße
+        float theta = -2.0f * M_PI / m;  // Grundwinkel der Wurzeln der Einheit
+	//printf("Stage: %d, m: %d, theta: %f\n", s, m, theta);
+
+        for (int k = 0; k < n; k += m) {  // Iteration über Gruppen
+            for (int j = 0; j < quarter_m; j++) {  // Innerhalb der Gruppe
+                // Wurzeln der Einheit
+                complex float w0 = 1.0f;  // Wurzel für j = 0
+                complex float w1 = cexpf(I * theta * j);      // Wurzel für j = 1
+                complex float w2 = cexpf(I * theta * 2 * j);  // Wurzel für j = 2
+                complex float w3 = cexpf(I * theta * 3 * j);  // Wurzel für j = 3
+
+                // Lade die Werte aus der Gruppe
+                complex float t0 = x[k + j];
+                complex float t1 = x[k + j + quarter_m] * w1;
+                complex float t2 = x[k + j + 2 * quarter_m] * w2;
+                complex float t3 = x[k + j + 3 * quarter_m] * w3;
+		//printf("w1: %f + %fi, w2: %f + %fi, w3: %f + %fi\n", crealf(w1), cimagf(w1), crealf(w2), cimagf(w2), crealf(w3), cimagf(w3));
+
+		//printf("Before: t0: %f + %fi, t1: %f + %fi, t2: %f + %fi, t3: %f + %fi\n", crealf(t0), cimagf(t0), crealf(t1), cimagf(t1), crealf(t2), cimagf(t2), crealf(t3), cimagf(t3));
+                // Butterfly-Operationen
+                x[k + j] = t0 + t1 + t2 + t3;
+                x[k + j + quarter_m] = t0 - t1 + I * (t3 - t2);
+                x[k + j + 2 * quarter_m] = t0 - t2 + t1 - t3;
+                x[k + j + 3 * quarter_m] = t0 - t1 - I * (t3 - t2);
+		//printf("After: x[%d]: %f + %fi, x[%d]: %f + %fi\n", k + j, crealf(x[k + j]), cimagf(x[k + j]), k + j + quarter_m, crealf(x[k + j + quarter_m]), cimagf(x[k + j + quarter_m]));
+            }
+        }
+    }
+}
+
+
+
+int task_fft_run(void *task) {
+
+    fft_config *config = (fft_config *)task;
+    complex float x[DATA_CHANNEL_DEPTH];
+    float c[DATA_CHANNEL_DEPTH];
+    
+    for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
+        float a;
+        data_channel_read(config->base.sources[0], (uint32_t *) &a);
+        x[i] = a;
+	//printf("Input x[%d] = %f + %fi\n", i, crealf(x[i]), cimagf(x[i]));
+    }
+
+    fft_radix4(x);
+
+    for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
+	//printf("Output complex x[%d] = %f + %fi\n", i, crealf(x[i]), cimagf(x[i]));
+	c[i] = sqrt(pow(crealf(x[i]), 2) + pow(cimagf(x[i]), 2));	// Betrag
+	if (i == 0)
+	    c[i] = c[i] * 1/DATA_CHANNEL_DEPTH;	// Sklaierung
+	else
+	   c[i] = c[i] * 2/DATA_CHANNEL_DEPTH;	// Sklaierung
+	printf("Output Magnitude skaliert c[%d] = %f\n", i, c [i]);
+
+	float_word output;
+	output.value = c[i];	
+
+        data_channel_write(config->base.sink, output.word);
+    }
+   
     return 0;
 }
 
+