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Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design

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sessleral71711 2022-06-14 12:32:53 +02:00
commit 730cc895b1
1 changed files with 11 additions and 0 deletions
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Top/Top.sv
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@ -2,6 +2,7 @@
`include "../fsm/Fsm.sv"
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>>>>>>> b8d8341 (Initalized top level design)
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@ -11,6 +12,10 @@
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`include "../timer_port/timer_top.sv"
>>>>>>> 026899b (Added parallelport, timer and ampelsteuerung)
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`include "../Bus_if/Bus_if.sv"
`include "../timer_port/timer_top.sv"
>>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
module Top(
input wire clk,
@ -26,8 +31,11 @@ module Top(
// FSM
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>>>>>>> b8d8341 (Initalized top level design)
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>>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
Fsm fsm(
.clk(clk),
.inAlarmAmpel(bus.AlarmAmpel),
@ -37,7 +45,10 @@ module Top(
.outSendData(bus.SendData),
.outTimerEN(bus.TimerEN)
);
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>>>>>>> c93bdaf (Added bus_if and fsm to top level design)
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>>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
// Parallelport
parallelport parallelport1 (
.inClk(clk),