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  1. # // Questa Sim-64
  2. # // Version 2019.4 linux_x86_64 Oct 15 2019
  3. # //
  4. # // Copyright 1991-2019 Mentor Graphics Corporation
  5. # // All Rights Reserved.
  6. # //
  7. # // QuestaSim and its associated documentation contain trade
  8. # // secrets and commercial or financial information that are the property of
  9. # // Mentor Graphics Corporation and are privileged, confidential,
  10. # // and exempt from disclosure under the Freedom of Information Act,
  11. # // 5 U.S.C. Section 552. Furthermore, this information
  12. # // is prohibited from disclosure under the Trade Secrets Act,
  13. # // 18 U.S.C. Section 1905.
  14. # //
  15. do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
  16. #
  17. # create workspace
  18. # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
  19. # ** Warning: (vlib-34) Library already exists at "work".
  20. # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
  21. # vmap work ./work
  22. # Modifying modelsim.ini
  23. #
  24. # Compile sv-Designfiles
  25. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  26. # Start time: 14:45:50 on Jun 15,2023
  27. # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
  28. # -- Compiling interface led_if
  29. # -- Compiling interface dip_if
  30. # -- Compiling interface fram_if
  31. # -- Compiling interface clock_if
  32. #
  33. # Top level modules:
  34. # --none--
  35. # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
  36. # Errors: 0, Warnings: 0
  37. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  38. # Start time: 14:45:50 on Jun 15,2023
  39. # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
  40. # -- Compiling module stimuli
  41. #
  42. # Top level modules:
  43. # stimuli
  44. # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
  45. # Errors: 0, Warnings: 0
  46. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  47. # Start time: 14:45:50 on Jun 15,2023
  48. # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
  49. # -- Compiling module top
  50. # -- Compiling interface bus
  51. # -- Compiling module parallelport
  52. # -- Compiling module steuerung
  53. #
  54. # Top level modules:
  55. # top
  56. # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
  57. # Errors: 0, Warnings: 0
  58. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  59. # Start time: 14:45:50 on Jun 15,2023
  60. # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
  61. # -- Compiling module top_tb
  62. #
  63. # Top level modules:
  64. # top_tb
  65. # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
  66. # Errors: 0, Warnings: 0
  67. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  68. # Start time: 14:45:51 on Jun 15,2023
  69. # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
  70. # -- Compiling module timer
  71. #
  72. # Top level modules:
  73. # timer
  74. # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
  75. # Errors: 0, Warnings: 0
  76. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  77. # Start time: 14:45:51 on Jun 15,2023
  78. # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
  79. # -- Compiling module SPI_Master
  80. #
  81. # Top level modules:
  82. # SPI_Master
  83. # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
  84. # Errors: 0, Warnings: 0
  85. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  86. # Start time: 14:45:51 on Jun 15,2023
  87. # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
  88. # -- Compiling module SPI_Master_With_Single_CS
  89. #
  90. # Top level modules:
  91. # SPI_Master_With_Single_CS
  92. # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
  93. # Errors: 0, Warnings: 0
  94. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  95. # Start time: 14:45:51 on Jun 15,2023
  96. # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
  97. # -- Compiling module FRAM
  98. #
  99. # Top level modules:
  100. # FRAM
  101. # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
  102. # Errors: 0, Warnings: 0
  103. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  104. # Start time: 14:45:51 on Jun 15,2023
  105. # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
  106. # -- Compiling module spi
  107. #
  108. # Top level modules:
  109. # spi
  110. # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
  111. # Errors: 0, Warnings: 0
  112. #
  113. # Run Simulation
  114. # vsim -cvg63 -voptargs=""+acc"" top_tb
  115. # Start time: 14:45:51 on Jun 15,2023
  116. # ** Note: (vsim-3812) Design is being optimized...
  117. # ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)".
  118. # Loading sv_std.std
  119. # Loading work.top_tb(fast)
  120. # Loading work.led_if(fast)
  121. # Loading work.dip_if(fast)
  122. # Loading work.fram_if(fast)
  123. # Loading work.clock_if(fast)
  124. # Loading work.top(fast)
  125. # Loading work.bus(fast)
  126. # Loading work.timer(fast)
  127. # Loading work.steuerung(fast)
  128. # Loading work.spi(fast)
  129. # Loading work.FRAM(fast)
  130. # Loading work.SPI_Master_With_Single_CS(fast)
  131. # Loading work.SPI_Master(fast)
  132. # Loading work.parallelport(fast)
  133. # Loading work.stimuli(fast)
  134. do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
  135. #
  136. # create workspace
  137. # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
  138. # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
  139. # ** Warning: (vlib-34) Library already exists at "work".
  140. # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
  141. # vmap work ./work
  142. # Modifying modelsim.ini
  143. #
  144. # Compile sv-Designfiles
  145. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  146. # Start time: 14:48:17 on Jun 15,2023
  147. # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
  148. # -- Compiling interface led_if
  149. # -- Compiling interface dip_if
  150. # -- Compiling interface fram_if
  151. # -- Compiling interface clock_if
  152. #
  153. # Top level modules:
  154. # --none--
  155. # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
  156. # Errors: 0, Warnings: 0
  157. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  158. # Start time: 14:48:17 on Jun 15,2023
  159. # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
  160. # -- Compiling module stimuli
  161. #
  162. # Top level modules:
  163. # stimuli
  164. # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
  165. # Errors: 0, Warnings: 0
  166. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  167. # Start time: 14:48:17 on Jun 15,2023
  168. # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
  169. # -- Compiling module top
  170. # -- Compiling interface bus
  171. # -- Compiling module parallelport
  172. # -- Compiling module steuerung
  173. #
  174. # Top level modules:
  175. # top
  176. # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
  177. # Errors: 0, Warnings: 0
  178. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  179. # Start time: 14:48:17 on Jun 15,2023
  180. # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
  181. # -- Compiling module top_tb
  182. #
  183. # Top level modules:
  184. # top_tb
  185. # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
  186. # Errors: 0, Warnings: 0
  187. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  188. # Start time: 14:48:17 on Jun 15,2023
  189. # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
  190. # -- Compiling module timer
  191. #
  192. # Top level modules:
  193. # timer
  194. # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
  195. # Errors: 0, Warnings: 0
  196. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  197. # Start time: 14:48:17 on Jun 15,2023
  198. # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
  199. # -- Compiling module SPI_Master
  200. #
  201. # Top level modules:
  202. # SPI_Master
  203. # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
  204. # Errors: 0, Warnings: 0
  205. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  206. # Start time: 14:48:17 on Jun 15,2023
  207. # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
  208. # -- Compiling module SPI_Master_With_Single_CS
  209. #
  210. # Top level modules:
  211. # SPI_Master_With_Single_CS
  212. # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
  213. # Errors: 0, Warnings: 0
  214. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  215. # Start time: 14:48:17 on Jun 15,2023
  216. # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
  217. # -- Compiling module FRAM
  218. #
  219. # Top level modules:
  220. # FRAM
  221. # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
  222. # Errors: 0, Warnings: 0
  223. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  224. # Start time: 14:48:17 on Jun 15,2023
  225. # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
  226. # -- Compiling module spi
  227. #
  228. # Top level modules:
  229. # spi
  230. # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
  231. # Errors: 0, Warnings: 0
  232. #
  233. # Run Simulation
  234. # End time: 14:48:18 on Jun 15,2023, Elapsed time: 0:02:27
  235. # Errors: 3, Warnings: 2
  236. # vsim -cvg63 -voptargs=""+acc"" top_tb
  237. # Start time: 14:48:18 on Jun 15,2023
  238. # ** Note: (vsim-3813) Design is being optimized due to module recompilation...
  239. # Loading sv_std.std
  240. # Loading work.top_tb(fast)
  241. # Loading work.led_if(fast)
  242. # Loading work.dip_if(fast)
  243. # Loading work.fram_if(fast)
  244. # Loading work.clock_if(fast)
  245. # Loading work.top(fast)
  246. # Loading work.bus(fast)
  247. # Loading work.timer(fast)
  248. # Loading work.steuerung(fast)
  249. # Loading work.spi(fast)
  250. # Loading work.FRAM(fast)
  251. # Loading work.SPI_Master_With_Single_CS(fast)
  252. # Loading work.SPI_Master(fast)
  253. # Loading work.parallelport(fast)
  254. # Loading work.stimuli(fast)
  255. add wave -position insertpoint \
  256. sim:/top_tb/t1/fpga_bus/spi_read
  257. do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
  258. #
  259. # create workspace
  260. # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
  261. # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
  262. # ** Warning: (vlib-34) Library already exists at "work".
  263. # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
  264. # vmap work ./work
  265. # Modifying modelsim.ini
  266. #
  267. # Compile sv-Designfiles
  268. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  269. # Start time: 14:51:02 on Jun 15,2023
  270. # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
  271. # -- Compiling interface led_if
  272. # -- Compiling interface dip_if
  273. # -- Compiling interface fram_if
  274. # -- Compiling interface clock_if
  275. #
  276. # Top level modules:
  277. # --none--
  278. # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
  279. # Errors: 0, Warnings: 0
  280. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  281. # Start time: 14:51:02 on Jun 15,2023
  282. # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
  283. # -- Compiling module stimuli
  284. #
  285. # Top level modules:
  286. # stimuli
  287. # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
  288. # Errors: 0, Warnings: 0
  289. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  290. # Start time: 14:51:02 on Jun 15,2023
  291. # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
  292. # -- Compiling module top
  293. # -- Compiling interface bus
  294. # -- Compiling module parallelport
  295. # -- Compiling module steuerung
  296. #
  297. # Top level modules:
  298. # top
  299. # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
  300. # Errors: 0, Warnings: 0
  301. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  302. # Start time: 14:51:02 on Jun 15,2023
  303. # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
  304. # -- Compiling module top_tb
  305. #
  306. # Top level modules:
  307. # top_tb
  308. # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
  309. # Errors: 0, Warnings: 0
  310. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  311. # Start time: 14:51:02 on Jun 15,2023
  312. # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
  313. # -- Compiling module timer
  314. #
  315. # Top level modules:
  316. # timer
  317. # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
  318. # Errors: 0, Warnings: 0
  319. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  320. # Start time: 14:51:02 on Jun 15,2023
  321. # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
  322. # -- Compiling module SPI_Master
  323. #
  324. # Top level modules:
  325. # SPI_Master
  326. # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
  327. # Errors: 0, Warnings: 0
  328. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  329. # Start time: 14:51:02 on Jun 15,2023
  330. # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
  331. # -- Compiling module SPI_Master_With_Single_CS
  332. #
  333. # Top level modules:
  334. # SPI_Master_With_Single_CS
  335. # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
  336. # Errors: 0, Warnings: 0
  337. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  338. # Start time: 14:51:02 on Jun 15,2023
  339. # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
  340. # -- Compiling module FRAM
  341. #
  342. # Top level modules:
  343. # FRAM
  344. # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
  345. # Errors: 0, Warnings: 0
  346. # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
  347. # Start time: 14:51:02 on Jun 15,2023
  348. # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
  349. # -- Compiling module spi
  350. #
  351. # Top level modules:
  352. # spi
  353. # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
  354. # Errors: 0, Warnings: 0
  355. #
  356. # Run Simulation
  357. # End time: 14:51:07 on Jun 15,2023, Elapsed time: 0:02:49
  358. # Errors: 1, Warnings: 2
  359. # vsim -cvg63 -voptargs=""+acc"" top_tb
  360. # Start time: 14:51:07 on Jun 15,2023
  361. # ** Note: (vsim-8009) Loading existing optimized design _opt1
  362. # Loading sv_std.std
  363. # Loading work.top_tb(fast)
  364. # Loading work.led_if(fast)
  365. # Loading work.dip_if(fast)
  366. # Loading work.fram_if(fast)
  367. # Loading work.clock_if(fast)
  368. # Loading work.top(fast)
  369. # Loading work.bus(fast)
  370. # Loading work.timer(fast)
  371. # Loading work.steuerung(fast)
  372. # Loading work.spi(fast)
  373. # Loading work.FRAM(fast)
  374. # Loading work.SPI_Master_With_Single_CS(fast)
  375. # Loading work.SPI_Master(fast)
  376. # Loading work.parallelport(fast)
  377. # Loading work.stimuli(fast)
  378. # End time: 14:52:23 on Jun 15,2023, Elapsed time: 0:01:16
  379. # Errors: 3, Warnings: 0