uebung_projekt
This commit is contained in:
hans
@@ -0,0 +1,197 @@
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module FRAM(
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input i_clk, //Module (Module CLock = SPI Clock)
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input i_nreset,
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input logic [19:0] i_adr, //Memorycell adress in FRAM
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input logic [7:0] i_data, //data to write
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output logic [7:0] o_data, //data to read
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input logic i_rw, //Read = 1, Write = 0
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input logic i_status, //If 1 Read Staut register
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input logic i_hbn, //If 1 FRAM will enter Hibernation Mode
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input logic i_cready, //Starts transmission
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output logic o_busy, //Indicates FRAM Busy
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// SPI Interface
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output o_SPI_Clk,
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input i_SPI_MISO,
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output o_SPI_MOSI,
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output o_SPI_CS_n
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);
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//FRAM SPI OP Codes
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//Write Enable Control
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localparam WREN = 8'h06; //Set Write enable latch
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localparam WRDI = 8'h04; //Reset write enable latch
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//Register Access
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localparam RDSR = 8'h05; //Read Status Register
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localparam WRSR = 8'h01; //Write Status Register
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//Memory Write
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localparam WRITE = 8'h02; //Write Memory Data
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//Memory Read
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localparam READ = 8'h03; //Read Memory Data
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localparam FSTRT = 8'h0B; //Fast read memory Data
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//Special Sector Memory Access
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localparam SSWR = 8'h42; //Spcial Sector Write
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localparam SSRD = 8'h4B; //Special Sector Read
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//Identification and serial Number
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localparam RDID = 8'h9F; //Read Device ID
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localparam RUID = 8'h4C; //Read Unique ID
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localparam WRSN = 8'hC2; //Write Serial Number
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localparam RDSN = 8'hC3; //Read Serial Number
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//Low Power Modes
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localparam DPD = 8'hBA; // Enter Deep Power-Down
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localparam HBN = 8'hB9; // Enter Hibernate Mode
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//end FRAM SPI OP Codes
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//Controller Specific
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logic [3:0] state;
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// SPI Specific
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parameter SPI_MODE = 0; // CPOL = 0, CPHA = 0
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parameter CLKS_PER_HALF_BIT = 2; // 25MHz
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parameter MAX_BYTES_PER_CS = 5; // 5 bytes max per chip select cycle
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parameter CS_INACTIVE_CLKS = 1; // Adds delay (1clk) between cycles
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logic [7:0] r_Master_TX_Byte = 0;
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logic r_Master_TX_DV = 1'b0;
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logic w_Master_TX_Ready;
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logic w_Master_RX_DV;
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logic [7:0] w_Master_RX_Byte;
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logic [$clog2(MAX_BYTES_PER_CS+1)-1:0] w_Master_RX_Count, r_Master_TX_Count = 3'h1; //Standard 1 Byte pro CS Cycle
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SPI_Master_With_Single_CS
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#(.SPI_MODE(SPI_MODE), //SPI Mode 0-3
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.CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT), //sets Frequency of SPI_CLK
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.MAX_BYTES_PER_CS(MAX_BYTES_PER_CS), //Maximum Bytes per CS Cycle
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.CS_INACTIVE_CLKS(CS_INACTIVE_CLKS) //Amount of Time holding CS Low befor next command
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) SPI
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(
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// Control/Data Signals,
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.i_Rst_L(i_nreset), // FPGA Reset
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.i_Clk(i_clk), // FPGA Clock
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// TX (MOSI) Signals
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.i_TX_Count(r_Master_TX_Count), // Number of bytes per CS
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.i_TX_Byte(r_Master_TX_Byte), // Byte to transmit on MOSI
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.i_TX_DV(r_Master_TX_DV), // Data Valid Pulse with i_TX_Byte
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.o_TX_Ready(w_Master_TX_Ready), // Transmit Ready for Byte
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// RX (MISO) Signals
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.o_RX_Count(w_Master_RX_Count), // Index of RX'd byte
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.o_RX_DV(w_Master_RX_DV), // Data Valid pulse (1 clock cycle)
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.o_RX_Byte(w_Master_RX_Byte), // Byte received on MISO
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// SPI Interface
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.o_SPI_Clk(o_SPI_Clk),
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.i_SPI_MISO(i_SPI_MISO),
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.o_SPI_MOSI(o_SPI_MOSI),
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.o_SPI_CS_n(o_SPI_CS_n)
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);
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//end SPI Specific
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task SPI_SendByte(input [7:0] data);
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@(posedge i_clk);
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r_Master_TX_Byte <= data;
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r_Master_TX_DV <= 1'b1;
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@(posedge i_clk);
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r_Master_TX_DV <= 1'b0;
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@(posedge i_clk);
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@(posedge w_Master_TX_Ready);
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endtask //end SPI_SendByte
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//FRAM Tasks
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task FRAM_Write(input [19:0] adr, input [7:0] data); //vgl. Fig.11
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logic [7:0] value;
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value <= 8'h0;
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//Set Write Enable
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r_Master_TX_Count <= 3'b1; //1Byte Transaction
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SPI_SendByte(WREN);
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//Write to fram
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r_Master_TX_Count <= 3'h5; //5 Byte Transaction
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SPI_SendByte(WRITE); //OPCode
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SPI_SendByte({4'hF,adr[19:16]}); //Adress [23-16]
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SPI_SendByte(adr[15:8]); //Adress [15-8]
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SPI_SendByte(adr[7:0]); //Adress [7-0]
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SPI_SendByte(data); //Data [7:0]
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//Reset Write Disable and Verify
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do begin
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r_Master_TX_Count <= 3'b1; //1Byte Transaction
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SPI_SendByte(WRDI); //Set Write Disable
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FRAM_Read_Status(value); //Lese Status Register
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end while(((value & 8'h2) >> 1) != 0);
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endtask //end FRAM_Write
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task FRAM_Read(input [19:0] adr, output [7:0] data); //vgl. Fig12
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r_Master_TX_Count <= 3'h5; //5 Byte Transaction
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SPI_SendByte(READ); //Opcode
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SPI_SendByte({4'hF,adr[19:16]}); //Adress [23-16]
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SPI_SendByte(adr[15:8]); //Adress [15-8]
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SPI_SendByte(adr[7:0]); //Adress [7-0]
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SPI_SendByte(8'hAA); //Dummy Bits, read byte in w_Master_RX_Byte
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data = w_Master_RX_Byte;
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endtask //end FRAM_READ
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task FRAM_Read_Status(output [7:0] data); //vgl. Fig9
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r_Master_TX_Count <= 3'h2; //2 Byte Transaction
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SPI_SendByte(RDSR); //OpCode
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SPI_SendByte(8'hFD); //Dummy Bits, read byte in w_Master_RX_Byte
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data = w_Master_RX_Byte;
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endtask //FRAM_Read_Status
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task FRAM_Hibernation(); //vgl. Fig22
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r_Master_TX_Count <= 3'h1; //1 Byte Transaction
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SPI_SendByte(HBN);
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endtask //FRAM_Hibernation
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//end FRAM Tasks
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always @(posedge i_clk or negedge i_nreset) begin
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state[0] = i_cready;
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state[1] = i_hbn;
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state[2] = i_status;
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state[3] = i_rw;
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if(~i_nreset) begin //Modul Reset
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o_data <= 8'h00;
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end //end if
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if(w_Master_TX_Ready) begin
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case(state) inside
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4'b??11: FRAM_Hibernation();
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4'b?101: FRAM_Read_Status(o_data);
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4'b1001: FRAM_Read(i_adr, o_data);
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4'b0001: FRAM_Write(i_adr, i_data);
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default:;
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endcase //endcase
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end //endif
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end //end always
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assign o_busy = w_Master_TX_Ready;
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endmodule
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@@ -0,0 +1,188 @@
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///////////////////////////////////////////////////////////////////////////////
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//Source: https://github.com/nandland/spi-master/tree/master/Verilog/source
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//Description: SPI (Serial Peripheral Interface) Master
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// With single chip-select (AKA Slave Select) capability
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//
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// Supports arbitrary length byte transfers.
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//
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// Instantiates a SPI Master and adds single CS.
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// If multiple CS signals are needed, will need to use different
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// module, OR multiplex the CS from this at a higher level.
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//
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// Note: i_Clk must be at least 2x faster than i_SPI_Clk
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//
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// Parameters: SPI_MODE, can be 0, 1, 2, or 3. See above.
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// Can be configured in one of 4 modes:
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// Mode | Clock Polarity (CPOL/CKP) | Clock Phase (CPHA)
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// 0 | 0 | 0
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// 1 | 0 | 1
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// 2 | 1 | 0
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// 3 | 1 | 1
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//
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// CLKS_PER_HALF_BIT - Sets frequency of o_SPI_Clk. o_SPI_Clk is
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// derived from i_Clk. Set to integer number of clocks for each
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// half-bit of SPI data. E.g. 100 MHz i_Clk, CLKS_PER_HALF_BIT = 2
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// would create o_SPI_CLK of 25 MHz. Must be >= 2
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//
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// MAX_BYTES_PER_CS - Set to the maximum number of bytes that
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// will be sent during a single CS-low pulse.
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//
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// CS_INACTIVE_CLKS - Sets the amount of time in clock cycles to
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// hold the state of Chip-Selct high (inactive) before next
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// command is allowed on the line. Useful if chip requires some
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// time when CS is high between trasnfers.
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///////////////////////////////////////////////////////////////////////////////
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module SPI_Master_With_Single_CS
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#(parameter SPI_MODE = 0,
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parameter CLKS_PER_HALF_BIT = 2,
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parameter MAX_BYTES_PER_CS = 1,
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parameter CS_INACTIVE_CLKS = 1)
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(
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// Control/Data Signals,
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input i_Rst_L, // FPGA Reset
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input i_Clk, // FPGA Clock
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// TX (MOSI) Signals
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input [$clog2(MAX_BYTES_PER_CS+1)-1:0] i_TX_Count, // # bytes per CS low
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input [7:0] i_TX_Byte, // Byte to transmit on MOSI
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input i_TX_DV, // Data Valid Pulse with i_TX_Byte
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output o_TX_Ready, // Transmit Ready for next byte
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// RX (MISO) Signals
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output reg [$clog2(MAX_BYTES_PER_CS+1)-1:0] o_RX_Count, // Index RX byte
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output o_RX_DV, // Data Valid pulse (1 clock cycle)
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output [7:0] o_RX_Byte, // Byte received on MISO
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// SPI Interface
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output o_SPI_Clk,
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input i_SPI_MISO,
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output o_SPI_MOSI,
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output o_SPI_CS_n
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);
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localparam IDLE = 2'b00;
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localparam TRANSFER = 2'b01;
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localparam CS_INACTIVE = 2'b10;
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reg [1:0] r_SM_CS;
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reg r_CS_n;
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reg [$clog2(CS_INACTIVE_CLKS)-1:0] r_CS_Inactive_Count;
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reg [$clog2(MAX_BYTES_PER_CS+1)-1:0] r_TX_Count;
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wire w_Master_Ready;
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// Instantiate Master
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SPI_Master
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#(.SPI_MODE(SPI_MODE),
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.CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT)
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) SPI_Master_Inst
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(
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// Control/Data Signals,
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.i_Rst_L(i_Rst_L), // FPGA Reset
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.i_Clk(i_Clk), // FPGA Clock
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// TX (MOSI) Signals
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.i_TX_Byte(i_TX_Byte), // Byte to transmit
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.i_TX_DV(i_TX_DV), // Data Valid Pulse
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.o_TX_Ready(w_Master_Ready), // Transmit Ready for Byte
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// RX (MISO) Signals
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.o_RX_DV(o_RX_DV), // Data Valid pulse (1 clock cycle)
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.o_RX_Byte(o_RX_Byte), // Byte received on MISO
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// SPI Interface
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.o_SPI_Clk(o_SPI_Clk),
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.i_SPI_MISO(i_SPI_MISO),
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.o_SPI_MOSI(o_SPI_MOSI)
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);
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// Purpose: Control CS line using State Machine
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always @(posedge i_Clk or negedge i_Rst_L)
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begin
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if (~i_Rst_L)
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begin
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r_SM_CS <= IDLE;
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r_CS_n <= 1'b1; // Resets to high
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r_TX_Count <= 0;
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r_CS_Inactive_Count <= CS_INACTIVE_CLKS;
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end
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else
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begin
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case (r_SM_CS)
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IDLE:
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begin
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if (r_CS_n & i_TX_DV) // Start of transmission
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begin
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r_TX_Count <= i_TX_Count - 1; // Register TX Count
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r_CS_n <= 1'b0; // Drive CS low
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r_SM_CS <= TRANSFER; // Transfer bytes
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end
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end
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TRANSFER:
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begin
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// Wait until SPI is done transferring do next thing
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if (w_Master_Ready)
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begin
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if (r_TX_Count > 0)
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begin
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if (i_TX_DV)
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begin
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r_TX_Count <= r_TX_Count - 1;
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end
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end
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else
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begin
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r_CS_n <= 1'b1; // we done, so set CS high
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r_CS_Inactive_Count <= CS_INACTIVE_CLKS;
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r_SM_CS <= CS_INACTIVE;
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end // else: !if(r_TX_Count > 0)
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end // if (w_Master_Ready)
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end // case: TRANSFER
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CS_INACTIVE:
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begin
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if (r_CS_Inactive_Count > 0)
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begin
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r_CS_Inactive_Count <= r_CS_Inactive_Count - 1'b1;
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end
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else
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begin
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r_SM_CS <= IDLE;
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end
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end
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default:
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begin
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r_CS_n <= 1'b1; // we done, so set CS high
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r_SM_CS <= IDLE;
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end
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endcase // case (r_SM_CS)
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end
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end // always @ (posedge i_Clk or negedge i_Rst_L)
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// Purpose: Keep track of RX_Count
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always @(posedge i_Clk)
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begin
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begin
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if (r_CS_n)
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begin
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o_RX_Count <= 0;
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end
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else if (o_RX_DV)
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begin
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o_RX_Count <= o_RX_Count + 1'b1;
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end
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end
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end
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assign o_SPI_CS_n = r_CS_n;
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assign o_TX_Ready = ((r_SM_CS == IDLE) | (r_SM_CS == TRANSFER && w_Master_Ready == 1'b1 && r_TX_Count > 0)) & ~i_TX_DV;
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endmodule // SPI_Master_With_Single_CS
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@@ -0,0 +1,240 @@
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//////////////////////////////////////////////////////////////////////////////
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//Source: https://github.com/nandland/spi-master/tree/master/Verilog/source
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// Description: SPI (Serial Peripheral Interface) Master
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// Creates master based on input configuration.
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// Sends a byte one bit at a time on MOSI
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// Will also receive byte data one bit at a time on MISO.
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// Any data on input byte will be shipped out on MOSI.
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//
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// To kick-off transaction, user must pulse i_TX_DV.
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// This module supports multi-byte transmissions by pulsing
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// i_TX_DV and loading up i_TX_Byte when o_TX_Ready is high.
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//
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// This module is only responsible for controlling Clk, MOSI,
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// and MISO. If the SPI peripheral requires a chip-select,
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// this must be done at a higher level.
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//
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// Note: i_Clk must be at least 2x faster than i_SPI_Clk
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//
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// Parameters: SPI_MODE, can be 0, 1, 2, or 3. See above.
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// Can be configured in one of 4 modes:
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// Mode | Clock Polarity (CPOL/CKP) | Clock Phase (CPHA)
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// 0 | 0 | 0
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// 1 | 0 | 1
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// 2 | 1 | 0
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// 3 | 1 | 1
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// More: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#Mode_numbers
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// CLKS_PER_HALF_BIT - Sets frequency of o_SPI_Clk. o_SPI_Clk is
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// derived from i_Clk. Set to integer number of clocks for each
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// half-bit of SPI data. E.g. 100 MHz i_Clk, CLKS_PER_HALF_BIT = 2
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// would create o_SPI_CLK of 25 MHz. Must be >= 2
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//
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///////////////////////////////////////////////////////////////////////////////
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module SPI_Master
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#(parameter SPI_MODE = 0,
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parameter CLKS_PER_HALF_BIT = 2)
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(
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// Control/Data Signals,
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input i_Rst_L, // FPGA Reset
|
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input i_Clk, // FPGA Clock
|
||||
|
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// TX (MOSI) Signals
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input [7:0] i_TX_Byte, // Byte to transmit on MOSI
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input i_TX_DV, // Data Valid Pulse with i_TX_Byte
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output reg o_TX_Ready, // Transmit Ready for next byte
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|
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// RX (MISO) Signals
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output reg o_RX_DV, // Data Valid pulse (1 clock cycle)
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output reg [7:0] o_RX_Byte, // Byte received on MISO
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// SPI Interface
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output reg o_SPI_Clk,
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input i_SPI_MISO,
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output reg o_SPI_MOSI
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);
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// SPI Interface (All Runs at SPI Clock Domain)
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wire w_CPOL; // Clock polarity
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wire w_CPHA; // Clock phase
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reg [$clog2(CLKS_PER_HALF_BIT*2)-1:0] r_SPI_Clk_Count;
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reg r_SPI_Clk;
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reg [4:0] r_SPI_Clk_Edges;
|
||||
reg r_Leading_Edge;
|
||||
reg r_Trailing_Edge;
|
||||
reg r_TX_DV;
|
||||
reg [7:0] r_TX_Byte;
|
||||
|
||||
reg [2:0] r_RX_Bit_Count;
|
||||
reg [2:0] r_TX_Bit_Count;
|
||||
|
||||
// CPOL: Clock Polarity
|
||||
// CPOL=0 means clock idles at 0, leading edge is rising edge.
|
||||
// CPOL=1 means clock idles at 1, leading edge is falling edge.
|
||||
assign w_CPOL = (SPI_MODE == 2) | (SPI_MODE == 3);
|
||||
|
||||
// CPHA: Clock Phase
|
||||
// CPHA=0 means the "out" side changes the data on trailing edge of clock
|
||||
// the "in" side captures data on leading edge of clock
|
||||
// CPHA=1 means the "out" side changes the data on leading edge of clock
|
||||
// the "in" side captures data on the trailing edge of clock
|
||||
assign w_CPHA = (SPI_MODE == 1) | (SPI_MODE == 3);
|
||||
|
||||
|
||||
|
||||
// Purpose: Generate SPI Clock correct number of times when DV pulse comes
|
||||
always @(posedge i_Clk or negedge i_Rst_L)
|
||||
begin
|
||||
if (~i_Rst_L)
|
||||
begin
|
||||
o_TX_Ready <= 1'b0;
|
||||
r_SPI_Clk_Edges <= 0;
|
||||
r_Leading_Edge <= 1'b0;
|
||||
r_Trailing_Edge <= 1'b0;
|
||||
r_SPI_Clk <= w_CPOL; // assign default state to idle state
|
||||
r_SPI_Clk_Count <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
|
||||
// Default assignments
|
||||
r_Leading_Edge <= 1'b0;
|
||||
r_Trailing_Edge <= 1'b0;
|
||||
|
||||
if (i_TX_DV)
|
||||
begin
|
||||
o_TX_Ready <= 1'b0;
|
||||
r_SPI_Clk_Edges <= 16; // Total # edges in one byte ALWAYS 16
|
||||
end
|
||||
else if (r_SPI_Clk_Edges > 0)
|
||||
begin
|
||||
o_TX_Ready <= 1'b0;
|
||||
|
||||
if (r_SPI_Clk_Count == CLKS_PER_HALF_BIT*2-1)
|
||||
begin
|
||||
r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1;
|
||||
r_Trailing_Edge <= 1'b1;
|
||||
r_SPI_Clk_Count <= 0;
|
||||
r_SPI_Clk <= ~r_SPI_Clk;
|
||||
end
|
||||
else if (r_SPI_Clk_Count == CLKS_PER_HALF_BIT-1)
|
||||
begin
|
||||
r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1;
|
||||
r_Leading_Edge <= 1'b1;
|
||||
r_SPI_Clk_Count <= r_SPI_Clk_Count + 1;
|
||||
r_SPI_Clk <= ~r_SPI_Clk;
|
||||
end
|
||||
else
|
||||
begin
|
||||
r_SPI_Clk_Count <= r_SPI_Clk_Count + 1;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
o_TX_Ready <= 1'b1;
|
||||
end
|
||||
|
||||
|
||||
end // else: !if(~i_Rst_L)
|
||||
end // always @ (posedge i_Clk or negedge i_Rst_L)
|
||||
|
||||
|
||||
// Purpose: Register i_TX_Byte when Data Valid is pulsed.
|
||||
// Keeps local storage of byte in case higher level module changes the data
|
||||
always @(posedge i_Clk or negedge i_Rst_L)
|
||||
begin
|
||||
if (~i_Rst_L)
|
||||
begin
|
||||
r_TX_Byte <= 8'h00;
|
||||
r_TX_DV <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
r_TX_DV <= i_TX_DV; // 1 clock cycle delay
|
||||
if (i_TX_DV)
|
||||
begin
|
||||
r_TX_Byte <= i_TX_Byte;
|
||||
end
|
||||
end // else: !if(~i_Rst_L)
|
||||
end // always @ (posedge i_Clk or negedge i_Rst_L)
|
||||
|
||||
|
||||
// Purpose: Generate MOSI data
|
||||
// Works with both CPHA=0 and CPHA=1
|
||||
always @(posedge i_Clk or negedge i_Rst_L)
|
||||
begin
|
||||
if (~i_Rst_L)
|
||||
begin
|
||||
o_SPI_MOSI <= 1'b0;
|
||||
r_TX_Bit_Count <= 3'b111; // send MSb first
|
||||
end
|
||||
else
|
||||
begin
|
||||
// If ready is high, reset bit counts to default
|
||||
if (o_TX_Ready)
|
||||
begin
|
||||
r_TX_Bit_Count <= 3'b111;
|
||||
end
|
||||
// Catch the case where we start transaction and CPHA = 0
|
||||
else if (r_TX_DV & ~w_CPHA)
|
||||
begin
|
||||
o_SPI_MOSI <= r_TX_Byte[3'b111];
|
||||
r_TX_Bit_Count <= 3'b110;
|
||||
end
|
||||
else if ((r_Leading_Edge & w_CPHA) | (r_Trailing_Edge & ~w_CPHA))
|
||||
begin
|
||||
r_TX_Bit_Count <= r_TX_Bit_Count - 1;
|
||||
o_SPI_MOSI <= r_TX_Byte[r_TX_Bit_Count];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Purpose: Read in MISO data.
|
||||
always @(posedge i_Clk or negedge i_Rst_L)
|
||||
begin
|
||||
if (~i_Rst_L)
|
||||
begin
|
||||
o_RX_Byte <= 8'h00;
|
||||
o_RX_DV <= 1'b0;
|
||||
r_RX_Bit_Count <= 3'b111;
|
||||
end
|
||||
else
|
||||
begin
|
||||
|
||||
// Default Assignments
|
||||
o_RX_DV <= 1'b0;
|
||||
|
||||
if (o_TX_Ready) // Check if ready is high, if so reset bit count to default
|
||||
begin
|
||||
r_RX_Bit_Count <= 3'b111;
|
||||
end
|
||||
else if ((r_Leading_Edge & ~w_CPHA) | (r_Trailing_Edge & w_CPHA))
|
||||
begin
|
||||
o_RX_Byte[r_RX_Bit_Count] <= i_SPI_MISO; // Sample data
|
||||
r_RX_Bit_Count <= r_RX_Bit_Count - 1;
|
||||
if (r_RX_Bit_Count == 3'b000)
|
||||
begin
|
||||
o_RX_DV <= 1'b1; // Byte done, pulse Data Valid
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Purpose: Add clock delay to signals for alignment.
|
||||
always @(posedge i_Clk or negedge i_Rst_L)
|
||||
begin
|
||||
if (~i_Rst_L)
|
||||
begin
|
||||
o_SPI_Clk <= w_CPOL;
|
||||
end
|
||||
else
|
||||
begin
|
||||
o_SPI_Clk <= r_SPI_Clk;
|
||||
end // else: !if(~i_Rst_L)
|
||||
end // always @ (posedge i_Clk or negedge i_Rst_L)
|
||||
|
||||
|
||||
endmodule // SPI_Master
|
||||
@@ -0,0 +1,40 @@
|
||||
//------------------------------------------------------
|
||||
//
|
||||
// File : assert_file.sv
|
||||
// Related Files :
|
||||
// Author(s) : Mueller
|
||||
// Email : muelleral82290@th-nuernberg.de
|
||||
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
|
||||
// Notes : Stimuli Modul
|
||||
//
|
||||
//------------------------------------------------------
|
||||
// History
|
||||
//------------------------------------------------------
|
||||
// Version| Author | Mod. Date | Changes Made:
|
||||
// v1.00 | Mueller | 27/04/2023 | first code
|
||||
//------------------------------------------------------
|
||||
|
||||
|
||||
//properties-> HIER NOCH NICHTS GEMACHT!
|
||||
|
||||
/* example
|
||||
property p_ones;
|
||||
bus_m.op == 4'h1 |-> bus_m.z == 4'hf;
|
||||
endproperty
|
||||
|
||||
property p_and;
|
||||
bus_m.op == 4'h4 |-> bus_m.z == (bus_m.a & bus_m.b);
|
||||
endproperty
|
||||
|
||||
//assertions
|
||||
|
||||
a_ones : assert property(@(posedge clk) p_ones)
|
||||
$display("%t, property asserted: a_ones", $time());
|
||||
else
|
||||
$display("%t, property failed: a_ones", $time());
|
||||
|
||||
a_and : assert property(@(posedge clk) p_and)
|
||||
$display("%t, property asserted: a_and", $time());
|
||||
else
|
||||
$display("%t, property failed: a_and", $time());
|
||||
*/
|
||||
@@ -0,0 +1,86 @@
|
||||
|
||||
|
||||
|
||||
module spi(bus.spi_port b, fram_if.fram_port_top i);
|
||||
|
||||
parameter ringbuffer_size = 256;
|
||||
|
||||
logic [19:0] FRAM_Adr;
|
||||
logic [7:0] FRAM_DATA_OUT;
|
||||
logic [7:0] FRAM_DATA_IN;
|
||||
logic FRAM_RW;
|
||||
logic FRAM_RSTATUS;
|
||||
logic FRAM_hbn;
|
||||
logic FRAM_go;
|
||||
logic FRAM_busy;
|
||||
|
||||
logic [7:0] clk_cntr;
|
||||
|
||||
initial begin
|
||||
FRAM_Adr <= 20'h0;
|
||||
FRAM_DATA_IN <= 8'h0;
|
||||
FRAM_RW = 0;
|
||||
FRAM_RSTATUS = 0;
|
||||
FRAM_hbn = 0;
|
||||
FRAM_go = 0;
|
||||
clk_cntr = 0;
|
||||
end
|
||||
|
||||
always @ (posedge b.timer) begin
|
||||
if(b.dip[0] == 0) begin //Reset
|
||||
FRAM_Adr <= 20'h0;
|
||||
FRAM_DATA_IN <= 8'h0;
|
||||
FRAM_RW = 0;
|
||||
FRAM_RSTATUS = 0;
|
||||
FRAM_hbn = 0;
|
||||
FRAM_go = 0;
|
||||
clk_cntr = 0;
|
||||
end
|
||||
else if(b.dip[1] == 1) begin //Read
|
||||
FRAM_Adr <= (FRAM_Adr - 1) % (ringbuffer_size - 1);
|
||||
FRAM_RW <= 1'h1; //Read
|
||||
FRAM_go <= 1'h1; //Go
|
||||
end
|
||||
else if(b.dip[1] == 0) begin //Write
|
||||
FRAM_Adr <= (FRAM_Adr + 1) % (ringbuffer_size - 1);
|
||||
FRAM_DATA_IN <= {6'h0, b.dip[3:2]};
|
||||
FRAM_RW <= 1'h0; //Write Operation
|
||||
FRAM_go <= 1'h1; //Go
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge b.clk) begin
|
||||
if(FRAM_go == 1)
|
||||
clk_cntr <= clk_cntr + 1;
|
||||
|
||||
if(clk_cntr > 50 && FRAM_RW == 1'h1) begin
|
||||
b.spi_read <= FRAM_DATA_OUT[1:0];
|
||||
FRAM_go <= 1'h0;
|
||||
FRAM_RW <= 1'h0;
|
||||
clk_cntr <= 0;
|
||||
end
|
||||
else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin
|
||||
FRAM_go <= 1'h0;
|
||||
clk_cntr <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
FRAM FRAM_ut(
|
||||
.i_clk(b.clk),
|
||||
.i_nreset(b.dip[0]),
|
||||
.i_adr(FRAM_Adr),
|
||||
.i_data(FRAM_DATA_IN),
|
||||
.o_data(FRAM_DATA_OUT),
|
||||
.i_rw(FRAM_RW),
|
||||
.i_status(FRAM_RSTATUS),
|
||||
.i_hbn(FRAM_hbn),
|
||||
.i_cready(FRAM_go),
|
||||
.o_busy(FRAM_busy),
|
||||
.o_SPI_Clk(i.sclk),
|
||||
.i_SPI_MISO(i.mosi),
|
||||
.o_SPI_MOSI(i.mosi),
|
||||
.o_SPI_CS_n(i.ss)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,86 @@
|
||||
|
||||
|
||||
|
||||
module spi(bus.spi_port b, fram_if.fram_port_top i);
|
||||
|
||||
parameter ringbuffer_size = 256;
|
||||
|
||||
logic [19:0] FRAM_Adr;
|
||||
logic [7:0] FRAM_DATA_OUT;
|
||||
logic [7:0] FRAM_DATA_IN;
|
||||
logic FRAM_RW;
|
||||
logic FRAM_RSTATUS;
|
||||
logic FRAM_hbn;
|
||||
logic FRAM_go;
|
||||
logic FRAM_busy;
|
||||
|
||||
logic [7:0] clk_cntr;
|
||||
|
||||
initial begin
|
||||
FRAM_Adr <= 20'h0;
|
||||
FRAM_DATA_IN <= 8'h0;
|
||||
FRAM_RW = 0;
|
||||
FRAM_RSTATUS = 0;
|
||||
FRAM_hbn = 0;
|
||||
FRAM_go = 0;
|
||||
clk_cntr = 0;
|
||||
end
|
||||
|
||||
always @ (posedge b.timer) begin
|
||||
if(b.dip[0] == 0) begin //Reset
|
||||
FRAM_Adr <= 20'h0;
|
||||
FRAM_DATA_IN <= 8'h0;
|
||||
FRAM_RW = 0;
|
||||
FRAM_RSTATUS = 0;
|
||||
FRAM_hbn = 0;
|
||||
FRAM_go = 0;
|
||||
clk_cntr = 0;
|
||||
end
|
||||
else if(b.dip[1] == 1) begin //Read
|
||||
FRAM_Adr <= (FRAM_Adr - 1) % (ringbuffer_size - 1);
|
||||
FRAM_RW <= 1'h1; //Read
|
||||
FRAM_go <= 1'h1; //Go
|
||||
end
|
||||
else if(b.dip[1] == 0) begin //Write
|
||||
FRAM_Adr <= (FRAM_Adr + 1) % (ringbuffer_size - 1);
|
||||
FRAM_DATA_IN <= {6'h0, b.dip[3:2]};
|
||||
FRAM_RW <= 1'h0; //Write Operation
|
||||
FRAM_go <= 1'h1; //Go
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge b.clk) begin
|
||||
if(FRAM_go == 1)
|
||||
clk_cntr <= clk_cntr + 1;
|
||||
|
||||
if(clk_cntr > 50 && FRAM_RW == 1'h1) begin
|
||||
b.spi_read <= FRAM_DATA_OUT[1:0];
|
||||
FRAM_go <= 1'h0;
|
||||
FRAM_RW <= 1'h0;
|
||||
clk_cntr <= 0;
|
||||
end
|
||||
else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin
|
||||
FRAM_go <= 1'h0;
|
||||
clk_cntr <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
FRAM FRAM_ut(
|
||||
.i_clk(b.clk),
|
||||
.i_nreset(b.dip[0]),
|
||||
.i_adr(FRAM_Adr),
|
||||
.i_data(FRAM_DATA_IN),
|
||||
.o_data(FRAM_DATA_OUT),
|
||||
.i_rw(FRAM_RW),
|
||||
.i_status(FRAM_RSTATUS),
|
||||
.i_hbn(FRAM_hbn),
|
||||
.i_cready(FRAM_go),
|
||||
.o_busy(FRAM_busy),
|
||||
.o_SPI_Clk(i.sclk),
|
||||
.i_SPI_MISO(i.mosi),
|
||||
.o_SPI_MOSI(i.mosi),
|
||||
.o_SPI_CS_n(i.ss)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,69 @@
|
||||
//------------------------------------------------------
|
||||
//
|
||||
// File : interface.sv
|
||||
// Related Files :
|
||||
// Author(s) : Mueller
|
||||
// Email : muelleral82290@th-nuernberg.de
|
||||
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
|
||||
// Notes : Stimuli Modul
|
||||
//
|
||||
//------------------------------------------------------
|
||||
// History
|
||||
//------------------------------------------------------
|
||||
// Version| Author | Mod. Date | Changes Made:
|
||||
// v1.00 | Mueller | 11/05/2023 | first code
|
||||
//------------------------------------------------------
|
||||
//eoh
|
||||
|
||||
|
||||
//interface for LED
|
||||
//reg [2:0]rbg stores rgb values that depend on dip[3:2]
|
||||
interface led_if();
|
||||
|
||||
logic [2:0]rgb;
|
||||
|
||||
modport led_port_stim(input rgb);
|
||||
modport led_port_top(output rgb);
|
||||
|
||||
|
||||
endinterface : led_if
|
||||
|
||||
//interface for DIPSCHALER
|
||||
// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
|
||||
interface dip_if();
|
||||
|
||||
logic [3:0]dip;
|
||||
|
||||
modport dip_port_stim(output dip);
|
||||
modport dip_port_top(input dip);
|
||||
|
||||
endinterface : dip_if
|
||||
|
||||
//interface for FRAM
|
||||
// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
|
||||
// clk -> system clock / timer
|
||||
// miso -> testbench output
|
||||
// mosi -> testbench input
|
||||
interface fram_if();
|
||||
|
||||
logic ss;
|
||||
logic mosi;
|
||||
logic miso;
|
||||
logic sclk;
|
||||
|
||||
modport fram_port_stim(input mosi, sclk, ss, output miso);
|
||||
modport fram_port_top(output mosi, sclk, ss, input miso);
|
||||
|
||||
endinterface : fram_if
|
||||
|
||||
//testbenchclock replaces the oscillator on the board
|
||||
interface clock_if();
|
||||
|
||||
logic clk;
|
||||
|
||||
modport clock_port_stim(output clk);
|
||||
modport clock_port_top(input clk);
|
||||
|
||||
endinterface : clock_if
|
||||
|
||||
|
||||
@@ -0,0 +1,92 @@
|
||||
//------------------------------------------------------
|
||||
//
|
||||
// File : stimuli.sv
|
||||
// Related Files :
|
||||
// Author(s) : Mueller
|
||||
// Email : muelleral82290@th-nuernberg.de
|
||||
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
|
||||
// Notes : Stimuli Modul
|
||||
//
|
||||
//------------------------------------------------------
|
||||
// History
|
||||
//------------------------------------------------------
|
||||
// Version| Author | Mod. Date | Changes Made:
|
||||
// v1.00 | Mueller | 11/05/2023 | first code
|
||||
//------------------------------------------------------
|
||||
|
||||
//interface for LED
|
||||
//reg [2:0]rbg stores rgb values that depend on dip[3:2]
|
||||
|
||||
//interface for DIPSCHALER
|
||||
// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
|
||||
|
||||
//interface for FRAM
|
||||
// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
|
||||
// clk -> system clock / timer
|
||||
// miso -> testbench output
|
||||
// mosi -> testbench input
|
||||
|
||||
//testbenchclock replaces the oscillator on the board
|
||||
|
||||
// 27.04.23 -> #delay/#oszillatordelay is not set jet
|
||||
// 09.06.23 -> removed fram_if.fram_port_stim fram_spi from the stimuli parameters, moved to "fram_module"
|
||||
// 09.06.23 -> oszillatordelay = 1, delay = 5
|
||||
|
||||
`timescale 10ns/10ps
|
||||
|
||||
module stimuli(led_if.led_port_stim led_stim, dip_if.dip_port_stim dip_stim, clock_if.clock_port_stim clk_stim);
|
||||
|
||||
// generate oszillator signal for the timer block (clock_if)
|
||||
reg oszillator;
|
||||
|
||||
initial oszillator = 0;
|
||||
|
||||
always
|
||||
begin
|
||||
#1 oszillator <= ! oszillator;
|
||||
clk_stim.clk <= ! oszillator;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
|
||||
/*~~~~toplevel is set to off~~~~~~~~*/
|
||||
/*~~~~dip[0] is set to 0~~~~~~~~~~~~*/
|
||||
dip_stim.dip = 4'b0000;
|
||||
#500 dip_stim.dip = 4'b0010;
|
||||
#500 dip_stim.dip = 4'b0100;
|
||||
#500 dip_stim.dip = 4'b0110;
|
||||
#500 dip_stim.dip = 4'b1000;
|
||||
#500 dip_stim.dip = 4'b1010;
|
||||
#500 dip_stim.dip = 4'b1100;
|
||||
#500 dip_stim.dip = 4'b1110;
|
||||
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
|
||||
|
||||
/*~~~~toplevel is set to on~~~~~~~~~*/
|
||||
/*~~~~dip[0] is set to 1~~~~~~~~~~~~*/
|
||||
|
||||
/*~~fram is set to write~~~~~~~~*/
|
||||
/*~~~~dip[1] is set to 0~~~~~~~~*/
|
||||
#800 dip_stim.dip = 4'b0001;
|
||||
#2000 dip_stim.dip = 4'b0101;
|
||||
#2000 dip_stim.dip = 4'b1001;
|
||||
#2000 dip_stim.dip = 4'b1101;
|
||||
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
|
||||
|
||||
/*~~fram is set to read~~~~~~~~~*/
|
||||
/*~~~~dip[1] is set to 1~~~~~~~~*/
|
||||
#2000 dip_stim.dip = 4'b0011;
|
||||
#2000 dip_stim.dip = 4'b0111;
|
||||
#2000 dip_stim.dip = 4'b1011;
|
||||
#2000 dip_stim.dip = 4'b1111;
|
||||
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
|
||||
|
||||
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
|
||||
|
||||
end
|
||||
|
||||
endmodule : stimuli
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,46 @@
|
||||
//------------------------------------------------------
|
||||
//
|
||||
// File : Timer.sv
|
||||
// Related Files :
|
||||
// Author(s) :
|
||||
// Email :
|
||||
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
|
||||
// Notes :
|
||||
//
|
||||
//------------------------------------------------------
|
||||
// History
|
||||
//------------------------------------------------------
|
||||
// Version| Author | Mod. Date | Changes Made:
|
||||
// v1.00 | | 11.05.2023 |
|
||||
//------------------------------------------------------
|
||||
//eoh
|
||||
|
||||
|
||||
module timer(bus.timer_port fpga_bus, clock_if.clock_port_top c); // (bus.timer b, clock_if.clock_port_top i)
|
||||
|
||||
integer counter = 0; // internal count reg
|
||||
integer reload_val;
|
||||
|
||||
|
||||
always @ (posedge c.clk or fpga_bus.dip[0]) begin
|
||||
if (!fpga_bus.dip[0]) begin
|
||||
counter <= 0;
|
||||
fpga_bus.timer <= 0;
|
||||
end else begin
|
||||
if(counter <= 800) begin // zu testzwecken kürzer 1000000
|
||||
counter++;
|
||||
fpga_bus.timer <= 0;
|
||||
end else begin
|
||||
counter <= 0;
|
||||
fpga_bus.timer <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
//give the input clock on the bus
|
||||
always@(posedge c.clk or negedge c.clk)
|
||||
fpga_bus.clk = c.clk;
|
||||
|
||||
endmodule : timer
|
||||
|
||||
@@ -0,0 +1,99 @@
|
||||
// Definition of top level
|
||||
module top(led_if.led_port_top l, dip_if.dip_port_top d, fram_if.fram_port_top f, clock_if.clock_port_top c);
|
||||
|
||||
// Initialisation of bus
|
||||
bus fpga_bus();
|
||||
|
||||
// Initialisation of modules
|
||||
timer t(fpga_bus, c);
|
||||
steuerung st(fpga_bus, l);
|
||||
spi s(fpga_bus, f);
|
||||
parallelport p(fpga_bus, d);
|
||||
endmodule : top
|
||||
|
||||
// Definition of bus interface
|
||||
interface bus();
|
||||
// bus wires
|
||||
logic clk; // clock
|
||||
logic timer;
|
||||
logic [3:0]dip;
|
||||
logic [1:0]spi_read;
|
||||
|
||||
// modports from modules pov
|
||||
modport timer_port(input dip, output timer, clk); //dip[0]
|
||||
modport parallel_port(output dip); //dip[3:0]
|
||||
modport steuerung_port(input dip, timer, spi_read, clk); //dip[3:0] / spi_read[1:0]
|
||||
modport spi_port(input dip, clk, timer, output spi_read); //spi_read[1:0]
|
||||
endinterface : bus
|
||||
|
||||
// Definition of parallelport
|
||||
module parallelport(bus.parallel_port b, dip_if.dip_port_top d);
|
||||
|
||||
//always at change of the input dip, put the change on the bus
|
||||
always@(d.dip[0] or d.dip[1] or d.dip[2] or d.dip[3])
|
||||
b.dip = d.dip;
|
||||
|
||||
endmodule
|
||||
|
||||
module steuerung(bus.steuerung_port b, led_if.led_port_top i);
|
||||
/*...
|
||||
b.dip[3:0], b.timer, b.spi_read[1:0]
|
||||
i.rgb[2:0]
|
||||
...*/
|
||||
endmodule
|
||||
|
||||
/*
|
||||
_______________________________________________________________________________________________________________
|
||||
Testbench
|
||||
__________________ ___________________
|
||||
| | | |
|
||||
| DIP-Schalter | | FRAM-Speicher |
|
||||
| | | |
|
||||
|__________________| |___________________|
|
||||
| |
|
||||
____________________________|________________________________________________________________|_________________
|
||||
Toplevel | |
|
||||
| |
|
||||
dip[3:0]-->| |<--mosi, miso, sclk, ss
|
||||
| |
|
||||
________|_________ ________|__________
|
||||
| | | |
|
||||
| Parallelport | | SPI-Schnittstelle |
|
||||
| | | & FRAM-Kontroller |
|
||||
|__________________| |___________________|
|
||||
| |
|
||||
| |
|
||||
dip[3:0]-->| |<--dip[3:0], timer, spi_read[1:0]
|
||||
| |
|
||||
| |
|
||||
---------------------------------------------------------------------BUS
|
||||
| |
|
||||
| |
|
||||
dip[0], clk, timer-->| |<--dip[3:0], timer, spi_read[1:0]
|
||||
| |
|
||||
________|_________ ___________________ ________|__________
|
||||
| | | | | |
|
||||
| Timer | | Oszillator-Takt | | Ampel-Steuerung |
|
||||
| | | (auf Board) | | |
|
||||
|__________________| |___________________| |___________________|
|
||||
| | |
|
||||
| | |
|
||||
clk-->------------------------------ |<--rgb[2:0]
|
||||
| |
|
||||
____________________________|________________________________________________________________|___________________
|
||||
| |
|
||||
________|_________ ________|__________
|
||||
| | | |
|
||||
| Takt | | RGB-LED |
|
||||
| (der Testbench) | | |
|
||||
|__________________| |___________________|
|
||||
|
||||
|
||||
__________________________________________________________________________________________________________________
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,52 @@
|
||||
//------------------------------------------------------
|
||||
//
|
||||
// File : top.sv
|
||||
// Related Files :
|
||||
// Author(s) : Mueller
|
||||
// Email : muelleral82290@th-nuernberg.de
|
||||
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
|
||||
// Notes : Stimuli Modul
|
||||
//
|
||||
//------------------------------------------------------
|
||||
// History
|
||||
//------------------------------------------------------
|
||||
// Version| Author | Mod. Date | Changes Made:
|
||||
// v1.00 | Mueller | 27/04/2023 | first code
|
||||
//------------------------------------------------------
|
||||
//eoh
|
||||
|
||||
//interface for LED
|
||||
//reg [2:0]rbg stores rgb values that depend on dip[3:2]
|
||||
|
||||
//interface for DIPSCHALER
|
||||
// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
|
||||
|
||||
//interface for FRAM
|
||||
// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
|
||||
// clk -> system clock / timer
|
||||
// miso -> testbench output
|
||||
// mosi -> testbench input
|
||||
|
||||
//testbenchclock replaces the oscillator on the board
|
||||
|
||||
`timescale 10us/10ns
|
||||
|
||||
module top_tb();
|
||||
|
||||
// Interface
|
||||
led_if stim_led_if();
|
||||
dip_if stim_dip_if();
|
||||
fram_if stim_fram_if();
|
||||
clock_if stim_clock_if();
|
||||
|
||||
// Instanziierungen
|
||||
top t1(stim_led_if, stim_dip_if, stim_fram_if, stim_clock_if);
|
||||
stimuli s1(stim_led_if, stim_dip_if, stim_clock_if);
|
||||
//fram_module f1(stim_fram_if);
|
||||
|
||||
// assertions
|
||||
//`include "./hdl_src/sv/led_assert.txt"
|
||||
|
||||
endmodule : top_tb
|
||||
|
||||
|
||||
Reference in New Issue
Block a user