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muellerlu 2026-05-29 10:19:13 +02:00
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charapallivenkatsaja@efiapps0:/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock$ tessent -shell
// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024
// Unpublished work. Copyright 2024 Siemens
//
// This material contains trade secrets or otherwise confidential
// information owned by Siemens Industry Software Inc. or its affiliates
// (collectively, "SISW"), or its licensors. Access to and use of this
// information is strictly limited as set forth in the Customer's
// applicable agreements with SISW.
//
// Siemens software executing under x86-64 Linux on Thu May 28 17:29:18 CEST 2026.
// 64 bit version
// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap)
//
SETUP> source scri
scripts scripts_risc_v
SETUP> source scripts_risc_v/5_atpg.do
// sub-command: set_context patterns -scan
// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib
// sub-command: read_design cpu -design_id Scan_0
// sub-command: add_black_boxes -modules " MemGen_16_10 "
// Command 'add_black_boxes' requires an elaborated design. Automatically elaborating the design ...
// Note: 36 duplicate cell library models were read. The last model read of the same name was kept.
// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on'
// before issuing 'read_cell_library'.
// Warning: 1 cell library model contained 2 floating model outputs.
// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on'
// before issuing 'read_cell_library'.
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
// Note: Top design is 'cpu'.
// Warning: 32 cases: Unused net in DFT library model
// Warning: 106 cases: Undriven net in netlist module
// Warning: 1 case: Floating input on instance in netlist
// Warning: 47 cases: Net in netlist not connected
// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings
// Design elaboration successful.
// sub-command: add_black_boxes -modules " MemGen_32_11 "
// sub-command: add_black_boxes -modules " main_mem "
// sub-command: set_current_design cpu
// Warning: Undefined modules were found.
// Before using "set_system_mode" or "create_flat_model", you must either define
// the missing modules using "read_verilog" and/or "read_cell_library", or use the
// following command to treat them as black boxes:
add_black_boxes -modules { \
MemGen_16_10 \
}
// You can also use "add_black_boxes -auto" to black box all undefined modules but
// it is recommended that you do not add this command to your dofile. Doing so may
// unintentionally black-box new undefined modules in future runs.
// Warning: 106 cases: Undriven net in netlist module
// Warning: 1 case: Floating input on instance in netlist
// Warning: 47 cases: Net in netlist not connected
// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings
// Note: Design level set to 'physical_block' from previous settings
// sub-command: set_design_level physical_block
// sub-command: import_scan_mode unwrapped
// Resetting design.
// Warning: The current mode name was not specified and will be set to 'unwrapped'.
// Different ATPG configurations should use different mode names, otherwise
// they will overwrite each other in the TSDB when 'write_tsdb_data -replace' is called.
// If you will have multiple ATPG configurations for this scan mode of this design,
// use the 'set_current_mode' command to change the current mode name.
// sub-command: set_system_mode analysis
// Warning: Rule FN1 violation occurs 152 times
// Flattening process completed, cell instances=4041, gates=16395, PIs=13, POs=12, CPU time=0.08 sec.
// ---------------------------------------------------------------------------
// Begin circuit learning analyses.
// --------------------------------
// Learning completed, CPU time=0.04 sec.
// ---------------------------------------------------------------------------
// Begin scan chain identification process, memory elements = 1059.
// ---------------------------------------------------------------------------
// Begin simulation of load_unload procedure.
// Simulation of load_unload procedure completed, CPU time=0.0 sec.
// Chain = unwrapped_chain1 successfully traced with scan_cells = 256.
// Chain = unwrapped_chain2 successfully traced with scan_cells = 256.
// Chain = unwrapped_chain3 successfully traced with scan_cells = 256.
// Chain = unwrapped_chain4 successfully traced with scan_cells = 256.
// 1024 scan cells have been identified in 4 scan chains.
// Longest scan chain has 256 scan cells.
// ---------------------------------------------------------------------------
// Begin transparent latch checking for 35 latches.
// ---------------------------------------------------------------------------
// Number transparent latches = 35.
// ---------------------------------------------------------------------------
// Begin scan clock rules checking.
// ---------------------------------------------------------------------------
// 1 scan clock/set/reset lines have been identified.
// All scan clocks successfully passed off-state check.
// Capture clock is set to clk_25mhz.
// ---------------------------------------------------------------------------
// 35 non-scan memory elements are identified.
// ---------------------------------------------------------------------------
// 35 non-scan memory elements are identified as TLA. (D5)
// ---------------------------------------------------------------------------
// 64 gates may have an observable X-state. (E5)
// sub-command: report_clocks
User-defined Clock (1):
=========================
Sync and Async Source Clock
============================
----------- --------- --------
Name Off State Internal
----------- --------- --------
'clk_25mhz' 0 No
// sub-command: report_drc_rules
D5: #fails=35 handling=warning (non-scan memory element)
E5: #fails=64 handling=note (X-state propagation)
// sub-command: set_fault_type stuck
// sub-command: add_faults -all
// sub-command: create_patterns
// | ------------------------------------------------------------------------------------------------------------------ |
// | Analyzing the design |
// | |
// | Current clock restriction setting: Domain_clock (edge interaction) |
// | (optimal) |
// | |
// | Current abort limit setting: 30 |
// | Calling: set_abort_limit 300 100 |
// | ------------------------------------------------------------------------------------------------------------------ |
// | |
// | Current sequential depth: 0 (optimal) |
// | |
// | ------------------------------------------------------------------------------------------------------------------ |
// ------------------------------------------------------------------------
// Simulation performed for #gates = 16395 #faults = 4988
// system mode = analysis pattern source = internal patterns
// ------------------------------------------------------------------------
// #patterns test #faults #faults # eff. # test process RE/AU/AAB
// simulated coverage in list detected patterns patterns CPU time
// --- ------ --- --- --- --- 6.31 sec 0/27368/0
// 16 25.95% 0 2239 10 10 6.32 sec
// -----------------------------------------------------------------------
// Performing redundant fault identification for 27368 faults
// -----------------------------------------------------------------------
// deterministic ATPG invoked with abort limit = 300
// # red. # non-red. # abort # remn. progress test process
// faults faults faults faults coverage CPU time
// 20 27338 10 0 100.00% 25.96% 1903.57 sec
Statistics Report
Stuck-at Faults
---------------------------------------
Fault Classes #faults
(total)
----------------------- --------------
FU (full) 39020
--------------------- --------------
DS (det_simulation) 2239 ( 5.74%)
DI (det_implication) 7351 (18.84%)
UU (unused) 2062 ( 5.28%)
RE (redundant) 20 ( 0.05%)
AU (atpg_untestable) 27348 (70.09%)
---------------------------------------
Fault Sub-classes
---------------------
AU (atpg_untestable)
BB (black_boxes) 24599 (63.04%)
Unclassified 2749 ( 7.05%)
---------------------------------------
Coverage
---------------------
test_coverage 25.96%
fault_coverage 24.58%
atpg_effectiveness 100.00%
---------------------------------------
#test_patterns 10
#simulated_patterns 16
CPU_time (secs) 1925.7
---------------------------------------
// sub-command: report_statistics
Statistics Report
Stuck-at Faults
---------------------------------------
Fault Classes #faults
(total)
----------------------- --------------
FU (full) 39020
--------------------- --------------
DS (det_simulation) 2239 ( 5.74%)
DI (det_implication) 7351 (18.84%)
UU (unused) 2062 ( 5.28%)
RE (redundant) 20 ( 0.05%)
AU (atpg_untestable) 27348 (70.09%)
---------------------------------------
Fault Sub-classes
---------------------
AU (atpg_untestable)
BB (black_boxes) 24599 (63.04%)
Unclassified 2749 ( 7.05%)
---------------------------------------
Coverage
---------------------
test_coverage 25.96%
fault_coverage 24.58%
atpg_effectiveness 100.00%
---------------------------------------
#test_patterns 10
#simulated_patterns 16
CPU_time (secs) 1925.7
---------------------------------------
// sub-command: report_faults -summary
Statistics Report
Stuck-at Faults
---------------------------------------
Fault Classes #faults
(total)
----------------------- --------------
FU (full) 39020
--------------------- --------------
DS (det_simulation) 2239 ( 5.74%)
DI (det_implication) 7351 (18.84%)
UU (unused) 2062 ( 5.28%)
RE (redundant) 20 ( 0.05%)
AU (atpg_untestable) 27348 (70.09%)
---------------------------------------
Fault Sub-classes
---------------------
AU (atpg_untestable)
BB (black_boxes) 24599 (63.04%)
Unclassified 2749 ( 7.05%)
---------------------------------------
Coverage
---------------------
test_coverage 25.96%
fault_coverage 24.58%
atpg_effectiveness 100.00%
---------------------------------------
#test_patterns 10
#simulated_patterns 16
CPU_time (secs) 1925.7
---------------------------------------
// sub-command: write_patterns cpu_patterns.stil -stil -replace
// sub-command: write_patterns cpu_patterns_serial.v -verilog -serial -replace
// sub-command: write_tsdb_data -replace
// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.tcd.gz
// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.flat.gz
// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.patdb
// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.faults.gz
// sub-command: exit

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#!/bin/sh
rm -rf output
mkdir output
mkdir output/odb
mkdir output/db
mkdir output/logs
rm -rf `find . -type f -name "oasys.*"`
# Gruppe setzen + volle Rechte + setgid (neue Dateien erben Gruppe)
chgrp -R projekt01 output
chmod -R 2775 output
# Zusätzlich für alle Projekt-Dateien (falls Oasys außerhalb von output/ schreibt)
chgrp -R projekt01 . 2>/dev/null
find . -type d -exec chmod g+rwxs {} \; 2>/dev/null
find . -type f -exec chmod g+rw {} \; 2>/dev/null
echo "\n-------------------------------------"
echo "\nCleanup Complete"
echo "\n-------------------------------------\n"

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$OASYS_HOME/bin/oasys -log output/logs/synth.log
source scripts_counter/1_read_design.tcl
source scripts_counter/2_synthesize_optimize.tcl

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create_clock -name clk -period 10 [get_ports clk]

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create_clock -name lfxt_clk -period 600 -waveform { 0 300 } [get_pins lfxt_clk_pad/C ]
create_clock -name sysclk_byp -period 600 -waveform { 0 300 } [get_pins sysclk_byp_pad/C ]
create_clock -name usbclk_byp -period 600 -waveform { 0 300 } [get_pins usbclk_byp_pad/C ]
create_clock -name vsysclk -period 15 -waveform { 0 7.5 }
create_clock -name vsysclk_ddr -period 7.5 -waveform { 0 3.75 }
create_clock -name sysclk -period 2 -waveform { 0 1 } [get_pins i_MAIN_PLL/PLLOUT]
create_clock -name usbclk -period 8 -waveform { 0 4 } [get_pins i_USB_PLL/PLLOUT]
#create_generated_clock -name sysclk -source i_MAIN_PLL/REF -master_clock lfxt_clk -multiply_by 40 -add [get_pins i_MAIN_PLL/PLLOUT]
#create_generated_clock -name usbclk -source i_USB_PLL/REF -master_clock lfxt_clk -multiply_by 6 -add [get_pins i_USB_PLL/PLLOUT]
set_clock_uncertainty -setup 0.2 [get_clocks sysclk]
set_clock_uncertainty -setup 0.1 [get_clocks usbclk]
set_false_path -from [get_ports nmi]
set_false_path -from [get_ports reset_n]
set_input_delay -clock vsysclk 10.5 [get_ports reset_n]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[15] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[14] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[13] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[12] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[11] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[10] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[9] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[8] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[7] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[6] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[5] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[4] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[3] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[2] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[1] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[0] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[15] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[14] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[13] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[12] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[11] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[10] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[9] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[8] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[7] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[6] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[5] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[4] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[3] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[2] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[1] }]
set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[0] }]
set_input_delay -clock vsysclk 10.5 [get_ports nmi]
set_input_delay -clock vsysclk 10.5 [get_ports scan_mode]
set_input_delay -clock vsysclk 10.5 [get_ports sysclk_byp]
set_input_delay -clock vsysclk 10.5 [get_ports usbclk_byp]
set_output_delay -clock vsysclk 4.5 [get_ports mclk]
set_output_delay -clock vsysclk 4.5 [get_ports BS_ren_0]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[16] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[15] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[14] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[13] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[12] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[11] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[10] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[9] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[8] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[7] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[6] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[5] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[4] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports BS_ren_1]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[16] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[15] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[14] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[13] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[12] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[11] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[10] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[9] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[8] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[7] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[6] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[5] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[4] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports ddr0_cke]
set_output_delay -clock vsysclk 4.5 [get_ports ddr0_cs_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr0_we_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr0_cas_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr0_ras_n]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[12] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[11] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[10] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[9] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[8] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[7] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[6] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[5] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[4] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_ba[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_ba[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports ddr1_cke]
set_output_delay -clock vsysclk 4.5 [get_ports ddr1_cs_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr1_we_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr1_cas_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr1_ras_n]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[12] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[11] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[10] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[9] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[8] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[7] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[6] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[5] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[4] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_ba[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_ba[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports ddr2_cke]
set_output_delay -clock vsysclk 4.5 [get_ports ddr2_cs_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr2_we_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr2_cas_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr2_ras_n]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[12] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[11] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[10] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[9] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[8] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[7] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[6] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[5] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[4] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_ba[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_ba[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports ddr3_cke]
set_output_delay -clock vsysclk 4.5 [get_ports ddr3_cs_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr3_we_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr3_cas_n]
set_output_delay -clock vsysclk 4.5 [get_ports ddr3_ras_n]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[12] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[11] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[10] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[9] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[8] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[7] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[6] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[5] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[4] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_ba[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_ba[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[31] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[30] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[29] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[28] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[27] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[26] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[25] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[24] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[23] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[22] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[21] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[20] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[19] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[18] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[17] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[16] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[15] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[14] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[13] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[12] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[11] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[10] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[9] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[8] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[7] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[6] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[5] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[4] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[31] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[30] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[29] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[28] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[27] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[26] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[25] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[24] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[23] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[22] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[21] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[20] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[19] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[18] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[17] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[16] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[15] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[14] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[13] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[12] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[11] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[10] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[9] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[8] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[7] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[6] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[5] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[4] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[31] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[30] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[29] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[28] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[27] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[26] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[25] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[24] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[23] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[22] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[21] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[20] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[19] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[18] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[17] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[16] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[15] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[14] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[13] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[12] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[11] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[10] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[9] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[8] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[7] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[6] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[5] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[4] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[0] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[31] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[30] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[29] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[28] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[27] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[26] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[25] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[24] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[23] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[22] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[21] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[20] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[19] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[18] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[17] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[16] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[15] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[14] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[13] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[12] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[11] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[10] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[9] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[8] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[7] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[6] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[5] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[4] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[3] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[2] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[1] }]
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[0] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[31] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[30] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[29] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[28] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[27] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[26] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[25] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[24] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[23] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[22] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[21] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[20] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[19] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[18] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[17] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[16] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[15] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[14] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[13] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[12] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[11] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[10] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[9] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[8] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[7] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[6] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[5] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[4] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[3] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[2] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[1] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[0] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[31] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[30] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[29] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[28] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[27] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[26] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[25] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[24] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[23] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[22] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[21] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[20] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[19] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[18] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[17] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[16] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[15] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[14] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[13] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[12] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[11] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[10] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[9] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[8] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[7] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[6] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[5] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[4] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[3] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[2] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[1] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[0] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[31] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[30] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[29] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[28] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[27] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[26] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[25] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[24] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[23] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[22] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[21] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[20] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[19] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[18] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[17] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[16] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[15] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[14] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[13] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[12] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[11] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[10] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[9] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[8] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[7] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[6] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[5] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[4] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[3] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[2] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[1] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[0] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[31] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[30] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[29] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[28] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[27] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[26] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[25] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[24] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[23] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[22] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[21] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[20] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[19] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[18] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[17] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[16] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[15] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[14] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[13] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[12] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[11] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[10] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[9] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[8] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[7] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[6] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[5] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[4] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[3] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[2] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[1] }]
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[0] }]
set_load 10 [get_ports mclk]
set_load 10 [get_ports BS_ren_0]
set_load 10 [get_ports { BS_addr_0[16] }]
set_load 10 [get_ports { BS_addr_0[15] }]
set_load 10 [get_ports { BS_addr_0[14] }]
set_load 10 [get_ports { BS_addr_0[13] }]
set_load 10 [get_ports { BS_addr_0[12] }]
set_load 10 [get_ports { BS_addr_0[11] }]
set_load 10 [get_ports { BS_addr_0[10] }]
set_load 10 [get_ports { BS_addr_0[9] }]
set_load 10 [get_ports { BS_addr_0[8] }]
set_load 10 [get_ports { BS_addr_0[7] }]
set_load 10 [get_ports { BS_addr_0[6] }]
set_load 10 [get_ports { BS_addr_0[5] }]
set_load 10 [get_ports { BS_addr_0[4] }]
set_load 10 [get_ports { BS_addr_0[3] }]
set_load 10 [get_ports { BS_addr_0[2] }]
set_load 10 [get_ports { BS_addr_0[1] }]
set_load 10 [get_ports { BS_addr_0[0] }]
set_load 10 [get_ports BS_ren_1]
set_load 10 [get_ports { BS_addr_1[16] }]
set_load 10 [get_ports { BS_addr_1[15] }]
set_load 10 [get_ports { BS_addr_1[14] }]
set_load 10 [get_ports { BS_addr_1[13] }]
set_load 10 [get_ports { BS_addr_1[12] }]
set_load 10 [get_ports { BS_addr_1[11] }]
set_load 10 [get_ports { BS_addr_1[10] }]
set_load 10 [get_ports { BS_addr_1[9] }]
set_load 10 [get_ports { BS_addr_1[8] }]
set_load 10 [get_ports { BS_addr_1[7] }]
set_load 10 [get_ports { BS_addr_1[6] }]
set_load 10 [get_ports { BS_addr_1[5] }]
set_load 10 [get_ports { BS_addr_1[4] }]
set_load 10 [get_ports { BS_addr_1[3] }]
set_load 10 [get_ports { BS_addr_1[2] }]
set_load 10 [get_ports { BS_addr_1[1] }]
set_load 10 [get_ports { BS_addr_1[0] }]
set_load 10 [get_ports ddr0_cke]
set_load 10 [get_ports ddr0_cs_n]
set_load 10 [get_ports ddr0_we_n]
set_load 10 [get_ports ddr0_cas_n]
set_load 10 [get_ports ddr0_ras_n]
set_load 10 [get_ports { ddr0_adr[12] }]
set_load 10 [get_ports { ddr0_adr[11] }]
set_load 10 [get_ports { ddr0_adr[10] }]
set_load 10 [get_ports { ddr0_adr[9] }]
set_load 10 [get_ports { ddr0_adr[8] }]
set_load 10 [get_ports { ddr0_adr[7] }]
set_load 10 [get_ports { ddr0_adr[6] }]
set_load 10 [get_ports { ddr0_adr[5] }]
set_load 10 [get_ports { ddr0_adr[4] }]
set_load 10 [get_ports { ddr0_adr[3] }]
set_load 10 [get_ports { ddr0_adr[2] }]
set_load 10 [get_ports { ddr0_adr[1] }]
set_load 10 [get_ports { ddr0_adr[0] }]
set_load 10 [get_ports { ddr0_ba[1] }]
set_load 10 [get_ports { ddr0_ba[0] }]
set_load 10 [get_ports { ddr0_dm[3] }]
set_load 10 [get_ports { ddr0_dm[2] }]
set_load 10 [get_ports { ddr0_dm[1] }]
set_load 10 [get_ports { ddr0_dm[0] }]
set_load 10 [get_ports ddr1_cke]
set_load 10 [get_ports ddr1_cs_n]
set_load 10 [get_ports ddr1_we_n]
set_load 10 [get_ports ddr1_cas_n]
set_load 10 [get_ports ddr1_ras_n]
set_load 10 [get_ports { ddr1_adr[12] }]
set_load 10 [get_ports { ddr1_adr[11] }]
set_load 10 [get_ports { ddr1_adr[10] }]
set_load 10 [get_ports { ddr1_adr[9] }]
set_load 10 [get_ports { ddr1_adr[8] }]
set_load 10 [get_ports { ddr1_adr[7] }]
set_load 10 [get_ports { ddr1_adr[6] }]
set_load 10 [get_ports { ddr1_adr[5] }]
set_load 10 [get_ports { ddr1_adr[4] }]
set_load 10 [get_ports { ddr1_adr[3] }]
set_load 10 [get_ports { ddr1_adr[2] }]
set_load 10 [get_ports { ddr1_adr[1] }]
set_load 10 [get_ports { ddr1_adr[0] }]
set_load 10 [get_ports { ddr1_ba[1] }]
set_load 10 [get_ports { ddr1_ba[0] }]
set_load 10 [get_ports { ddr1_dm[3] }]
set_load 10 [get_ports { ddr1_dm[2] }]
set_load 10 [get_ports { ddr1_dm[1] }]
set_load 10 [get_ports { ddr1_dm[0] }]
set_load 10 [get_ports ddr2_cke]
set_load 10 [get_ports ddr2_cs_n]
set_load 10 [get_ports ddr2_we_n]
set_load 10 [get_ports ddr2_cas_n]
set_load 10 [get_ports ddr2_ras_n]
set_load 10 [get_ports { ddr2_adr[12] }]
set_load 10 [get_ports { ddr2_adr[11] }]
set_load 10 [get_ports { ddr2_adr[10] }]
set_load 10 [get_ports { ddr2_adr[9] }]
set_load 10 [get_ports { ddr2_adr[8] }]
set_load 10 [get_ports { ddr2_adr[7] }]
set_load 10 [get_ports { ddr2_adr[6] }]
set_load 10 [get_ports { ddr2_adr[5] }]
set_load 10 [get_ports { ddr2_adr[4] }]
set_load 10 [get_ports { ddr2_adr[3] }]
set_load 10 [get_ports { ddr2_adr[2] }]
set_load 10 [get_ports { ddr2_adr[1] }]
set_load 10 [get_ports { ddr2_adr[0] }]
set_load 10 [get_ports { ddr2_ba[1] }]
set_load 10 [get_ports { ddr2_ba[0] }]
set_load 10 [get_ports { ddr2_dm[3] }]
set_load 10 [get_ports { ddr2_dm[2] }]
set_load 10 [get_ports { ddr2_dm[1] }]
set_load 10 [get_ports { ddr2_dm[0] }]
set_load 10 [get_ports ddr3_cke]
set_load 10 [get_ports ddr3_cs_n]
set_load 10 [get_ports ddr3_we_n]
set_load 10 [get_ports ddr3_cas_n]
set_load 10 [get_ports ddr3_ras_n]
set_load 10 [get_ports { ddr3_adr[12] }]
set_load 10 [get_ports { ddr3_adr[11] }]
set_load 10 [get_ports { ddr3_adr[10] }]
set_load 10 [get_ports { ddr3_adr[9] }]
set_load 10 [get_ports { ddr3_adr[8] }]
set_load 10 [get_ports { ddr3_adr[7] }]
set_load 10 [get_ports { ddr3_adr[6] }]
set_load 10 [get_ports { ddr3_adr[5] }]
set_load 10 [get_ports { ddr3_adr[4] }]
set_load 10 [get_ports { ddr3_adr[3] }]
set_load 10 [get_ports { ddr3_adr[2] }]
set_load 10 [get_ports { ddr3_adr[1] }]
set_load 10 [get_ports { ddr3_adr[0] }]
set_load 10 [get_ports { ddr3_ba[1] }]
set_load 10 [get_ports { ddr3_ba[0] }]
set_load 10 [get_ports { ddr3_dm[3] }]
set_load 10 [get_ports { ddr3_dm[2] }]
set_load 10 [get_ports { ddr3_dm[1] }]
set_load 10 [get_ports { ddr3_dm[0] }]
set_load 10 [get_ports { ddr0_dq[31] }]
set_load 10 [get_ports { ddr0_dq[30] }]
set_load 10 [get_ports { ddr0_dq[29] }]
set_load 10 [get_ports { ddr0_dq[28] }]
set_load 10 [get_ports { ddr0_dq[27] }]
set_load 10 [get_ports { ddr0_dq[26] }]
set_load 10 [get_ports { ddr0_dq[25] }]
set_load 10 [get_ports { ddr0_dq[24] }]
set_load 10 [get_ports { ddr0_dq[23] }]
set_load 10 [get_ports { ddr0_dq[22] }]
set_load 10 [get_ports { ddr0_dq[21] }]
set_load 10 [get_ports { ddr0_dq[20] }]
set_load 10 [get_ports { ddr0_dq[19] }]
set_load 10 [get_ports { ddr0_dq[18] }]
set_load 10 [get_ports { ddr0_dq[17] }]
set_load 10 [get_ports { ddr0_dq[16] }]
set_load 10 [get_ports { ddr0_dq[15] }]
set_load 10 [get_ports { ddr0_dq[14] }]
set_load 10 [get_ports { ddr0_dq[13] }]
set_load 10 [get_ports { ddr0_dq[12] }]
set_load 10 [get_ports { ddr0_dq[11] }]
set_load 10 [get_ports { ddr0_dq[10] }]
set_load 10 [get_ports { ddr0_dq[9] }]
set_load 10 [get_ports { ddr0_dq[8] }]
set_load 10 [get_ports { ddr0_dq[7] }]
set_load 10 [get_ports { ddr0_dq[6] }]
set_load 10 [get_ports { ddr0_dq[5] }]
set_load 10 [get_ports { ddr0_dq[4] }]
set_load 10 [get_ports { ddr0_dq[3] }]
set_load 10 [get_ports { ddr0_dq[2] }]
set_load 10 [get_ports { ddr0_dq[1] }]
set_load 10 [get_ports { ddr0_dq[0] }]
set_load 10 [get_ports { ddr1_dq[31] }]
set_load 10 [get_ports { ddr1_dq[30] }]
set_load 10 [get_ports { ddr1_dq[29] }]
set_load 10 [get_ports { ddr1_dq[28] }]
set_load 10 [get_ports { ddr1_dq[27] }]
set_load 10 [get_ports { ddr1_dq[26] }]
set_load 10 [get_ports { ddr1_dq[25] }]
set_load 10 [get_ports { ddr1_dq[24] }]
set_load 10 [get_ports { ddr1_dq[23] }]
set_load 10 [get_ports { ddr1_dq[22] }]
set_load 10 [get_ports { ddr1_dq[21] }]
set_load 10 [get_ports { ddr1_dq[20] }]
set_load 10 [get_ports { ddr1_dq[19] }]
set_load 10 [get_ports { ddr1_dq[18] }]
set_load 10 [get_ports { ddr1_dq[17] }]
set_load 10 [get_ports { ddr1_dq[16] }]
set_load 10 [get_ports { ddr1_dq[15] }]
set_load 10 [get_ports { ddr1_dq[14] }]
set_load 10 [get_ports { ddr1_dq[13] }]
set_load 10 [get_ports { ddr1_dq[12] }]
set_load 10 [get_ports { ddr1_dq[11] }]
set_load 10 [get_ports { ddr1_dq[10] }]
set_load 10 [get_ports { ddr1_dq[9] }]
set_load 10 [get_ports { ddr1_dq[8] }]
set_load 10 [get_ports { ddr1_dq[7] }]
set_load 10 [get_ports { ddr1_dq[6] }]
set_load 10 [get_ports { ddr1_dq[5] }]
set_load 10 [get_ports { ddr1_dq[4] }]
set_load 10 [get_ports { ddr1_dq[3] }]
set_load 10 [get_ports { ddr1_dq[2] }]
set_load 10 [get_ports { ddr1_dq[1] }]
set_load 10 [get_ports { ddr1_dq[0] }]
set_load 10 [get_ports { ddr2_dq[31] }]
set_load 10 [get_ports { ddr2_dq[30] }]
set_load 10 [get_ports { ddr2_dq[29] }]
set_load 10 [get_ports { ddr2_dq[28] }]
set_load 10 [get_ports { ddr2_dq[27] }]
set_load 10 [get_ports { ddr2_dq[26] }]
set_load 10 [get_ports { ddr2_dq[25] }]
set_load 10 [get_ports { ddr2_dq[24] }]
set_load 10 [get_ports { ddr2_dq[23] }]
set_load 10 [get_ports { ddr2_dq[22] }]
set_load 10 [get_ports { ddr2_dq[21] }]
set_load 10 [get_ports { ddr2_dq[20] }]
set_load 10 [get_ports { ddr2_dq[19] }]
set_load 10 [get_ports { ddr2_dq[18] }]
set_load 10 [get_ports { ddr2_dq[17] }]
set_load 10 [get_ports { ddr2_dq[16] }]
set_load 10 [get_ports { ddr2_dq[15] }]
set_load 10 [get_ports { ddr2_dq[14] }]
set_load 10 [get_ports { ddr2_dq[13] }]
set_load 10 [get_ports { ddr2_dq[12] }]
set_load 10 [get_ports { ddr2_dq[11] }]
set_load 10 [get_ports { ddr2_dq[10] }]
set_load 10 [get_ports { ddr2_dq[9] }]
set_load 10 [get_ports { ddr2_dq[8] }]
set_load 10 [get_ports { ddr2_dq[7] }]
set_load 10 [get_ports { ddr2_dq[6] }]
set_load 10 [get_ports { ddr2_dq[5] }]
set_load 10 [get_ports { ddr2_dq[4] }]
set_load 10 [get_ports { ddr2_dq[3] }]
set_load 10 [get_ports { ddr2_dq[2] }]
set_load 10 [get_ports { ddr2_dq[1] }]
set_load 10 [get_ports { ddr2_dq[0] }]
set_load 10 [get_ports { ddr3_dq[31] }]
set_load 10 [get_ports { ddr3_dq[30] }]
set_load 10 [get_ports { ddr3_dq[29] }]
set_load 10 [get_ports { ddr3_dq[28] }]
set_load 10 [get_ports { ddr3_dq[27] }]
set_load 10 [get_ports { ddr3_dq[26] }]
set_load 10 [get_ports { ddr3_dq[25] }]
set_load 10 [get_ports { ddr3_dq[24] }]
set_load 10 [get_ports { ddr3_dq[23] }]
set_load 10 [get_ports { ddr3_dq[22] }]
set_load 10 [get_ports { ddr3_dq[21] }]
set_load 10 [get_ports { ddr3_dq[20] }]
set_load 10 [get_ports { ddr3_dq[19] }]
set_load 10 [get_ports { ddr3_dq[18] }]
set_load 10 [get_ports { ddr3_dq[17] }]
set_load 10 [get_ports { ddr3_dq[16] }]
set_load 10 [get_ports { ddr3_dq[15] }]
set_load 10 [get_ports { ddr3_dq[14] }]
set_load 10 [get_ports { ddr3_dq[13] }]
set_load 10 [get_ports { ddr3_dq[12] }]
set_load 10 [get_ports { ddr3_dq[11] }]
set_load 10 [get_ports { ddr3_dq[10] }]
set_load 10 [get_ports { ddr3_dq[9] }]
set_load 10 [get_ports { ddr3_dq[8] }]
set_load 10 [get_ports { ddr3_dq[7] }]
set_load 10 [get_ports { ddr3_dq[6] }]
set_load 10 [get_ports { ddr3_dq[5] }]
set_load 10 [get_ports { ddr3_dq[4] }]
set_load 10 [get_ports { ddr3_dq[3] }]
set_load 10 [get_ports { ddr3_dq[2] }]
set_load 10 [get_ports { ddr3_dq[1] }]
set_load 10 [get_ports { ddr3_dq[0] }]
set_load 10 [get_ports usb_plus]
set_load 10 [get_ports usb_minus]
set_input_transition 0.1 [get_ports { ddr0_dq[31] }]
set_input_transition 0.1 [get_ports { ddr0_dq[30] }]
set_input_transition 0.1 [get_ports { ddr0_dq[29] }]
set_input_transition 0.1 [get_ports { ddr0_dq[28] }]
set_input_transition 0.1 [get_ports { ddr0_dq[27] }]
set_input_transition 0.1 [get_ports { ddr0_dq[26] }]
set_input_transition 0.1 [get_ports { ddr0_dq[25] }]
set_input_transition 0.1 [get_ports { ddr0_dq[24] }]
set_input_transition 0.1 [get_ports { ddr0_dq[23] }]
set_input_transition 0.1 [get_ports { ddr0_dq[22] }]
set_input_transition 0.1 [get_ports { ddr0_dq[21] }]
set_input_transition 0.1 [get_ports { ddr0_dq[20] }]
set_input_transition 0.1 [get_ports { ddr0_dq[19] }]
set_input_transition 0.1 [get_ports { ddr0_dq[18] }]
set_input_transition 0.1 [get_ports { ddr0_dq[17] }]
set_input_transition 0.1 [get_ports { ddr0_dq[16] }]
set_input_transition 0.1 [get_ports { ddr0_dq[15] }]
set_input_transition 0.1 [get_ports { ddr0_dq[14] }]
set_input_transition 0.1 [get_ports { ddr0_dq[13] }]
set_input_transition 0.1 [get_ports { ddr0_dq[12] }]
set_input_transition 0.1 [get_ports { ddr0_dq[11] }]
set_input_transition 0.1 [get_ports { ddr0_dq[10] }]
set_input_transition 0.1 [get_ports { ddr0_dq[9] }]
set_input_transition 0.1 [get_ports { ddr0_dq[8] }]
set_input_transition 0.1 [get_ports { ddr0_dq[7] }]
set_input_transition 0.1 [get_ports { ddr0_dq[6] }]
set_input_transition 0.1 [get_ports { ddr0_dq[5] }]
set_input_transition 0.1 [get_ports { ddr0_dq[4] }]
set_input_transition 0.1 [get_ports { ddr0_dq[3] }]
set_input_transition 0.1 [get_ports { ddr0_dq[2] }]
set_input_transition 0.1 [get_ports { ddr0_dq[1] }]
set_input_transition 0.1 [get_ports { ddr0_dq[0] }]
set_input_transition 0.1 [get_ports { ddr1_dq[31] }]
set_input_transition 0.1 [get_ports { ddr1_dq[30] }]
set_input_transition 0.1 [get_ports { ddr1_dq[29] }]
set_input_transition 0.1 [get_ports { ddr1_dq[28] }]
set_input_transition 0.1 [get_ports { ddr1_dq[27] }]
set_input_transition 0.1 [get_ports { ddr1_dq[26] }]
set_input_transition 0.1 [get_ports { ddr1_dq[25] }]
set_input_transition 0.1 [get_ports { ddr1_dq[24] }]
set_input_transition 0.1 [get_ports { ddr1_dq[23] }]
set_input_transition 0.1 [get_ports { ddr1_dq[22] }]
set_input_transition 0.1 [get_ports { ddr1_dq[21] }]
set_input_transition 0.1 [get_ports { ddr1_dq[20] }]
set_input_transition 0.1 [get_ports { ddr1_dq[19] }]
set_input_transition 0.1 [get_ports { ddr1_dq[18] }]
set_input_transition 0.1 [get_ports { ddr1_dq[17] }]
set_input_transition 0.1 [get_ports { ddr1_dq[16] }]
set_input_transition 0.1 [get_ports { ddr1_dq[15] }]
set_input_transition 0.1 [get_ports { ddr1_dq[14] }]
set_input_transition 0.1 [get_ports { ddr1_dq[13] }]
set_input_transition 0.1 [get_ports { ddr1_dq[12] }]
set_input_transition 0.1 [get_ports { ddr1_dq[11] }]
set_input_transition 0.1 [get_ports { ddr1_dq[10] }]
set_input_transition 0.1 [get_ports { ddr1_dq[9] }]
set_input_transition 0.1 [get_ports { ddr1_dq[8] }]
set_input_transition 0.1 [get_ports { ddr1_dq[7] }]
set_input_transition 0.1 [get_ports { ddr1_dq[6] }]
set_input_transition 0.1 [get_ports { ddr1_dq[5] }]
set_input_transition 0.1 [get_ports { ddr1_dq[4] }]
set_input_transition 0.1 [get_ports { ddr1_dq[3] }]
set_input_transition 0.1 [get_ports { ddr1_dq[2] }]
set_input_transition 0.1 [get_ports { ddr1_dq[1] }]
set_input_transition 0.1 [get_ports { ddr1_dq[0] }]
set_input_transition 0.1 [get_ports { ddr2_dq[31] }]
set_input_transition 0.1 [get_ports { ddr2_dq[30] }]
set_input_transition 0.1 [get_ports { ddr2_dq[29] }]
set_input_transition 0.1 [get_ports { ddr2_dq[28] }]
set_input_transition 0.1 [get_ports { ddr2_dq[27] }]
set_input_transition 0.1 [get_ports { ddr2_dq[26] }]
set_input_transition 0.1 [get_ports { ddr2_dq[25] }]
set_input_transition 0.1 [get_ports { ddr2_dq[24] }]
set_input_transition 0.1 [get_ports { ddr2_dq[23] }]
set_input_transition 0.1 [get_ports { ddr2_dq[22] }]
set_input_transition 0.1 [get_ports { ddr2_dq[21] }]
set_input_transition 0.1 [get_ports { ddr2_dq[20] }]
set_input_transition 0.1 [get_ports { ddr2_dq[19] }]
set_input_transition 0.1 [get_ports { ddr2_dq[18] }]
set_input_transition 0.1 [get_ports { ddr2_dq[17] }]
set_input_transition 0.1 [get_ports { ddr2_dq[16] }]
set_input_transition 0.1 [get_ports { ddr2_dq[15] }]
set_input_transition 0.1 [get_ports { ddr2_dq[14] }]
set_input_transition 0.1 [get_ports { ddr2_dq[13] }]
set_input_transition 0.1 [get_ports { ddr2_dq[12] }]
set_input_transition 0.1 [get_ports { ddr2_dq[11] }]
set_input_transition 0.1 [get_ports { ddr2_dq[10] }]
set_input_transition 0.1 [get_ports { ddr2_dq[9] }]
set_input_transition 0.1 [get_ports { ddr2_dq[8] }]
set_input_transition 0.1 [get_ports { ddr2_dq[7] }]
set_input_transition 0.1 [get_ports { ddr2_dq[6] }]
set_input_transition 0.1 [get_ports { ddr2_dq[5] }]
set_input_transition 0.1 [get_ports { ddr2_dq[4] }]
set_input_transition 0.1 [get_ports { ddr2_dq[3] }]
set_input_transition 0.1 [get_ports { ddr2_dq[2] }]
set_input_transition 0.1 [get_ports { ddr2_dq[1] }]
set_input_transition 0.1 [get_ports { ddr2_dq[0] }]
set_input_transition 0.1 [get_ports { ddr3_dq[31] }]
set_input_transition 0.1 [get_ports { ddr3_dq[30] }]
set_input_transition 0.1 [get_ports { ddr3_dq[29] }]
set_input_transition 0.1 [get_ports { ddr3_dq[28] }]
set_input_transition 0.1 [get_ports { ddr3_dq[27] }]
set_input_transition 0.1 [get_ports { ddr3_dq[26] }]
set_input_transition 0.1 [get_ports { ddr3_dq[25] }]
set_input_transition 0.1 [get_ports { ddr3_dq[24] }]
set_input_transition 0.1 [get_ports { ddr3_dq[23] }]
set_input_transition 0.1 [get_ports { ddr3_dq[22] }]
set_input_transition 0.1 [get_ports { ddr3_dq[21] }]
set_input_transition 0.1 [get_ports { ddr3_dq[20] }]
set_input_transition 0.1 [get_ports { ddr3_dq[19] }]
set_input_transition 0.1 [get_ports { ddr3_dq[18] }]
set_input_transition 0.1 [get_ports { ddr3_dq[17] }]
set_input_transition 0.1 [get_ports { ddr3_dq[16] }]
set_input_transition 0.1 [get_ports { ddr3_dq[15] }]
set_input_transition 0.1 [get_ports { ddr3_dq[14] }]
set_input_transition 0.1 [get_ports { ddr3_dq[13] }]
set_input_transition 0.1 [get_ports { ddr3_dq[12] }]
set_input_transition 0.1 [get_ports { ddr3_dq[11] }]
set_input_transition 0.1 [get_ports { ddr3_dq[10] }]
set_input_transition 0.1 [get_ports { ddr3_dq[9] }]
set_input_transition 0.1 [get_ports { ddr3_dq[8] }]
set_input_transition 0.1 [get_ports { ddr3_dq[7] }]
set_input_transition 0.1 [get_ports { ddr3_dq[6] }]
set_input_transition 0.1 [get_ports { ddr3_dq[5] }]
set_input_transition 0.1 [get_ports { ddr3_dq[4] }]
set_input_transition 0.1 [get_ports { ddr3_dq[3] }]
set_input_transition 0.1 [get_ports { ddr3_dq[2] }]
set_input_transition 0.1 [get_ports { ddr3_dq[1] }]
set_input_transition 0.1 [get_ports { ddr3_dq[0] }]
set_input_transition 0.1 [get_ports usb_plus]
set_input_transition 0.1 [get_ports usb_minus]
set_input_transition 0.1 [get_ports reset_n]
set_input_transition 0.1 [get_ports { BS_data_0[15] }]
set_input_transition 0.1 [get_ports { BS_data_0[14] }]
set_input_transition 0.1 [get_ports { BS_data_0[13] }]
set_input_transition 0.1 [get_ports { BS_data_0[12] }]
set_input_transition 0.1 [get_ports { BS_data_0[11] }]
set_input_transition 0.1 [get_ports { BS_data_0[10] }]
set_input_transition 0.1 [get_ports { BS_data_0[9] }]
set_input_transition 0.1 [get_ports { BS_data_0[8] }]
set_input_transition 0.1 [get_ports { BS_data_0[7] }]
set_input_transition 0.1 [get_ports { BS_data_0[6] }]
set_input_transition 0.1 [get_ports { BS_data_0[5] }]
set_input_transition 0.1 [get_ports { BS_data_0[4] }]
set_input_transition 0.1 [get_ports { BS_data_0[3] }]
set_input_transition 0.1 [get_ports { BS_data_0[2] }]
set_input_transition 0.1 [get_ports { BS_data_0[1] }]
set_input_transition 0.1 [get_ports { BS_data_0[0] }]
set_input_transition 0.1 [get_ports { BS_data_1[15] }]
set_input_transition 0.1 [get_ports { BS_data_1[14] }]
set_input_transition 0.1 [get_ports { BS_data_1[13] }]
set_input_transition 0.1 [get_ports { BS_data_1[12] }]
set_input_transition 0.1 [get_ports { BS_data_1[11] }]
set_input_transition 0.1 [get_ports { BS_data_1[10] }]
set_input_transition 0.1 [get_ports { BS_data_1[9] }]
set_input_transition 0.1 [get_ports { BS_data_1[8] }]
set_input_transition 0.1 [get_ports { BS_data_1[7] }]
set_input_transition 0.1 [get_ports { BS_data_1[6] }]
set_input_transition 0.1 [get_ports { BS_data_1[5] }]
set_input_transition 0.1 [get_ports { BS_data_1[4] }]
set_input_transition 0.1 [get_ports { BS_data_1[3] }]
set_input_transition 0.1 [get_ports { BS_data_1[2] }]
set_input_transition 0.1 [get_ports { BS_data_1[1] }]
set_input_transition 0.1 [get_ports { BS_data_1[0] }]
set_input_transition 0.1 [get_ports lfxt_clk]
set_input_transition 0.1 [get_ports nmi]
set_input_transition 0.1 [get_ports scan_mode]
set_input_transition 0.1 [get_ports sysclk_byp]
set_input_transition 0.1 [get_ports usbclk_byp]
set_case_analysis 0 [get_ports scan_mode]
set_input_delay 0.7 [get_ports usb_minus]
set_input_delay 0.7 [get_ports usb_plus]
set_clock_groups -name CLOCK_GROUP__0 -asynchronous -group [get_clocks lfxt_clk] -group [get_clocks sysclk] -group [get_clocks usbclk]

29
constraints/define_regions.def Executable file
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#
# Created by Oasys-RTL -- (c) Mentor Graphics Corporation
#
VERSION 5.8 ;
NAMESCASESENSITIVE ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN demo_chip ;
UNITS DISTANCE MICRONS 2000 ;
PROPERTYDEFINITIONS
END PROPERTYDEFINITIONS
DIEAREA ( 0 0 ) ( 2834850 2834850 ) ;
REGIONS 2 ;
- __r__6 ( 64840 50430 ) ( 1549550 1203580 ) ;
- __r__7 ( 1254060 1513530 ) ( 2803620 2767590 ) ;
END REGIONS
COMPONENTS 352 ;
- i_cpu_sys cpu_sys
+ REGION __r__6
;
- i_usbf usb_sys
+ REGION __r__7
;
END COMPONENTS
END DESIGN

89
constraints/demo_chip_func.sdc Executable file
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######################################################################
# Design : demo_chip
# SDC timing constraint file
######################################################################
set clock_period 100.0
set sysclk_multiplier 40
set usbclk_multiplier 6
set clock_margin 0.20
set pad_load 10
set transition 0.1
set io_clock_period [ expr ${clock_period} / ${sysclk_multiplier} ]
set io_clock_period_ddr [ expr ${io_clock_period} / 2 ]
# ------------------------------------------------------------------
# Clock definitions
# ------------------------------------------------------------------
# PLL input clock 10MHz
create_clock -name lfxt_clk -period ${clock_period} [ get_ports lfxt_clk ]
# Main system clock - 400MHz
create_generated_clock \
-name sysclk \
-source [ get_pins i_MAIN_PLL/REF ] \
-multiply_by ${sysclk_multiplier} \
-add -master_clock lfxt_clk \
[ get_pins i_MAIN_PLL/PLLOUT ]
# USB clock - 60MHz
create_generated_clock \
-name usbclk \
-source [ get_pins i_USB_PLL/REF ] \
-multiply_by ${usbclk_multiplier} \
-add -master_clock lfxt_clk \
[ get_pins i_USB_PLL/PLLOUT ]
# Scan mode clocks
create_clock -name sysclk_byp -period ${clock_period} [ get_ports sysclk_byp ]
create_clock -name usbclk_byp -period ${clock_period} [ get_ports usbclk_byp ]
# Virtual clocks for I/O and DDR timing
create_clock -name vsysclk -period ${io_clock_period}
create_clock -name vsysclk_ddr -period ${io_clock_period_ddr}
# Apply uncertainties to clocks
set_clock_uncertainty -setup ${clock_margin} [ get_clocks sysclk ]
set_clock_uncertainty -setup ${clock_margin} [ get_clocks usbclk ]
# ------------------------------------------------------------------
# port timings
# ------------------------------------------------------------------
set_input_delay 0.4 [get_ports usb_minus]
set_input_delay 0.4 [get_ports usb_plus]
set_input_delay -clock vsysclk [ expr 0.4 *${io_clock_period} ] \
[ remove_from_collection [ all_inputs ] [ get_ports { lfxt_clk usb_plus usb_minus ddr*dq }] ]
set_output_delay -clock vsysclk [ expr 0.3 * ${io_clock_period} ] \
[ remove_from_collection [ all_outputs ] [ get_ports { usb_plus usb_minus }] ]
# DDR input timings
set_input_delay -clock vsysclk_ddr [ expr 0.4 * ${io_clock_period_ddr} ] \
[ get_ports { ddr*dq* }]
# ------------------------------------------------------------------
# external conditions
# ------------------------------------------------------------------
set_load ${pad_load} [ all_outputs ]
set_input_transition ${transition} [ all_inputs ]
# ------------------------------------------------------------------
# Exceptions
# ------------------------------------------------------------------
# NMI and reset are asynchronous
set_false_path -from [ get_ports nmi ]
set_false_path -from [ get_ports reset_n ]
# Power up/down will take long time --> set false paths
set_false_path -through [ get_pins {nova0/power_control nova0/power_ack nova1/power_control nova1/power_ack i_usbf/*power_control i_usbf/*power_ack }]
# All clock domain crossings are async
set_clock_groups -asynchronous \
-group lfxt_clk \
-group sysclk \
-group usbclk
# Block scan clocks with case analysis
set_case_analysis 0 [get_ports scan_mode]
set_false_path -from SCAN_ENABLE
set_input_delay 0.7 [get_ports usb_minus]
set_input_delay 0.7 [get_ports usb_plus]

76
constraints/riscv.sdc Normal file
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# =============================================================================
# Constraints File: cpu.sdc
# Project: BCDC Microtec Academy - RISC-V CPU
# Top Module: cpu
# =============================================================================
# -----------------------------------------------------------------------------
# 1. Primary Clock - 25 MHz input clock
# -----------------------------------------------------------------------------
create_clock -name clk_25mhz \
-period 40.000 \
-waveform {0 20} \
[get_ports clk_25mhz]
# -----------------------------------------------------------------------------
# 2. Generated Clock - 12.5 MHz (divided by 2 inside always_ff)
# -----------------------------------------------------------------------------
#create_generated_clock -name clk_12p5 \
# -source [get_ports clk_25mhz] \
# -divide_by 2 \
# [get_pins thePC/clk]
# -----------------------------------------------------------------------------
# 3. Clock Uncertainty & Transition
# -----------------------------------------------------------------------------
set_clock_uncertainty -setup 0.5 [get_clocks clk_25mhz]
set_clock_uncertainty -hold 0.2 [get_clocks clk_25mhz]
set_clock_transition 0.1 [get_clocks clk_25mhz]
# -----------------------------------------------------------------------------
# 4. Input Delays (btn pins - relative to clk_25mhz)
# -----------------------------------------------------------------------------
set_input_delay -clock clk_25mhz -max 2.0 [get_ports {btn[*]}]
set_input_delay -clock clk_25mhz -min 0.5 [get_ports {btn[*]}]
# -----------------------------------------------------------------------------
# 5. Output Delays (led pins)
# -----------------------------------------------------------------------------
set_output_delay -clock clk_25mhz -max 2.0 [get_ports {led[*]}]
set_output_delay -clock clk_25mhz -min 0.5 [get_ports {led[*]}]
# -----------------------------------------------------------------------------
# 6. False Paths
# -----------------------------------------------------------------------------
# Reset is async and driven from a button - no timing analysis needed
set_false_path -from [get_ports {btn[0]}]
# LED outputs driven from combinational/slow logic - relax if needed
# set_false_path -to [get_ports {led[*]}]
# -----------------------------------------------------------------------------
# 7. Clock Domain Crossing
# -----------------------------------------------------------------------------
# clk12p5 is derived from clk_25mhz via FF division - set as async crossing
# to prevent hold violations across the two domains
#set_clock_groups -asynchronous \
-group [get_clocks clk_25mhz] \
-group [get_clocks clk_12p5]
# -----------------------------------------------------------------------------
# 8. Drive Strength & Load (adjust to your target technology)
# -----------------------------------------------------------------------------
#set_driving_cell -lib_cell <YOUR_INPUT_BUF> [get_ports {btn[*]}]
set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[*]}]
set_load 0.05 [get_ports {led[*]}]
# -----------------------------------------------------------------------------
# 9. Max Fanout & Transition
# -----------------------------------------------------------------------------
set_max_fanout 20 [current_design]
set_max_transition 0.5 [current_design]

355
cpu_patterns.stil Normal file
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STIL 1.0;
Header {
Title "cpu_cpu_patterns_stil" ;
Date "Thu May 28 18:01:24 2026" ;
Source "Tessent Shell 2023.4-p1" ;
History {
Ann {* Fault : STUCK *}
Ann {* Coverage : 25.96(TC) 24.58(FC) *}
Ann {* Begin_Verify_Section *}
Ann {* format = STIL *}
Ann {* serial_flag = OFF *}
Ann {* test_set_type = ALL_TEST *}
Ann {* pad_value = X *}
Ann {* pattern_begin = 0 *}
Ann {* pattern_end = 9 *}
Ann {* one_setup = ON *}
Ann {* no_initialization = ON *}
Ann {* pattern_checksum = 94986 *}
Ann {* End_Verify_Section *}
}
}
Signals {
"btn"[6] In; "btn"[5] In; "btn"[4] In; "btn"[3] In; "btn"[2] In; "btn"[1] In; "btn"[0] In; "clk_25mhz" In; "scan_en" In; "SI_1" In; "SI_2" In; "SI_3" In; "SI_4" In;
"led"[7] Out; "led"[6] Out; "led"[5] Out; "led"[4] Out; "led"[3] Out; "led"[2] Out; "led"[1] Out; "led"[0] Out; "SO_1" Out; "SO_2" Out; "SO_3" Out; "SO_4" Out;
}
SignalGroups {
_pi_ = '"btn"[6] + "btn"[5] + "btn"[4] + "btn"[3] + "btn"[2] + "btn"[1] + "btn"[0] + "clk_25mhz" + "scan_en" + "SI_1" + "SI_2" + "SI_3" + "SI_4"';
_po_ = '"led"[7] + "led"[6] + "led"[5] + "led"[4] + "led"[3] + "led"[2] + "led"[1] + "led"[0] + "SO_1" + "SO_2" + "SO_3" + "SO_4"';
input_time_gen_0 = '"btn"[6] + "btn"[5] + "btn"[4] + "btn"[3] + "btn"[2] + "btn"[1] + "btn"[0] + "scan_en" + "SI_1" + "SI_2" + "SI_3" + "SI_4"';
input_time_gen_1 = '"clk_25mhz"';
"_unwrapped_chain1_SI_1_" = '"SI_1"' {ScanIn 256;}
"_unwrapped_chain1_SO_1_" = '"SO_1"' {ScanOut 256;}
"_unwrapped_chain2_SI_2_" = '"SI_2"' {ScanIn 256;}
"_unwrapped_chain2_SO_2_" = '"SO_2"' {ScanOut 256;}
"_unwrapped_chain3_SI_3_" = '"SI_3"' {ScanIn 256;}
"_unwrapped_chain3_SO_3_" = '"SO_3"' {ScanOut 256;}
"_unwrapped_chain4_SI_4_" = '"SI_4"' {ScanIn 256;}
"_unwrapped_chain4_SO_4_" = '"SO_4"' {ScanOut 256;}
}
Timing STUCK_timing {
WaveformTable tset_gen_tp1 {
Period '40ns' ;
Waveforms {
input_time_gen_0 { 01NZ { '0ns' D/U/N/Z; }}
input_time_gen_1 { 01 { '0ns' D; '20ns' D/U; '30ns' D;}}
_po_ { LHXT { '10ns' L/H/X/T;}}
}
}
}
ScanStructures {
ScanChain unwrapped_chain1 {
ScanLength 256;
ScanInversion 0;
ScanCells "\thePC_CurrentPC_reg[30] " "\thePC_CurrentPC_reg[29] " "\thePC_CurrentPC_reg[28] " "\thePC_CurrentPC_reg[27] " "\thePC_CurrentPC_reg[26] " "\thePC_CurrentPC_reg[25] " "\thePC_CurrentPC_reg[24] " "\thePC_CurrentPC_reg[23] " "\thePC_CurrentPC_reg[22] " "\thePC_CurrentPC_reg[21] " "\thePC_CurrentPC_reg[20] " "\thePC_CurrentPC_reg[19] " "\thePC_CurrentPC_reg[18] " "\thePC_CurrentPC_reg[17] " "\thePC_CurrentPC_reg[16] " "\thePC_CurrentPC_reg[15] " "\thePC_CurrentPC_reg[14] " "\thePC_CurrentPC_reg[13] " "\thePC_CurrentPC_reg[12] " "\thePC_CurrentPC_reg[11] " "\thePC_CurrentPC_reg[10] " "\thePC_CurrentPC_reg[9] " "\thePC_CurrentPC_reg[8] " "\thePC_CurrentPC_reg[7] " "\thePC_CurrentPC_reg[6] " "\thePC_CurrentPC_reg[5] " "\thePC_CurrentPC_reg[4] " "\thePC_CurrentPC_reg[3] " "\thePC_CurrentPC_reg[2] " "\thePC_CurrentPC_reg[31] " "\thePC_CurrentPC_reg[1] " "\thePC_CurrentPC_reg[0] " "theRegisters.\registers_reg[16][31] " "theRegisters.\registers_reg[10][31] " "theRegisters.\registers_reg[12][31] "
"theRegisters.\registers_reg[11][31] " "theRegisters.\registers_reg[13][31] " "theRegisters.\registers_reg[15][31] " "theRegisters.\registers_reg[14][31] " "theRegisters.\registers_reg[16][30] " "theRegisters.\registers_reg[10][30] " "theRegisters.\registers_reg[12][30] " "theRegisters.\registers_reg[11][30] " "theRegisters.\registers_reg[13][30] " "theRegisters.\registers_reg[15][30] " "theRegisters.\registers_reg[14][30] " "theRegisters.\registers_reg[10][29] " "theRegisters.\registers_reg[13][29] " "theRegisters.\registers_reg[12][29] " "theRegisters.\registers_reg[15][29] " "theRegisters.\registers_reg[16][29] " "theRegisters.\registers_reg[14][29] " "theRegisters.\registers_reg[11][29] " "theRegisters.\registers_reg[15][28] " "theRegisters.\registers_reg[12][28] " "theRegisters.\registers_reg[14][28] " "theRegisters.\registers_reg[13][28] " "theRegisters.\registers_reg[10][28] " "theRegisters.\registers_reg[16][28] " "theRegisters.\registers_reg[11][28] " "theRegisters.\registers_reg[11][27] "
"theRegisters.\registers_reg[16][27] " "theRegisters.\registers_reg[10][27] " "theRegisters.\registers_reg[12][27] " "theRegisters.\registers_reg[13][27] " "theRegisters.\registers_reg[15][27] " "theRegisters.\registers_reg[14][27] " "theRegisters.\registers_reg[11][26] " "theRegisters.\registers_reg[16][26] " "theRegisters.\registers_reg[12][26] " "theRegisters.\registers_reg[13][26] " "theRegisters.\registers_reg[15][26] " "theRegisters.\registers_reg[14][26] " "theRegisters.\registers_reg[10][26] " "theRegisters.\registers_reg[12][25] " "theRegisters.\registers_reg[11][25] " "theRegisters.\registers_reg[10][25] " "theRegisters.\registers_reg[13][25] " "theRegisters.\registers_reg[15][25] " "theRegisters.\registers_reg[16][25] " "theRegisters.\registers_reg[14][25] " "theRegisters.\registers_reg[12][24] " "theRegisters.\registers_reg[11][24] " "theRegisters.\registers_reg[10][24] " "theRegisters.\registers_reg[13][24] " "theRegisters.\registers_reg[15][24] " "theRegisters.\registers_reg[16][24] "
"theRegisters.\registers_reg[14][24] " "theRegisters.\registers_reg[15][23] " "theRegisters.\registers_reg[14][23] " "theRegisters.\registers_reg[16][23] " "theRegisters.\registers_reg[11][23] " "theRegisters.\registers_reg[13][23] " "theRegisters.\registers_reg[12][23] " "theRegisters.\registers_reg[10][23] " "theRegisters.\registers_reg[11][22] " "theRegisters.\registers_reg[12][22] " "theRegisters.\registers_reg[10][22] " "theRegisters.\registers_reg[13][22] " "theRegisters.\registers_reg[15][22] " "theRegisters.\registers_reg[16][22] " "theRegisters.\registers_reg[14][22] " "theRegisters.\registers_reg[12][21] " "theRegisters.\registers_reg[11][21] " "theRegisters.\registers_reg[10][21] " "theRegisters.\registers_reg[13][21] " "theRegisters.\registers_reg[15][21] " "theRegisters.\registers_reg[16][21] " "theRegisters.\registers_reg[14][21] " "theRegisters.\registers_reg[10][20] " "theRegisters.\registers_reg[12][20] " "theRegisters.\registers_reg[15][20] " "theRegisters.\registers_reg[11][20] "
"theRegisters.\registers_reg[13][20] " "theRegisters.\registers_reg[16][20] " "theRegisters.\registers_reg[14][20] " "theRegisters.\registers_reg[12][19] " "theRegisters.\registers_reg[15][19] " "theRegisters.\registers_reg[11][19] " "theRegisters.\registers_reg[13][19] " "theRegisters.\registers_reg[16][19] " "theRegisters.\registers_reg[14][19] " "theRegisters.\registers_reg[10][19] " "theRegisters.\registers_reg[11][18] " "theRegisters.\registers_reg[16][18] " "theRegisters.\registers_reg[12][18] " "theRegisters.\registers_reg[13][18] " "theRegisters.\registers_reg[15][18] " "theRegisters.\registers_reg[14][18] " "theRegisters.\registers_reg[10][18] " "theRegisters.\registers_reg[12][17] " "theRegisters.\registers_reg[15][17] " "theRegisters.\registers_reg[11][17] " "theRegisters.\registers_reg[10][17] " "theRegisters.\registers_reg[13][17] " "theRegisters.\registers_reg[16][17] " "theRegisters.\registers_reg[14][17] " "theRegisters.\registers_reg[11][16] " "theRegisters.\registers_reg[10][16] "
"theRegisters.\registers_reg[16][16] " "theRegisters.\registers_reg[12][16] " "theRegisters.\registers_reg[13][16] " "theRegisters.\registers_reg[15][16] " "theRegisters.\registers_reg[14][16] " "theRegisters.\registers_reg[10][15] " "theRegisters.\registers_reg[12][15] " "theRegisters.\registers_reg[15][15] " "theRegisters.\registers_reg[11][15] " "theRegisters.\registers_reg[13][15] " "theRegisters.\registers_reg[16][15] " "theRegisters.\registers_reg[14][15] " "theRegisters.\registers_reg[10][14] " "theRegisters.\registers_reg[14][14] " "theRegisters.\registers_reg[16][14] " "theRegisters.\registers_reg[15][14] " "theRegisters.\registers_reg[12][14] " "theRegisters.\registers_reg[13][14] " "theRegisters.\registers_reg[11][14] " "theRegisters.\registers_reg[10][13] " "theRegisters.\registers_reg[16][13] " "theRegisters.\registers_reg[15][13] " "theRegisters.\registers_reg[12][13] " "theRegisters.\registers_reg[13][13] " "theRegisters.\registers_reg[14][13] " "theRegisters.\registers_reg[11][13] "
"theRegisters.\registers_reg[10][12] " "theRegisters.\registers_reg[16][12] " "theRegisters.\registers_reg[15][12] " "theRegisters.\registers_reg[12][12] " "theRegisters.\registers_reg[13][12] " "theRegisters.\registers_reg[14][12] " "theRegisters.\registers_reg[11][12] " "theRegisters.\registers_reg[10][11] " "theRegisters.\registers_reg[16][11] " "theRegisters.\registers_reg[15][11] " "theRegisters.\registers_reg[12][11] " "theRegisters.\registers_reg[13][11] " "theRegisters.\registers_reg[14][11] " "theRegisters.\registers_reg[11][11] " "theRegisters.\registers_reg[10][10] " "theRegisters.\registers_reg[13][10] " "theRegisters.\registers_reg[12][10] " "theRegisters.\registers_reg[15][10] " "theRegisters.\registers_reg[16][10] " "theRegisters.\registers_reg[14][10] " "theRegisters.\registers_reg[11][10] " "theRegisters.\registers_reg[13][9] " "theRegisters.\registers_reg[10][9] " "theRegisters.\registers_reg[12][9] " "theRegisters.\registers_reg[15][9] " "theRegisters.\registers_reg[16][9] "
"theRegisters.\registers_reg[14][9] " "theRegisters.\registers_reg[11][9] " "theRegisters.\registers_reg[13][8] " "theRegisters.\registers_reg[10][8] " "theRegisters.\registers_reg[12][8] " "theRegisters.\registers_reg[15][8] " "theRegisters.\registers_reg[16][8] " "theRegisters.\registers_reg[14][8] " "theRegisters.\registers_reg[11][8] " "theRegisters.\registers_reg[13][7] " "theRegisters.\registers_reg[10][7] " "theRegisters.\registers_reg[11][7] " "theRegisters.\registers_reg[12][7] " "theRegisters.\registers_reg[15][7] " "theRegisters.\registers_reg[16][7] " "theRegisters.\registers_reg[14][7] " "theRegisters.\registers_reg[10][6] " "theRegisters.\registers_reg[15][6] " "theRegisters.\registers_reg[11][6] " "theRegisters.\registers_reg[16][6] " "theRegisters.\registers_reg[12][6] " "theRegisters.\registers_reg[13][6] " "theRegisters.\registers_reg[14][6] " "theRegisters.\registers_reg[10][5] " "theRegisters.\registers_reg[16][5] " "theRegisters.\registers_reg[15][5] " "theRegisters.\registers_reg[12][5] "
"theRegisters.\registers_reg[13][5] " "theRegisters.\registers_reg[14][5] " "theRegisters.\registers_reg[11][5] " "theRegisters.\registers_reg[10][4] " "theRegisters.\registers_reg[13][4] " "theRegisters.\registers_reg[12][4] " "theRegisters.\registers_reg[11][4] " "theRegisters.\registers_reg[14][4] " "theRegisters.\registers_reg[15][4] " "theRegisters.\registers_reg[16][4] " "theRegisters.\registers_reg[10][3] " "theRegisters.\registers_reg[16][3] " "theRegisters.\registers_reg[15][3] " "theRegisters.\registers_reg[12][3] " "theRegisters.\registers_reg[13][3] " "theRegisters.\registers_reg[14][3] " "theRegisters.\registers_reg[11][3] " "theRegisters.\registers_reg[16][2] " "theRegisters.\registers_reg[15][2] " "theRegisters.\registers_reg[11][2] " "theRegisters.\registers_reg[10][2] " "theRegisters.\registers_reg[12][2] " "theRegisters.\registers_reg[13][2] " "theRegisters.\registers_reg[14][2] " "theRegisters.\registers_reg[13][1] " "theRegisters.\registers_reg[10][1] " "theRegisters.\registers_reg[12][1] "
"theRegisters.\registers_reg[15][1] " "theRegisters.\registers_reg[16][1] " "theRegisters.\registers_reg[14][1] " "theRegisters.\registers_reg[11][1] " "theRegisters.\registers_reg[13][0] " "theRegisters.\registers_reg[10][0] " "theRegisters.\registers_reg[12][0] " "theRegisters.\registers_reg[15][0] " "theRegisters.\registers_reg[16][0] " "theRegisters.\registers_reg[14][0] " "theRegisters.\registers_reg[11][0] " ;
ScanIn "SI_1";
ScanOut "SO_1";
ScanMasterClock "clk_25mhz";
}
ScanChain unwrapped_chain2 {
ScanLength 256;
ScanInversion 0;
ScanCells "theRegisters.\registers_reg[1][31] " "theRegisters.\registers_reg[23][31] " "theRegisters.\registers_reg[19][31] " "theRegisters.\registers_reg[18][31] " "theRegisters.\registers_reg[22][31] " "theRegisters.\registers_reg[21][31] " "theRegisters.\registers_reg[17][31] " "theRegisters.\registers_reg[20][31] " "theRegisters.\registers_reg[17][30] " "theRegisters.\registers_reg[1][30] " "theRegisters.\registers_reg[23][30] " "theRegisters.\registers_reg[19][30] " "theRegisters.\registers_reg[18][30] " "theRegisters.\registers_reg[20][30] " "theRegisters.\registers_reg[22][30] " "theRegisters.\registers_reg[21][30] " "theRegisters.\registers_reg[20][29] " "theRegisters.\registers_reg[19][29] " "theRegisters.\registers_reg[23][29] " "theRegisters.\registers_reg[21][29] " "theRegisters.\registers_reg[18][29] " "theRegisters.\registers_reg[17][29] " "theRegisters.\registers_reg[22][29] " "theRegisters.\registers_reg[1][29] " "theRegisters.\registers_reg[22][28] " "theRegisters.\registers_reg[17][28] "
"theRegisters.\registers_reg[20][28] " "theRegisters.\registers_reg[1][28] " "theRegisters.\registers_reg[23][28] " "theRegisters.\registers_reg[21][28] " "theRegisters.\registers_reg[19][28] " "theRegisters.\registers_reg[18][28] " "theRegisters.\registers_reg[1][27] " "theRegisters.\registers_reg[22][27] " "theRegisters.\registers_reg[19][27] " "theRegisters.\registers_reg[21][27] " "theRegisters.\registers_reg[20][27] " "theRegisters.\registers_reg[18][27] " "theRegisters.\registers_reg[23][27] " "theRegisters.\registers_reg[17][27] " "theRegisters.\registers_reg[18][26] " "theRegisters.\registers_reg[22][26] " "theRegisters.\registers_reg[1][26] " "theRegisters.\registers_reg[19][26] " "theRegisters.\registers_reg[21][26] " "theRegisters.\registers_reg[20][26] " "theRegisters.\registers_reg[23][26] " "theRegisters.\registers_reg[17][26] " "theRegisters.\registers_reg[17][25] " "theRegisters.\registers_reg[21][25] " "theRegisters.\registers_reg[20][25] " "theRegisters.\registers_reg[22][25] "
"theRegisters.\registers_reg[1][25] " "theRegisters.\registers_reg[18][25] " "theRegisters.\registers_reg[19][25] " "theRegisters.\registers_reg[23][25] " "theRegisters.\registers_reg[17][24] " "theRegisters.\registers_reg[21][24] " "theRegisters.\registers_reg[20][24] " "theRegisters.\registers_reg[22][24] " "theRegisters.\registers_reg[1][24] " "theRegisters.\registers_reg[18][24] " "theRegisters.\registers_reg[19][24] " "theRegisters.\registers_reg[23][24] " "theRegisters.\registers_reg[18][23] " "theRegisters.\registers_reg[22][23] " "theRegisters.\registers_reg[1][23] " "theRegisters.\registers_reg[21][23] " "theRegisters.\registers_reg[20][23] " "theRegisters.\registers_reg[19][23] " "theRegisters.\registers_reg[23][23] " "theRegisters.\registers_reg[17][23] " "theRegisters.\registers_reg[17][22] " "theRegisters.\registers_reg[21][22] " "theRegisters.\registers_reg[20][22] " "theRegisters.\registers_reg[22][22] " "theRegisters.\registers_reg[1][22] " "theRegisters.\registers_reg[18][22] "
"theRegisters.\registers_reg[19][22] " "theRegisters.\registers_reg[23][22] " "theRegisters.\registers_reg[17][21] " "theRegisters.\registers_reg[21][21] " "theRegisters.\registers_reg[20][21] " "theRegisters.\registers_reg[22][21] " "theRegisters.\registers_reg[1][21] " "theRegisters.\registers_reg[18][21] " "theRegisters.\registers_reg[19][21] " "theRegisters.\registers_reg[23][21] " "theRegisters.\registers_reg[17][20] " "theRegisters.\registers_reg[21][20] " "theRegisters.\registers_reg[20][20] " "theRegisters.\registers_reg[22][20] " "theRegisters.\registers_reg[1][20] " "theRegisters.\registers_reg[18][20] " "theRegisters.\registers_reg[19][20] " "theRegisters.\registers_reg[23][20] " "theRegisters.\registers_reg[17][19] " "theRegisters.\registers_reg[21][19] " "theRegisters.\registers_reg[20][19] " "theRegisters.\registers_reg[22][19] " "theRegisters.\registers_reg[1][19] " "theRegisters.\registers_reg[18][19] " "theRegisters.\registers_reg[19][19] " "theRegisters.\registers_reg[23][19] "
"theRegisters.\registers_reg[22][18] " "theRegisters.\registers_reg[1][18] " "theRegisters.\registers_reg[18][18] " "theRegisters.\registers_reg[19][18] " "theRegisters.\registers_reg[21][18] " "theRegisters.\registers_reg[20][18] " "theRegisters.\registers_reg[23][18] " "theRegisters.\registers_reg[17][18] " "theRegisters.\registers_reg[17][17] " "theRegisters.\registers_reg[21][17] " "theRegisters.\registers_reg[20][17] " "theRegisters.\registers_reg[22][17] " "theRegisters.\registers_reg[1][17] " "theRegisters.\registers_reg[18][17] " "theRegisters.\registers_reg[19][17] " "theRegisters.\registers_reg[23][17] " "theRegisters.\registers_reg[18][16] " "theRegisters.\registers_reg[22][16] " "theRegisters.\registers_reg[1][16] " "theRegisters.\registers_reg[19][16] " "theRegisters.\registers_reg[21][16] " "theRegisters.\registers_reg[20][16] " "theRegisters.\registers_reg[23][16] " "theRegisters.\registers_reg[17][16] " "theRegisters.\registers_reg[17][15] " "theRegisters.\registers_reg[21][15] "
"theRegisters.\registers_reg[20][15] " "theRegisters.\registers_reg[22][15] " "theRegisters.\registers_reg[1][15] " "theRegisters.\registers_reg[18][15] " "theRegisters.\registers_reg[19][15] " "theRegisters.\registers_reg[23][15] " "theRegisters.\registers_reg[18][14] " "theRegisters.\registers_reg[21][14] " "theRegisters.\registers_reg[17][14] " "theRegisters.\registers_reg[23][14] " "theRegisters.\registers_reg[20][14] " "theRegisters.\registers_reg[1][14] " "theRegisters.\registers_reg[19][14] " "theRegisters.\registers_reg[22][14] " "theRegisters.\registers_reg[1][13] " "theRegisters.\registers_reg[23][13] " "theRegisters.\registers_reg[18][13] " "theRegisters.\registers_reg[22][13] " "theRegisters.\registers_reg[21][13] " "theRegisters.\registers_reg[20][13] " "theRegisters.\registers_reg[17][13] " "theRegisters.\registers_reg[19][13] " "theRegisters.\registers_reg[17][12] " "theRegisters.\registers_reg[1][12] " "theRegisters.\registers_reg[23][12] " "theRegisters.\registers_reg[18][12] "
"theRegisters.\registers_reg[20][12] " "theRegisters.\registers_reg[22][12] " "theRegisters.\registers_reg[21][12] " "theRegisters.\registers_reg[19][12] " "theRegisters.\registers_reg[17][11] " "theRegisters.\registers_reg[1][11] " "theRegisters.\registers_reg[23][11] " "theRegisters.\registers_reg[18][11] " "theRegisters.\registers_reg[20][11] " "theRegisters.\registers_reg[22][11] " "theRegisters.\registers_reg[21][11] " "theRegisters.\registers_reg[19][11] " "theRegisters.\registers_reg[20][10] " "theRegisters.\registers_reg[23][10] " "theRegisters.\registers_reg[21][10] " "theRegisters.\registers_reg[18][10] " "theRegisters.\registers_reg[17][10] " "theRegisters.\registers_reg[22][10] " "theRegisters.\registers_reg[1][10] " "theRegisters.\registers_reg[19][10] " "theRegisters.\registers_reg[21][9] " "theRegisters.\registers_reg[23][9] " "theRegisters.\registers_reg[20][9] " "theRegisters.\registers_reg[18][9] " "theRegisters.\registers_reg[17][9] " "theRegisters.\registers_reg[22][9] " "theRegisters.\registers_reg[1][9] "
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"theRegisters.\registers_reg[6][11] " "theRegisters.\registers_reg[5][11] " "theRegisters.\registers_reg[3][11] " "theRegisters.\registers_reg[31][11] " "theRegisters.\registers_reg[4][11] " "theRegisters.\registers_reg[7][11] " "theRegisters.\registers_reg[8][10] " "theRegisters.\registers_reg[31][10] " "theRegisters.\registers_reg[7][10] " "theRegisters.\registers_reg[4][10] " "theRegisters.\registers_reg[5][10] " "theRegisters.\registers_reg[9][10] " "theRegisters.\registers_reg[6][10] " "theRegisters.\registers_reg[3][10] " "theRegisters.\registers_reg[7][9] " "theRegisters.\registers_reg[3][9] " "theRegisters.\registers_reg[31][9] " "theRegisters.\registers_reg[4][9] " "theRegisters.\registers_reg[8][9] " "theRegisters.\registers_reg[5][9] " "theRegisters.\registers_reg[9][9] " "theRegisters.\registers_reg[6][9] " "theRegisters.\registers_reg[7][8] " "theRegisters.\registers_reg[3][8] " "theRegisters.\registers_reg[31][8] " "theRegisters.\registers_reg[4][8] " "theRegisters.\registers_reg[8][8] "
"theRegisters.\registers_reg[5][8] " "theRegisters.\registers_reg[9][8] " "theRegisters.\registers_reg[6][8] " "theRegisters.\registers_reg[8][7] " "theRegisters.\registers_reg[31][7] " "theRegisters.\registers_reg[7][7] " "theRegisters.\registers_reg[4][7] " "theRegisters.\registers_reg[5][7] " "theRegisters.\registers_reg[3][7] " "theRegisters.\registers_reg[9][7] " "theRegisters.\registers_reg[6][7] " "theRegisters.\registers_reg[8][6] " "theRegisters.\registers_reg[9][6] " "theRegisters.\registers_reg[6][6] " "theRegisters.\registers_reg[5][6] " "theRegisters.\registers_reg[31][6] " "theRegisters.\registers_reg[4][6] " "theRegisters.\registers_reg[7][6] " "theRegisters.\registers_reg[3][6] " "theRegisters.\registers_reg[4][5] " "theRegisters.\registers_reg[8][5] " "theRegisters.\registers_reg[9][5] " "theRegisters.\registers_reg[6][5] " "theRegisters.\registers_reg[3][5] " "theRegisters.\registers_reg[5][5] " "theRegisters.\registers_reg[31][5] " "theRegisters.\registers_reg[7][5] " "theRegisters.\registers_reg[9][4] "
"theRegisters.\registers_reg[8][4] " "theRegisters.\registers_reg[3][4] " "theRegisters.\registers_reg[31][4] " "theRegisters.\registers_reg[7][4] " "theRegisters.\registers_reg[4][4] " "theRegisters.\registers_reg[6][4] " "theRegisters.\registers_reg[5][4] " "theRegisters.\registers_reg[8][3] " "theRegisters.\registers_reg[9][3] " "theRegisters.\registers_reg[6][3] " "theRegisters.\registers_reg[3][3] " "theRegisters.\registers_reg[5][3] " "theRegisters.\registers_reg[31][3] " "theRegisters.\registers_reg[4][3] " "theRegisters.\registers_reg[7][3] " "theRegisters.\registers_reg[4][2] " "theRegisters.\registers_reg[31][2] " "theRegisters.\registers_reg[6][2] " "theRegisters.\registers_reg[5][2] " "theRegisters.\registers_reg[8][2] " "theRegisters.\registers_reg[9][2] " "theRegisters.\registers_reg[7][2] " "theRegisters.\registers_reg[3][2] " "theRegisters.\registers_reg[7][1] " "theRegisters.\registers_reg[3][1] " "theRegisters.\registers_reg[31][1] " "theRegisters.\registers_reg[4][1] " "theRegisters.\registers_reg[8][1] "
"theRegisters.\registers_reg[5][1] " "theRegisters.\registers_reg[9][1] " "theRegisters.\registers_reg[6][1] " "theRegisters.\registers_reg[8][0] " "theRegisters.\registers_reg[7][0] " "theRegisters.\registers_reg[3][0] " "theRegisters.\registers_reg[31][0] " "theRegisters.\registers_reg[4][0] " "theRegisters.\registers_reg[5][0] " "theRegisters.\registers_reg[9][0] " "theRegisters.\registers_reg[6][0] " ;
ScanIn "SI_4";
ScanOut "SO_4";
ScanMasterClock "clk_25mhz";
}
}
MacroDefs {
"scan_grp1" {
W tset_gen_tp1;
Shift { V { "scan_en" = 1; "_unwrapped_chain1_SI_1_" = #; "_unwrapped_chain1_SO_1_" = #; "_unwrapped_chain2_SI_2_" = #; "_unwrapped_chain2_SO_2_" = #; "_unwrapped_chain3_SI_3_" = #; "_unwrapped_chain3_SO_3_" = #; "_unwrapped_chain4_SI_4_" = #; "_unwrapped_chain4_SO_4_" = #; "clk_25mhz" = 1; } }
W tset_gen_tp1;
}
}
PatternBurst scanpats {
PatList { scan_test; }
}
PatternExec {
Timing STUCK_timing;
PatternBurst scanpats;
}
Pattern scan_test {
Ann {* Begin chain test *}
//Chain Pattern:0 Vector:0 TesterCycle:0
Ann {* Chain Pattern:0 Vector:0 TesterCycle:0 *}
"chain_pattern 0":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011;
"_unwrapped_chain1_SO_1_" = \r256 X;
"_unwrapped_chain2_SI_2_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011;
"_unwrapped_chain2_SO_2_" = \r256 X;
"_unwrapped_chain3_SI_3_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011;
"_unwrapped_chain3_SO_3_" = \r256 X;
"_unwrapped_chain4_SI_4_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011;
"_unwrapped_chain4_SO_4_" = \r256 X;
}
V {
_pi_=ZZZZZZN011111;
_po_=\r12 X;
}
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011;
"_unwrapped_chain1_SO_1_" = LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH;
"_unwrapped_chain2_SI_2_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011;
"_unwrapped_chain2_SO_2_" = LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH;
"_unwrapped_chain3_SI_3_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011;
"_unwrapped_chain3_SO_3_" = LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH;
"_unwrapped_chain4_SI_4_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011;
"_unwrapped_chain4_SO_4_" = LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH;
}
Ann {* End chain test *}
//Pattern:0 Vector:3 TesterCycle:513
Ann {* Pattern:0 Vector:3 TesterCycle:513 *}
"pattern 0":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 0011100000100001110010101100111011011010001011000111100111101111010010110111010011000010011101001110001000100011110110000100000111011011011101000100100001001111111101111111001111100111101000010001110010111011011100001010000000 \r24 1 001111;
"_unwrapped_chain1_SO_1_" = \r256 X;
"_unwrapped_chain2_SI_2_" = 1100100001001001011011110101011111011101010011011011110100011100010110100010111100111101011010101110111101001011100111101100111000101011000011010110110111001101001000111001100001110011110111011111010110001101001111010111101000101001001111110000110110001000;
"_unwrapped_chain2_SO_2_" = \r256 X;
"_unwrapped_chain3_SI_3_" = 0111011001010101010000101110010011010100000011011110001100110111011011101110000111011101101001111000011000010101101010110100100010100100101111110001010001011111000111001001110001100101100010010001011011011110000011101010100111111011111000011011111110001000;
"_unwrapped_chain3_SO_3_" = \r256 X;
"_unwrapped_chain4_SI_4_" = 11010110101111111011010001111011001001100101100110110110011001111010010100010100111000111110101101011100010 \r10 1 0001111000101111101100111011000111110111011101000110011111111010101000100111011100101000111010001011111000101100010011101000111000011100100;
"_unwrapped_chain4_SO_4_" = \r256 X;
}
V {
_pi_=0001110100011;
_po_=XXXXXXXXLHLH;
}
//Pattern:1 Vector:5 TesterCycle:770
Ann {* Pattern:1 Vector:5 TesterCycle:770 *}
"pattern 1":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 001001001000111101101111111001101001011010000111001010101011100101110101011110111111000101001001011110100001111010010011110101100111001100010101100100101101111101010011111011101000111110011000111010011010100011110100000100010 \r13 1 011111110110111111;
"_unwrapped_chain1_SO_1_" = \r256 L;
"_unwrapped_chain2_SI_2_" = 1100101010001101111001111100101010001101101010001010011000111111110010000100011010101011111101110111011100010110000010111000000111110010001010001010010001010100011001100001100111110101000101011101001111000101111111011101101110001000101011110101010110011001;
"_unwrapped_chain2_SO_2_" = \r256 L;
"_unwrapped_chain3_SI_3_" = 1010101010101100011100011101011110110000010001110110100000011110101100100111001101001100011110000010001100110001111110010001111001101110010111011111101110111110100101100110011001011101000100101111011111001011100100100010111010101100101000101010001001011011;
"_unwrapped_chain3_SO_3_" = \r256 L;
"_unwrapped_chain4_SI_4_" = 1100 \r11 1 00010111010110111000011111100111110101111000111000111110100010101111101100110001110110111111110111110100010101110000000111001110000101110001100111110111000111100110101110100111110010001011010111010010000001001111010001011000001010 \r11 1;
"_unwrapped_chain4_SO_4_" = \r256 L;
}
V {
_pi_=1010010101011;
_po_=XXXXXXXXLHHH;
}
//Pattern:2 Vector:7 TesterCycle:1027
Ann {* Pattern:2 Vector:7 TesterCycle:1027 *}
"pattern 2":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 11110001011011001111011010100111000110111000010000000010110010001111111101010110011111010101110011100001101011010111110010101000101011101110110011010100110000011010110011111001100111111010111011000110100110100110000011100100 \r30 1 01;
"_unwrapped_chain1_SO_1_" = \r256 L;
"_unwrapped_chain2_SI_2_" = 0010000010111001001111101101111010010000101101001111101100000101001101101101111100111110110011001101000111101111011010110111001010110011111010001111110111110010011000010111111001110000111111001111000101010100111101110101111011110011001011011101010011001011;
"_unwrapped_chain2_SO_2_" = \r256 L;
"_unwrapped_chain3_SI_3_" = 111110101011101001011101111001010101111011001111011110110011100100100111111011111010111101000101010 \r10 1 001100001010101101111011110100001111101100111100010000100011010111001101101100010011011111011010011111100100011010010110100001010011111101100011101;
"_unwrapped_chain3_SO_3_" = \r256 L;
"_unwrapped_chain4_SI_4_" = 0101010 \r10 1 0110001011001011111000011010001000010101111011111110011010011111111100111001111000101001000001111010010001011001110011111101101100101110111001111100011111110111111100100111011001100000101011110000001110 \r10 1 011011111110011111011110111;
"_unwrapped_chain4_SO_4_" = \r256 L;
}
V {
_pi_=1111100100111;
_po_=XXXXXXXXHLHL;
}
//Pattern:3 Vector:9 TesterCycle:1284
Ann {* Pattern:3 Vector:9 TesterCycle:1284 *}
"pattern 3":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 000110100001110111001010100001111111110100000101100100101111000001001010001000001111101101010110001011000111010010010011000111111111001100011110011101111100111011010011110100110001011111110101110100010000001100101010100111100 \r24 1 0011101;
"_unwrapped_chain1_SO_1_" = \r256 L;
"_unwrapped_chain2_SI_2_" = 1111010110010011010001110101010110011110001110101101011010011000011010011001001111110010011100010000001010011001110110101000101110010011000001011101110100110011001100101101100110110011001110000111000100011110011100100001110001011111111011001101010001100010;
"_unwrapped_chain2_SO_2_" = \r256 L;
"_unwrapped_chain3_SI_3_" = 1101111110110001011010111111110000111010100010110111011011101000111011010010000111011110110111011110000010011101100110110111100100000110111010101100110111001100010110100100101001010111110001010001011110011111110000110011100010111010011011000101011010111000;
"_unwrapped_chain3_SO_3_" = \r256 L;
"_unwrapped_chain4_SI_4_" = 0111100011110101011111101000110100001111010111100101111100010010001111111110001011101110000110101100010010111110011111110110110110010101010101110100101011001011101001010001100001101110000100111110000011111001100100111011010101111011100110001011101011100000;
"_unwrapped_chain4_SO_4_" = \r256 L;
}
V {
_pi_=0101010101001;
_po_=XXXXXXXXLHHL;
}
//Pattern:4 Vector:11 TesterCycle:1541
Ann {* Pattern:4 Vector:11 TesterCycle:1541 *}
"pattern 4":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 00100110101101100000001000011011001001111111011100111110110001011111001110011101111101001100111101111000111111001011010101011011011000101010 \r12 1 011110110000100001001111110000111011111000010110010101101011110111100111110 \r26 1 011;
"_unwrapped_chain1_SO_1_" = \r256 L;
"_unwrapped_chain2_SI_2_" = 00000110001001001001100011011000000010100101101110001100110011111111010001010101010 \r11 1 001100110101100010100110111100010110101111101111110101101101101110111001111001101101100001011011101111000010101011000101101111001110001001001111010101000011111111;
"_unwrapped_chain2_SO_2_" = \r256 L;
"_unwrapped_chain3_SI_3_" = 1101101000010010111111000111110110110011110011011011101111110011001011100000101001111111001000111111101111100111000001110100111101101110010001010111001110111111101101101010101101101100101011111101110111001011101111110111111100101111011010001100111011110001;
"_unwrapped_chain3_SO_3_" = \r256 L;
"_unwrapped_chain4_SI_4_" = 1111110000010010110100001111101111010110110101010110101111001010101111011111110111110110110101111110000011111001000000111010100111111101100111010000001001110011100111110101101111000001011101110001101111010001110101101111100110100100000011111010000111111001;
"_unwrapped_chain4_SO_4_" = \r256 L;
}
V {
_pi_=0000000101111;
_po_=XXXXXXXXLLHH;
}
//Pattern:5 Vector:13 TesterCycle:1798
Ann {* Pattern:5 Vector:13 TesterCycle:1798 *}
"pattern 5":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 110001100001111000111101111001101011010110010001110101111100000111110010101110101000011011101011100011010001011111010000100000001101111110000100101101001111111001011010111111110101011111100100000000100101001110101001110111000 \r21 1 0010001011;
"_unwrapped_chain1_SO_1_" = \r256 L;
"_unwrapped_chain2_SI_2_" = 0001000000100000000010101110000010111101100100001101011000001011111001010100111101110111111001111101000101101100011101001011110101000010100111000110010000110010111110101101010111010111001110101101111010001101010111110111010010000101001011111000110111001111;
"_unwrapped_chain2_SO_2_" = \r256 L;
"_unwrapped_chain3_SI_3_" = 10100101001110001110100001101100101110001101000110100000101000110011010101101000010001 \r11 0 111100100100101001101001010111001000101111111010111000100111001011111101110011001001110111011010101010110111110001111100010111000011001100100010111011000111011;
"_unwrapped_chain3_SO_3_" = \r256 L;
"_unwrapped_chain4_SI_4_" = 1111000111111110011110110010010111000001111001110001111001110011011000111000110010000111010010101010010101110101011010100111010110100011000001111101111111101000101011011010010110101001100000111001101111110111101000111100000000100000111110110101001011101100;
"_unwrapped_chain4_SO_4_" = \r256 L;
}
V {
_pi_=1010100100101;
_po_=XXXXXXXXHLHH;
}
//Pattern:6 Vector:15 TesterCycle:2055
Ann {* Pattern:6 Vector:15 TesterCycle:2055 *}
"pattern 6":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 11011011100110011001010101110000101010010101100111010101101011100010100110011101010100101111011011001100100011001001111111110110101100110111110111101100100011111000010101101010110 \r10 1 00001100110111011001001100010101111010 \r15 1 01110110111001;
"_unwrapped_chain1_SO_1_" = \r256 L;
"_unwrapped_chain2_SI_2_" = 1100011010011001011101011001000100111101110000100101010110110100010101101101011010001110011101011110100000000101111111101011101001000110111000000010000010101011101110101011111100110111011101100011110001100101110111001101111011011110101011110001010110111010;
"_unwrapped_chain2_SO_2_" = \r256 L;
"_unwrapped_chain3_SI_3_" = 0100000100011010110000101000011110011110001010010100000111011000111011100011011110100010001010111101111010101011011101101110100100011100111111011101101100001100100101110101101101001110111001101101110010111111100010000110111101011001110110101100011110000010;
"_unwrapped_chain3_SO_3_" = \r256 L;
"_unwrapped_chain4_SI_4_" = 1101010001001110110000000001100101111101000100001111101100010111111010110101100111100100001100110100100101101110111001011110110011101101101101010000011101011011101010010110000111111011000001110000100001000011010001111001001101101001111101111100011011111111;
"_unwrapped_chain4_SO_4_" = \r256 L;
}
V {
_pi_=1111110101000;
_po_=XXXXXXXXHHLH;
}
//Pattern:7 Vector:17 TesterCycle:2312
Ann {* Pattern:7 Vector:17 TesterCycle:2312 *}
"pattern 7":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 01010110010101000100010101110011101110110001110110010100100110001100111100001011101100010101000001001100100010011011000100101111100000100000110101010000100110110010111001100001001011111011000001011100100000110010000001010100110 \r18 1 01110101101;
"_unwrapped_chain1_SO_1_" = \r256 L;
"_unwrapped_chain2_SI_2_" = 10111101111001011000101001101100 \r11 1 011110111110001111011101011110111101011110011110110001111000010111001001001111101100110000100010111110000000011100011001000101001011001100111000000001101010001100011100000010000100111101011011111110001101101000001;
"_unwrapped_chain2_SO_2_" = \r256 L;
"_unwrapped_chain3_SI_3_" = 1011010100001111111110001111010000110101000101011011000001101011011101110001000001110011000111100100110111101111010101011100111010111010011011000111011001010110110000101000011111001110100011010101010011011111010110111100111011111011111110110101111001101110;
"_unwrapped_chain3_SO_3_" = \r256 L;
"_unwrapped_chain4_SI_4_" = 1110111011000110000111011000010100100111011000110001101100000100111011110011001001011111100010111011011101110011100001100110000001001011110111000110111100001110101110110010001110001010110001111100111111001101001011011011100111111111001100010000110111010000;
"_unwrapped_chain4_SO_4_" = \r256 L;
}
V {
_pi_=0101010100110;
_po_=XXXXXXXXLHHH;
}
//Pattern:8 Vector:19 TesterCycle:2569
Ann {* Pattern:8 Vector:19 TesterCycle:2569 *}
"pattern 8":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 101101101111110000111000001110110110001010010111111001101110011111111011011101011110101011111111101101010001100110010011001010011010111110011101010110100011110000101111011100011010001110000001011110111110000001110101011110010 \r22 1 011011101;
"_unwrapped_chain1_SO_1_" = \r256 L;
"_unwrapped_chain2_SI_2_" = 0101010011110010101001110111100101110110011011001110001011011001111110101111111001101010111001101110100111011101100100011010000100110111101101111101111001010010011101001101000001100110011010010001110101011010001100101100010000101001001011100110110111111101;
"_unwrapped_chain2_SO_2_" = \r256 L;
"_unwrapped_chain3_SI_3_" = 0000001111010000010011101001111101010001110110010110110111111100001011101010110111011111001011011101011011101001100011101100100001100011011100001110000110101001010011010010001101011110101100001011111010000110000111001011101101100000011111101101011011111100;
"_unwrapped_chain3_SO_3_" = \r256 L;
"_unwrapped_chain4_SI_4_" = 0101101011010001110111100000000110011111111100101011111000100100001111111010001011010101110000101110001001101011010110001111011010111101101101100110111000001000101101101010101111101000100000111110001011111111001100101110000100111110000010001100110111001111;
"_unwrapped_chain4_SO_4_" = \r256 L;
}
V {
_pi_=0000000100001;
_po_=XXXXXXXXHLLL;
}
//Pattern:9 Vector:21 TesterCycle:2826
Ann {* Pattern:9 Vector:21 TesterCycle:2826 *}
"pattern 9":
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 101110010101010111111101010010011110000110001100111000001010111100011 \r10 0 1001100011110011111001110001011101111010011010111011100101010011010110000101100001001001011011111100011111010001101000111101111101011000001110000100 \r24 1 01011;
"_unwrapped_chain1_SO_1_" = \r256 L;
"_unwrapped_chain2_SI_2_" = 1110111110101110100011101010001101111100010101101101101001111110100011111010001101011011010001010001111010000000111001110110001011010001011001100100101011110001101110000001111010111011011000101101111100011011100100011101000100100011111111010101100011111011;
"_unwrapped_chain2_SO_2_" = \r256 L;
"_unwrapped_chain3_SI_3_" = 1011011100100101011000100100011100110100001001010111110111001010011010011101001011100110111010111010010001010101000111101011100011001000000100010101010111111001111101000000110011001110010110011001110010110101001111000111111101010000010001111100001001001010;
"_unwrapped_chain3_SO_3_" = \r256 L;
"_unwrapped_chain4_SI_4_" = 1101111101100100110011010011111100111000101011101000001101101011111010111001010001110000101111011011111101101011101010100000000110111011011111001010011101111110100001111011000001100111110111110000100111111101110010101010101010110000001001110101001111011101;
"_unwrapped_chain4_SO_4_" = \r256 L;
}
V {
_pi_=1010100101010;
_po_=XXXXXXXXHHHH;
}
Macro "scan_grp1" {
"_unwrapped_chain1_SI_1_" = 101110010101010111111101010010011110000110001100111000001010111100011 \r10 0 1001100011110011111001110001011101111010011010111011100101010011010110000101100001001001011011111100011111010001101000111101111101011000001110000100 \r24 1 01011;
"_unwrapped_chain1_SO_1_" = \r256 L;
"_unwrapped_chain2_SI_2_" = 1110111110101110100011101010001101111100010101101101101001111110100011111010001101011011010001010001111010000000111001110110001011010001011001100100101011110001101110000001111010111011011000101101111100011011100100011101000100100011111111010101100011111011;
"_unwrapped_chain2_SO_2_" = \r256 L;
"_unwrapped_chain3_SI_3_" = 1011011100100101011000100100011100110100001001010111110111001010011010011101001011100110111010111010010001010101000111101011100011001000000100010101010111111001111101000000110011001110010110011001110010110101001111000111111101010000010001111100001001001010;
"_unwrapped_chain3_SO_3_" = \r256 L;
"_unwrapped_chain4_SI_4_" = 1101111101100100110011010011111100111000101011101000001101101011111010111001010001110000101111011011111101101011101010100000000110111011011111001010011101111110100001111011000001100111110111110000100111111101110010101010101010110000001001110101001111011101;
"_unwrapped_chain4_SO_4_" = \r256 L;
}
Ann {* Total count Patterns:10 Vectors:24 TesterCycles:3339 *}
}

1098
cpu_patterns_serial.v Normal file
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3729
cpu_patterns_serial.v.0.vec Normal file
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1
cpu_patterns_serial.v.cfg Normal file
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cpu_patterns_serial.v.0.vec 3352 11

22
cpu_patterns_serial.v.info.dict Normal file
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#
# Information Dictionary File produced by Tessent Shell 2023.4-p1
# Date : Thu May 28 18:01:24 2026
#
# <view> : (interface) | scan_graybox | full | ijtag_graybox
# <language_version> : (verilog_2001) | verilog_sv31a
set pattern_info_dict {
version 1
pattern_type scan
ssn off
current_mode unwrapped
simulation_design_view {
testbench_language verilog_2001
testbench_name cpu_cpu_patterns_serial_v_ctl
dut_inst cpu_inst
current_design_block {
module_name cpu
view full
}
}
}

12
cpu_patterns_serial.v.po.name Normal file
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6c65645b375d
6c65645b365d
6c65645b355d
6c65645b345d
6c65645b335d
6c65645b325d
6c65645b315d
6c65645b305d
0000534f5f31
0000534f5f32
0000534f5f33
0000534f5f34

BIN
demo_chip_rtl/demo_chip.odb Normal file
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85
demo_chip_rtl/rtl/demo_chip/cpu_sys.v Executable file
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//
// Wrapper for CPU + memory
module cpu_sys (
input clock,
input reset,
input [4:0] Interrupts, // 5 general-purpose hardware interrupts
input NMI, // Non-maskable interrupt
// Data Memory Interface
input [31:0] per_dout, //
output DataMem_Read,
output [3:0] DataMem_Write, // 4-bit Write, one for each byte in word.
output [29:0] DataMem_Address, // Addresses are words, not bytes.
output [31:0] DataMem_Out
);
// Instruction Memory Interface
wire [31:0] pmem_dout;
wire [29:0] pmem_addr; // Addresses are words, not bytes.
wire pmem_cen;
wire dmem_cen;
wire [31:0] dmem_dout; // Data Memory data output
wire [31:0] DataMem_In;
// ---------------------------------
// MIPS processor
// ---------------------------------
Processor MIPS_CPU (
.clock(clock),
.reset(reset),
.Interrupts(Interrupts), // 5 general-purpose hardware interrupts
.NMI(NMI), // Non-maskable interrupt
// Data Memory Interface
.DataMem_In(DataMem_In),
.DataMem_Ready(1'b1),
.DataMem_Read(),
.DataMem_Write(DataMem_Write), // 4-bit Write, one for each byte in word.
.DataMem_Address(DataMem_Address), // Addresses are words, not bytes.
.DataMem_Out(DataMem_Out),
// Instruction Memory Interface
.InstMem_In(pmem_dout),
.InstMem_Address(pmem_addr), // Addresses are words, not bytes.
.InstMem_Ready(1'b1),
.InstMem_Read(pmem_cen),
.IP() // Pending interrupts (diagnostic)
);
// ---------------------------------
// Program Memory RAM //
// ---------------------------------
MemGen_32_12 program_memory (
.chip_en(pmem_cen),
.clock(clock),
.addr(pmem_addr[11:0]),
.rd_data(pmem_dout),
.rd_en(pmem_cen),
.wr_data(32'h00000000),
.wr_en(1'b0)
);
// ---------------------------------
// Program Memory RAM //
// ---------------------------------
assign DataMem_In = DataMem_Address[29] ? per_dout : dmem_dout;
assign dmem_cen = !DataMem_Address[29];
MemGen_32_12 data_memory (
.chip_en(dmem_cen),
.clock(clock),
.addr(DataMem_Address[11:0]),
.rd_data(dmem_dout),
.rd_en(DataMem_Read),
.wr_data(DataMem_Out),
.wr_en(DataMem_Write[0])
);
endmodule

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demo_chip_rtl/rtl/demo_chip/demo_chip.v Executable file
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////////////////////////////////////////////////////////////////////
// Design : demo_chip
// Author(s) :
// Creation date : August 9,2013
// Copyright (C) ...
////////////////////////////////////////////////////////////////////
// Description: demo_chip instantiates the following modules:
// 1 MIPS 32r1 CPU
// 2 nova decoder wrapper
// 3 4 * HPDMC DDR controllers
// 4 USB controller + PHY
//
////////////////////////////////////////////////////////////////////
module demo_chip(
output mclk, // Main system clock (used by external memories)
input reset_n,
//
// First H264 Decoder Pins
//
input [15:0] BS_data_0,
output BS_ren_0,
output [16:0] BS_addr_0,
//
// Second H264 Decoder Pins
//
input [15:0] BS_data_1,
output BS_ren_1,
output [16:0] BS_addr_1,
//
// Microcontroller pins
//
input lfxt_clk, // Low frequency reference (typ 10MHz)
input nmi, // Non-maskable interrupt (asynchronous and non-glitchy)
// DDR0
output ddr0_cke,
output ddr0_cs_n,
output ddr0_we_n,
output ddr0_cas_n,
output ddr0_ras_n,
output [12:0] ddr0_adr,
output [1:0] ddr0_ba,
output [3:0] ddr0_dm,
inout [31:0] ddr0_dq,
inout [3:0] ddr0_dqs,
// DDR1
output ddr1_cke,
output ddr1_cs_n,
output ddr1_we_n,
output ddr1_cas_n,
output ddr1_ras_n,
output [12:0] ddr1_adr,
output [1:0] ddr1_ba,
output [3:0] ddr1_dm,
inout [31:0] ddr1_dq,
inout [3:0] ddr1_dqs,
// DDR2
output ddr2_cke,
output ddr2_cs_n,
output ddr2_we_n,
output ddr2_cas_n,
output ddr2_ras_n,
output [12:0] ddr2_adr,
output [1:0] ddr2_ba,
output [3:0] ddr2_dm,
inout [31:0] ddr2_dq,
inout [3:0] ddr2_dqs,
// DDR3
output ddr3_cke,
output ddr3_cs_n,
output ddr3_we_n,
output ddr3_cas_n,
output ddr3_ras_n,
output [12:0] ddr3_adr,
output [1:0] ddr3_ba,
output [3:0] ddr3_dm,
inout [31:0] ddr3_dq,
inout [3:0] ddr3_dqs,
// USB
inout usb_plus, usb_minus,
//
input scan_mode,
input sysclk_byp,
input usbclk_byp
);
// Internal chip side pad connections
wire lfxt_clk_i; // Main system clock (used by external memories)
wire reset_n_i;
wire nmi_i; // Non-maskable interrupt (asynchronous and non-glitchy)
wire mclk_i; // Main system clock (used by external memories)
wire scan_mode_i;
wire sysclk_byp_i;
wire usbclk_byp_i;
// DDR
wire ddr0_cke_i, ddr0_cs_n_i, ddr0_we_n_i, ddr0_cas_n_i, ddr0_ras_n_i,
ddr1_cke_i, ddr1_cs_n_i, ddr1_we_n_i, ddr1_cas_n_i, ddr1_ras_n_i,
ddr2_cke_i, ddr2_cs_n_i, ddr2_we_n_i, ddr2_cas_n_i, ddr2_ras_n_i,
ddr3_cke_i, ddr3_cs_n_i, ddr3_we_n_i, ddr3_cas_n_i, ddr3_ras_n_i;
wire [12:0] ddr0_adr_i, ddr1_adr_i, ddr2_adr_i, ddr3_adr_i;
wire [1:0] ddr0_ba_i, ddr1_ba_i, ddr2_ba_i, ddr3_ba_i;
wire [3:0] ddr0_dm_i, ddr1_dm_i, ddr2_dm_i, ddr3_dm_i;
wire [15:0] BitStream_buffer_input_0_i;
wire BitStream_ram_ren_0_i;
wire [16:0] BitStream_ram_addr_0_i;
wire [15:0] BitStream_buffer_input_1_i;
wire BitStream_ram_ren_1_i;
wire [16:0] BitStream_ram_addr_1_i;
// wire [15:0] BS_data_0; //added by sudhish for missing declarations on pads
// wire [15:0] BS_data_1;
wire [31:0] dmem_din; // Data Memory data input
wire [29:0] dmem_addr; // Data Memory address
wire [3:0] dmem_wen; // Data Memory write enable (low active)
wire dmem_cen; // Data Memory write enable (low active)
wire [31:0] power_control; // Power switch powerdwon control
wire [31:0] power_iso; // Power switch isolation control
wire [31:0] power_ack; // Power switch acknowledge
wire power_control_0;
wire power_ack_0;
// QSG wire power_ack_2;
// QSG wire power_control_2;
wire smclk;
wire pll_clk, pll_clk_o;
wire aclk;
wire dco_clk;
reg enable_nova0, enable_nova1;
wire mclk_nova0, mclk_nova1;
wire ext_frame_RAM0_cs_n;
wire ext_frame_RAM0_wr;
wire [13:0] ext_frame_RAM0_addr;
wire [31:0] ext_frame_RAM0_data;
wire [63:0] fml_do_ddr0;
wire ext_frame_RAM1_cs_n;
wire ext_frame_RAM1_wr;
wire [13:0] ext_frame_RAM1_addr;
wire [31:0] ext_frame_RAM1_data;
wire [63:0] fml_do_ddr1;
wire [31:0] dis_frame_RAM_din_0;
wire ext_frame_RAM2_cs_n;
wire ext_frame_RAM2_wr;
wire [13:0] ext_frame_RAM2_addr;
wire [31:0] ext_frame_RAM2_data;
wire [63:0] fml_do_ddr2;
wire ext_frame_RAM3_cs_n;
wire ext_frame_RAM3_wr;
wire [13:0] ext_frame_RAM3_addr;
wire [31:0] ext_frame_RAM3_data;
wire [63:0] fml_do_ddr3;
wire [31:0] dis_frame_RAM_din_1;
// USB
wire usb_clk, usb_clk_o;
wire usb_txdp, usb_txdn, usb_txoe;
wire usb_rxd, usb_rxdp, usb_rxdn;
wire [7:0] usb_DataOut;
wire usb_TxValid;
wire usb_TxReady;
wire [7:0] usb_DataIn;
wire usb_RxValid;
wire usb_RxActive;
wire usb_RxError;
wire [1:0] usb_LineState;
wire usb_inta, usb_intb;
wire [4:0] Interrupts; // 5 general-purpose hardware interrupts
// Define clocks - all from PLL
assign smclk = pll_clk;
assign mclk_i = pll_clk;
assign mclk_n = !pll_clk;
assign dqs_clk = pll_clk;
assign dqs_clk_n = !pll_clk;
assign aclk = pll_clk;
assign mclk_i = pll_clk;
assign dco_clk = pll_clk;
// ---------------------------------
// External pads (non-DDR)
// ---------------------------------
PADBID lfxt_clk_pad ( .I(1'b0), .OEN(1'b1), .PAD(lfxt_clk), .C(lfxt_clk_i) );
PADBID reset_n_pad ( .I(1'b0), .OEN(1'b1), .PAD(reset_n), .C(reset_n_i) );
PADBID nmi_pad ( .I(1'b0), .OEN(1'b1), .PAD(nmi), .C(nmi_i) );
PADBID mclk_pad ( .I(mclk_i), .OEN(1'b0), .PAD(mclk), .C() );
PADBID BS_ren_0_pad ( .I(BitStream_ram_ren_0_i), .OEN(1'b0), .PAD(BS_ren_0), .C() );
PADBID BS_ren_1_pad ( .I(BitStream_ram_ren_1_i), .OEN(1'b0), .PAD(BS_ren_1), .C() );
PADBID scan_mode_pad ( .I(1'b0), .OEN(1'b1), .PAD(scan_mode), .C(scan_mode_i) );
// PADBID sysclk_byp_pad ( .I(1'b0), .OEN(1'b1), .PAD(sysclk_byp), .C(sysclk_byp_i) );
//PADBID usbclk_byp_pad ( .I(1'b0), .OEN(1'b1), .PAD(usbclk_byp), .C(usbclk_byp_i) );
PADCLK sysclk_byp_pad ( .PAD(sysclk_byp), .C(sysclk_byp_i) );
PADCLK usbclk_byp_pad ( .PAD(usbclk_byp), .C(usbclk_byp_i) );
genvar i, ddr;
// Data buses
generate
for (i = 0; i <= 15; i = i + 1) begin
PADBID BS_data_0_pad ( .I(1'b0), .OEN(1'b1), .PAD(BS_data_0[i]), .C(BitStream_buffer_input_0_i[i]) );
PADBID BS_data_1_pad ( .I(1'b0), .OEN(1'b1), .PAD(BS_data_1[i]), .C(BitStream_buffer_input_1_i[i]) );
end
endgenerate
// Address buses
generate
for (i = 0; i <= 16; i = i + 1) begin
PADBID BS_addr_0_pad ( .I(BitStream_ram_addr_0_i[i]), .OEN(1'b0), .PAD(BS_addr_0[i]), .C() );
PADBID BS_addr_1_pad ( .I(BitStream_ram_addr_1_i[i]), .OEN(1'b0), .PAD(BS_addr_1[i]), .C() );
end
endgenerate
PADBID i_usb_pad_plus ( .I(usb_txdp), .OEN(usb_txoe), .PAD(usb_plus), .C(usb_rxdp) );
PADBID i_usb_pad_minus ( .I(usb_txdn), .OEN(usb_txoe), .PAD(usb_minus), .C(usb_rxdn) );
assign usb_rxd = usb_rxdp && usb_rxdn;
// ---------------------------------
// DDR output pads (data pads are in the PHY module
// ---------------------------------
PADBID ddr0_cke_pad ( .I(ddr0_cke_i), .OEN(1'b0), .PAD(ddr0_cke), .C() );
PADBID ddr0_cs_n_pad ( .I(ddr0_cs_n_i), .OEN(1'b0), .PAD(ddr0_cs_n), .C() );
PADBID ddr0_we_n_pad ( .I(ddr0_we_n_i), .OEN(1'b0), .PAD(ddr0_we_n), .C() );
PADBID ddr0_cas_n_pad ( .I(ddr0_cas_n_i), .OEN(1'b0), .PAD(ddr0_cas_n), .C() );
PADBID ddr0_ras_n_pad ( .I(ddr0_ras_n_i), .OEN(1'b0), .PAD(ddr0_ras_n), .C() );
PADBID ddr1_cke_pad ( .I(ddr1_cke_i), .OEN(1'b0), .PAD(ddr1_cke), .C() );
PADBID ddr1_cs_n_pad ( .I(ddr1_cs_n_i), .OEN(1'b0), .PAD(ddr1_cs_n), .C() );
PADBID ddr1_we_n_pad ( .I(ddr1_we_n_i), .OEN(1'b0), .PAD(ddr1_we_n), .C() );
PADBID ddr1_cas_n_pad ( .I(ddr1_cas_n_i), .OEN(1'b0), .PAD(ddr1_cas_n), .C() );
PADBID ddr1_ras_n_pad ( .I(ddr1_ras_n_i), .OEN(1'b0), .PAD(ddr1_ras_n), .C() );
PADBID ddr2_cke_pad ( .I(ddr2_cke_i), .OEN(1'b0), .PAD(ddr2_cke), .C() );
PADBID ddr2_cs_n_pad ( .I(ddr2_cs_n_i), .OEN(1'b0), .PAD(ddr2_cs_n), .C() );
PADBID ddr2_we_n_pad ( .I(ddr2_we_n_i), .OEN(1'b0), .PAD(ddr2_we_n), .C() );
PADBID ddr2_cas_n_pad ( .I(ddr2_cas_n_i), .OEN(1'b0), .PAD(ddr2_cas_n), .C() );
PADBID ddr2_ras_n_pad ( .I(ddr2_ras_n_i), .OEN(1'b0), .PAD(ddr2_ras_n), .C() );
PADBID ddr3_cke_pad ( .I(ddr3_cke_i), .OEN(1'b0), .PAD(ddr3_cke), .C() );
PADBID ddr3_cs_n_pad ( .I(ddr3_cs_n_i), .OEN(1'b0), .PAD(ddr3_cs_n), .C() );
PADBID ddr3_we_n_pad ( .I(ddr3_we_n_i), .OEN(1'b0), .PAD(ddr3_we_n), .C() );
PADBID ddr3_cas_n_pad ( .I(ddr3_cas_n_i), .OEN(1'b0), .PAD(ddr3_cas_n), .C() );
PADBID ddr3_ras_n_pad ( .I(ddr3_ras_n_i), .OEN(1'b0), .PAD(ddr3_ras_n), .C() );
generate
for (i = 0; i <= 12; i = i + 1) begin
PADBID ddr0_adr_pad ( .I(ddr0_adr_i[i]), .OEN(1'b0), .PAD(ddr0_adr[i]), .C() );
PADBID ddr1_adr_pad ( .I(ddr1_adr_i[i]), .OEN(1'b0), .PAD(ddr1_adr[i]), .C() );
PADBID ddr2_adr_pad ( .I(ddr2_adr_i[i]), .OEN(1'b0), .PAD(ddr2_adr[i]), .C() );
PADBID ddr3_adr_pad ( .I(ddr3_adr_i[i]), .OEN(1'b0), .PAD(ddr3_adr[i]), .C() );
end
endgenerate
generate
for (i = 0; i <= 1; i = i + 1) begin
PADBID ddr0_ba_pad ( .I(ddr0_ba_i[i]), .OEN(1'b0), .PAD(ddr0_ba[i]), .C() );
PADBID ddr1_ba_pad ( .I(ddr1_ba_i[i]), .OEN(1'b0), .PAD(ddr1_ba[i]), .C() );
PADBID ddr2_ba_pad ( .I(ddr2_ba_i[i]), .OEN(1'b0), .PAD(ddr2_ba[i]), .C() );
PADBID ddr3_ba_pad ( .I(ddr3_ba_i[i]), .OEN(1'b0), .PAD(ddr3_ba[i]), .C() );
end
endgenerate
generate
for (i = 0; i <= 3; i = i + 1) begin
PADBID ddr0_dm_pad ( .I(ddr0_dm_i[i]), .OEN(1'b0), .PAD(ddr0_dm[i]), .C() );
PADBID ddr1_dm_pad ( .I(ddr1_dm_i[i]), .OEN(1'b0), .PAD(ddr1_dm[i]), .C() );
PADBID ddr2_dm_pad ( .I(ddr2_dm_i[i]), .OEN(1'b0), .PAD(ddr2_dm[i]), .C() );
PADBID ddr3_dm_pad ( .I(ddr3_dm_i[i]), .OEN(1'b0), .PAD(ddr3_dm[i]), .C() );
end
endgenerate
// ---------------------------------
// Peripheral Interface bus
// ---------------------------------
wire [15:0] per_dout; // Register data output to microcontroller
wire [15:0] per_dout_nova0; // Register data output from nova0
wire [15:0] per_dout_nova1; // Register data output from nova1
wire [31:0] per_dout_ddr0; // Register data output from ddr0
wire [31:0] per_dout_ddr1; // Register data output from ddr0
wire [31:0] per_dout_ddr2; // Register data output from ddr0
wire [31:0] per_dout_ddr3; // Register data output from ddr0
wire [31:0] per_dout_usb; // Register data output from USB
wire [31:0] per_dout_pctl; // Register data output from USB
wire [13:0] per_addr; // Register address
wire [31:0] per_din; // Register data input
wire [1:0] per_we; // Register write enable (high active)
wire per_en; // Register enable (high active)
wire per_rd; // Register read
assign per_din = dmem_din;
assign per_dout = {15'h0000,per_dout_nova0} ||
{15'h0000,per_dout_nova1[15:0]} ||
per_dout_ddr0 ||
per_dout_ddr1 ||
per_dout_ddr2 ||
per_dout_ddr3 ||
per_dout_usb ||
per_dout_pctl ||
32'h00000000;
assign per_en = dmem_addr[29];
assign per_we[0] = dmem_addr[29] && dmem_wen[0];
assign per_we[1] = dmem_addr[29] && dmem_wen[1];
assign per_rd = per_en && !per_we[0];
assign per_addr = dmem_addr[13:0];
//assign DataMem_In = dmem_addr[29] ? per_dout : dmem_dout;
wire NMI; // Non-maskable interrupt
wire DataMem_Ready;
wire DataMem_Read;
wire [3:0] DataMem_Write; // 4-bit Write; one for each byte in word.
wire [29:0] DataMem_Address; // Addresses are words; not bytes.
wire [31:0] DataMem_Out;
// Instruction Memory Interface
wire [31:0] InstMem_In;
wire [29:0] InstMem_Address; // Addresses are words; not bytes.
wire InstMem_Ready;
wire InstMem_Read;
wire [7:0] IP; // Pending interrupts (diagnostic)
assign Interrupts = { 3'b0, usb_inta, usb_intb } ;
// ---------------------------------
// MIPS CPU
// ---------------------------------
cpu_sys i_cpu_sys (
.clock(smclk),
.reset(reset_n_i),
.Interrupts(Interrupts), // 5 general-purpose hardware interrupts
.NMI(nmi_i), // Non-maskable interrupt
// Data Memory Interface
.per_dout(per_dout),
.DataMem_Read(dmem_rd),
.DataMem_Write(dmem_wen), // 4-bit Write, one for each byte in word.
.DataMem_Address(dmem_addr), // Addresses are words, not bytes.
.DataMem_Out(dmem_din)
);
// ---------------------------------
// Powerdown register
// ---------------------------------
// Tie off pre-layout - will connect to power switches
// assign power_ack = 32'hffff_ffff;
powerdown_control powerdown_control (
.clk(mclk_i),
.reset_n(reset_n_i),
.per_addr(per_addr),
.per_din(per_din),
.per_en(per_en),
.per_we(per_we[0]),
.per_rd(per_rd),
.per_dout(per_dout_pctl),
.power_control(power_control),
.power_ack(power_ack),
.power_iso(power_iso)
);
//dummy_connector dummy_connector (.power_control(power_control), .power_iso(power_iso), .power_ack(power_ack) );
// NOVA 0 clock gate
always @(negedge mclk_i ) enable_nova0 <= power_iso[0];
AND2_X1_HVT i_nova0_cg (.A1(mclk_i), .A2(enable_nova0), .ZN(mclk_nova0) );
///////////////////
// NOVA decoders //
///////////////////
nova_wrapper nova0 (
.clk(mclk_nova0),
.clk_reg(smclk),
.reset_n(reset_n_i),
.per_dout(per_dout_nova0),
.per_addr(per_addr),
.per_din(per_din[15:0]),
.per_en(per_en),
.per_we(per_we),
.BitStream_buffer_input(BitStream_buffer_input_0_i),
.BitStream_ram_ren(BitStream_ram_ren_0_i),
.BitStream_ram_addr(BitStream_ram_addr_0_i),
.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
.ext_frame_RAM0_data(ext_frame_RAM0_data),
.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
.ext_frame_RAM1_data(ext_frame_RAM1_data),
.dis_frame_RAM_din(dis_frame_RAM_din_0),
.power_ack(power_ack_0),
.power_control(power_control_0)
);
// DDR port 0
// Dummy register to create control signal
reg [7:0] fml_sel_ddr0;
always @ (posedge mclk_nova0 )
begin
if ( ext_frame_RAM0_cs_n == 1'b0 )
if ( ext_frame_RAM0_wr )
fml_sel_ddr0 <= dis_frame_RAM_din_0[7:0];
else
fml_sel_ddr0 <= dis_frame_RAM_din_0[15:8];
end
// Create to get a 2 bit pll_stat for DDR
wire sys_pll_lock;
reg sys_pll_lock_sync;
always @ (posedge pll_clk_o ) sys_pll_lock_sync <= sys_pll_lock;
// Dummy register to expand DDR bus to 64 bits
reg [31:0] nova0_data_extend;
wire [63:0]nova0_fml_di;
always @ (posedge mclk_nova0 ) nova0_data_extend <= dis_frame_RAM_din_0;
assign nova0_fml_di = { nova0_data_extend, dis_frame_RAM_din_0 };
assign ext_frame_RAM0_data = ext_frame_RAM0_addr[13] ? fml_do_ddr0 [63:32] : fml_do_ddr0 [31:0] ;
hpdmc #(
.csr_addr(4'h0),
.sdram_depth(14),
.sdram_columndepth(9)
) nova0_ddr0 (
.sys_clk(mclk_nova0),
.sys_clk_n(!mclk_nova0),
.dqs_clk(mclk_nova0),
.dqs_clk_n(!mclk_nova0),
.sys_rst(!reset_n_i),
/* Control interface */
.csr_a(per_addr),
.csr_we(per_we[0]),
.csr_di(per_din),
.csr_do(per_dout_ddr0),
/* Simple FML 4x64 interface to the memory contents */
.fml_adr(ext_frame_RAM0_addr),
.fml_stb(ext_frame_RAM0_cs_n),
.fml_we(ext_frame_RAM0_wr),
.fml_ack(),
.fml_sel(fml_sel_ddr0),
.fml_di(nova0_fml_di),
.fml_do(fml_do_ddr0),
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
.sdram_cke(ddr0_cke_i),
.sdram_cs_n(ddr0_cs_n_i),
.sdram_we_n(ddr0_we_n_i),
.sdram_cas_n(ddr0_cas_n_i),
.sdram_ras_n(ddr0_ras_n_i),
.sdram_adr(ddr0_adr_i),
.sdram_ba(ddr0_ba_i),
.sdram_dm(ddr0_dm_i),
.sdram_dq(ddr0_dq),
.sdram_dqs(ddr0_dqs),
/* Interface to the DCM generating DQS */
.dqs_psen(),
.dqs_psincdec(),
.dqs_psdone(1'b0),
.pll_stat({sys_pll_lock,sys_pll_lock_sync})
);
// DDR port 1
// Dummy register to create control signal
reg [7:0] fml_sel_ddr1;
always @ (posedge mclk_nova0 )
begin
if ( ext_frame_RAM1_cs_n == 1'b0 )
if ( ext_frame_RAM1_wr )
fml_sel_ddr1 <= dis_frame_RAM_din_0[23:16];
else
fml_sel_ddr1 <= dis_frame_RAM_din_0[31:24];
end
assign ext_frame_RAM1_data = ext_frame_RAM1_addr[13] ? fml_do_ddr1 [63:32] : fml_do_ddr1 [31:0] ;
hpdmc #(
.csr_addr(4'h1),
.sdram_depth(14),
.sdram_columndepth(9)
) nova0_ddr1 (
.sys_clk(mclk_nova0),
.sys_clk_n(!mclk_nova0),
.dqs_clk(mclk_nova0),
.dqs_clk_n(!mclk_nova0),
.sys_rst(!reset_n_i),
/* Control interface */
.csr_a(per_addr),
.csr_we(per_we[0]),
.csr_di(per_din),
.csr_do(per_dout_ddr1),
/* Simple FML 4x64 interface to the memory contents */
.fml_adr(ext_frame_RAM1_addr),
.fml_stb(ext_frame_RAM1_cs_n),
.fml_we(ext_frame_RAM1_wr),
.fml_ack(),
.fml_sel(fml_sel_ddr1),
.fml_di(nova0_fml_di),
.fml_do(fml_do_ddr1),
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
.sdram_cke(ddr1_cke_i),
.sdram_cs_n(ddr1_cs_n_i),
.sdram_we_n(ddr1_we_n_i),
.sdram_cas_n(ddr1_cas_n_i),
.sdram_ras_n(ddr1_ras_n_i),
.sdram_adr(ddr1_adr_i),
.sdram_ba(ddr1_ba_i),
.sdram_dm(ddr1_dm_i),
.sdram_dq(ddr1_dq),
.sdram_dqs(ddr1_dqs),
/* Interface to the DCM generating DQS */
.dqs_psen(),
.dqs_psincdec(),
.dqs_psdone(1'b0),
.pll_stat({sys_pll_lock,sys_pll_lock_sync})
);
// NOVA 1 clock gate
always @(negedge mclk_i ) enable_nova1 <= power_iso[1];
AND2_X1_HVT i_nova1_cg (.A1(mclk_i), .A2(enable_nova1), .ZN(mclk_nova1) );
nova_wrapper nova1 (
.clk(mclk_nova1),
.clk_reg(smclk),
.reset_n(reset_n_i),
.per_dout(per_dout_nova1),
.per_addr(per_addr),
.per_din(per_din[15:0]),
.per_en(per_en),
.per_we(per_we),
.BitStream_buffer_input(BitStream_buffer_input_1_i),
.BitStream_ram_ren(BitStream_ram_ren_1_i),
.BitStream_ram_addr(BitStream_ram_addr_1_i),
.ext_frame_RAM0_cs_n(ext_frame_RAM2_cs_n),
.ext_frame_RAM0_wr(ext_frame_RAM2_wr),
.ext_frame_RAM0_addr(ext_frame_RAM2_addr),
.ext_frame_RAM0_data(ext_frame_RAM2_data),
.ext_frame_RAM1_cs_n(ext_frame_RAM3_cs_n),
.ext_frame_RAM1_wr(ext_frame_RAM3_wr),
.ext_frame_RAM1_addr(ext_frame_RAM3_addr),
.ext_frame_RAM1_data(ext_frame_RAM3_data),
.dis_frame_RAM_din(dis_frame_RAM_din_1),
.power_ack(power_ack[1]),
.power_control(power_control[1])
);
// DDR port 2
// Dummy register to create control signal
reg [7:0] fml_sel_ddr2;
always @ (posedge mclk_nova1 )
begin
if ( ext_frame_RAM2_cs_n == 1'b0 )
if ( ext_frame_RAM0_wr )
fml_sel_ddr2 <= dis_frame_RAM_din_1[7:0];
else
fml_sel_ddr2 <= dis_frame_RAM_din_1[15:8];
end
// Dummy register to expand DDR bus to 64 bits
reg [31:0] nova1_data_extend;
wire [63:0]nova1_fml_di;
always @ (posedge mclk_nova1 ) nova1_data_extend <= dis_frame_RAM_din_1;
assign nova1_fml_di = { nova1_data_extend, dis_frame_RAM_din_1 };
assign ext_frame_RAM2_data = ext_frame_RAM2_addr[13] ? fml_do_ddr2 [63:32] : fml_do_ddr2 [31:0] ;
hpdmc #(
.csr_addr(4'h2),
.sdram_depth(14),
.sdram_columndepth(9)
) nova0_ddr2 (
.sys_clk(mclk_nova1),
.sys_clk_n(!mclk_nova1),
.dqs_clk(mclk_nova1),
.dqs_clk_n(!mclk_nova1),
.sys_rst(!reset_n_i),
/* Control interface */
.csr_a(per_addr),
.csr_we(per_we[0]),
.csr_di(per_din),
.csr_do(per_dout_ddr2),
/* Simple FML 4x64 interface to the memory contents */
.fml_adr(ext_frame_RAM2_addr),
.fml_stb(ext_frame_RAM2_cs_n),
.fml_we(ext_frame_RAM2_wr),
.fml_ack(),
.fml_sel(fml_sel_ddr2),
.fml_di(nova1_fml_di),
.fml_do(fml_do_ddr2),
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
.sdram_cke(ddr2_cke_i),
.sdram_cs_n(ddr2_cs_n_i),
.sdram_we_n(ddr2_we_n_i),
.sdram_cas_n(ddr2_cas_n_i),
.sdram_ras_n(ddr2_ras_n_i),
.sdram_adr(ddr2_adr_i),
.sdram_ba(ddr2_ba_i),
.sdram_dm(ddr2_dm_i),
.sdram_dq(ddr2_dq),
.sdram_dqs(ddr2_dqs),
/* Interface to the DCM generating DQS */
.dqs_psen(),
.dqs_psincdec(),
.dqs_psdone(1'b0),
.pll_stat({sys_pll_lock,sys_pll_lock_sync})
);
// DDR port 3
// Dummy register to create control signal
reg [7:0] fml_sel_ddr3;
always @ (posedge mclk_nova1 )
begin
if ( ext_frame_RAM3_cs_n == 1'b0 )
if ( ext_frame_RAM0_wr )
fml_sel_ddr3 <= dis_frame_RAM_din_1[23:16];
else
fml_sel_ddr3 <= dis_frame_RAM_din_1[31:24];
end
assign ext_frame_RAM3_data = ext_frame_RAM3_addr[13] ? fml_do_ddr3 [63:32] : fml_do_ddr3 [31:0] ;
hpdmc #(
.csr_addr(4'h1),
.sdram_depth(14),
.sdram_columndepth(9)
) nova0_ddr3 (
.sys_clk(mclk_nova1),
.sys_clk_n(!mclk_nova1),
.dqs_clk(mclk_nova1),
.dqs_clk_n(!mclk_nova1),
.sys_rst(!reset_n_i),
/* Control interface */
.csr_a(per_addr),
.csr_we(per_we[0]),
.csr_di(per_din),
.csr_do(per_dout_ddr3),
/* Simple FML 4x64 interface to the memory contents */
.fml_adr(ext_frame_RAM3_addr),
.fml_stb(ext_frame_RAM3_cs_n),
.fml_we(ext_frame_RAM3_wr),
.fml_ack(),
.fml_sel(fml_sel_ddr3),
.fml_di(nova1_fml_di),
.fml_do(fml_do_ddr3),
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
.sdram_cke(ddr3_cke_i),
.sdram_cs_n(ddr3_cs_n_i),
.sdram_we_n(ddr3_we_n_i),
.sdram_cas_n(ddr3_cas_n_i),
.sdram_ras_n(ddr3_ras_n_i),
.sdram_adr(ddr3_adr_i),
.sdram_ba(ddr3_ba_i),
.sdram_dm(ddr3_dm_i),
.sdram_dq(ddr3_dq),
.sdram_dqs(ddr3_dqs),
/* Interface to the DCM generating DQS */
.dqs_psen(),
.dqs_psincdec(),
.dqs_psdone(1'b0),
.pll_stat({sys_pll_lock,sys_pll_lock_sync})
);
usb_sys i_usbf (
// WISHBONE Interface
// QSG .power_ack(power_ack_2),
// QSG .power_control(power_control_2),
.clk_i(mclk_i),
.rst_i(reset_n_i),
.wb_addr_i(dmem_addr[17:0]),
.wb_data_i(per_din),
.wb_data_o(per_dout_usb),
.wb_we_i(per_we[0]),
.wb_stb_i(per_en),
.inta_o(usb_intb),
.intb_o(usb_inta),
// UTMI Interface
.phy_clk_pad_i(usb_clk),
.phy_rst_pad_o(phy_rst_pad),
.DataOut_pad_o(usb_DataOut),
.TxValid_pad_o(usb_TxValid),
.TxReady_pad_i(usb_TxReady),
.RxValid_pad_i (usb_RxValid),
.RxActive_pad_i (usb_RxActive),
.RxError_pad_i (usb_RxError),
.DataIn_pad_i (usb_DataIn),
.LineState_pad_i (usb_LineState)
);
usb_phy i_usb_phy(
.clk(usb_clk),
.rst(phy_rst_pad),
.phy_tx_mode(1'b0),
.usb_rst(),
// UTMI Interface
.DataOut_i (usb_DataOut),
.TxValid_i (usb_TxValid),
.TxReady_o (usb_TxReady),
.RxValid_o (usb_RxValid),
.RxActive_o (usb_RxActive),
.RxError_o (usb_RxError),
.DataIn_o (usb_DataIn),
.LineState_o (usb_LineState),
.txdp(usb_txdp),
.txdn(usb_txdn),
.txoe(usb_txoe),
.rxd(usb_rxd),
.rxdp(usb_rxdp),
.rxdn(usb_rxdn)
);
// --------------------
// Main PLL
// DIVR = 1, DIVF = 80. DIVQ = 2
// Overall Multiply by 40
// --------------------
PLL i_MAIN_PLL (
.REF(lfxt_clk_i), // Reference clock
.FB(dco_clk), // Feedback clock
.FSE(1'b1), // Selects source of feedback input
.BYPASS(1'b0),
.RESET(!reset_n_i),
.DIVF7(1'b0), .DIVF6(1'b1), .DIVF5(1'b0), .DIVF4(1'b0), .DIVF3(1'b1), .DIVF2(1'b1), .DIVF1(1'b1), .DIVF0(1'b1),
.DIVQ2(1'b0), .DIVQ1(1'b0), .DIVQ0(1'b1),
.DIVR5(1'b0), .DIVR4(1'b0), .DIVR3(1'b0), .DIVR2(1'b0), .DIVR1(1'b0), .DIVR0(1'b0),
.RANGE2(1'b0), .RANGE1(1'b0), .RANGE0(1'b1),
.LOCK(sys_pll_lock),
.PLLOUT(pll_clk_o)
);
//assign pll_clk = scan_mode_i ? sysclk_byp_i : pll_clk_o;
MUX2_X2_HVT i_sys_clk_mux ( .A(pll_clk_o), .B(sysclk_byp_i), .S(scan_mode_i), .Z(pll_clk) );
// --------------------
// USB PLL
// DIVR = 1, DIVF = 96. DIVQ = 16
// Overall Multiply by 6
// --------------------
PLL i_USB_PLL (
.REF(lfxt_clk_i), // Reference clock
.FB(1'b0), // Feedback clock
.FSE(1'b1), // Selects source of feedback input
.BYPASS(1'b0),
.RESET(!reset_n_i),
.DIVF7(1'b0), .DIVF6(1'b1), .DIVF5(1'b0), .DIVF4(1'b1), .DIVF3(1'b1), .DIVF2(1'b1), .DIVF1(1'b1), .DIVF0(1'b1),
.DIVQ2(1'b1), .DIVQ1(1'b0), .DIVQ0(1'b0),
.DIVR5(1'b0), .DIVR4(1'b0), .DIVR3(1'b0), .DIVR2(1'b0), .DIVR1(1'b0), .DIVR0(1'b0),
.RANGE2(1'b0), .RANGE1(1'b0), .RANGE0(1'b1),
.LOCK(), // ??? Will it be used?
.PLLOUT(usb_clk_o)
);
//assign usb_clk = scan_mode_i ? usbclk_byp_i : usb_clk_o;
MUX2_X2_HVT i_usb_clk_mux ( .A(usb_clk_o), .B(usbclk_byp_i), .S(scan_mode_i), .Z(usb_clk) );
endmodule

160
demo_chip_rtl/rtl/demo_chip/nova_wrapper.v Executable file
View File

@ -0,0 +1,160 @@
////////////////////////////////////////////////////////////////////
// Design : nova_wrapper
// Author(s) :
// Creation date : August 13,2013
// Copyright (C) ...
////////////////////////////////////////////////////////////////////
// Description: Includes nova module and associated registers
//
////////////////////////////////////////////////////////////////////
module nova_wrapper(
input clk,
input clk_reg,
input reset_n,
input power_control,
output power_ack,
//---register access---
output [15:0] per_dout,
input [13:0] per_addr,
input [15:0] per_din,
input per_en,
input [1:0] per_we,
input [15:0] BitStream_buffer_input,
output BitStream_ram_ren,
output [16:0] BitStream_ram_addr,
//---ext_frame_RAM0---
output ext_frame_RAM0_cs_n,
output ext_frame_RAM0_wr,
output [13:0] ext_frame_RAM0_addr,
input [31:0] ext_frame_RAM0_data,
//---ext_frame_RAM1---
output ext_frame_RAM1_cs_n,
output ext_frame_RAM1_wr,
output [13:0] ext_frame_RAM1_addr,
input [31:0] ext_frame_RAM1_data,
output [31:0] dis_frame_RAM_din
);
//assign power_ack=power_control;//To ask RnD how to declare control
//and acknowledgement of power switch chains in RTL
// nova pins stored in registers
wire slice_header_s6;
wire [5:0] pic_num;
wire freq_ctrl0, freq_ctrl1, pin_disable_DF;
///////////////
// Registers //
///////////////
// Code copied and modified from Opencores openMSP430 periph/template_periph_16b.v
// 1) PARAMETER DECLARATION
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0190;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 3;
// Register addresses offset
parameter [DEC_WD-1:0] CNTRL1 = 'h0,
CNTRL2 = 'h2;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1),
CNTRL2_D = (BASE_REG << CNTRL2);
// 2) REGISTER DECODER
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr == CNTRL1 )}}) |
(CNTRL2_D & {DEC_SZ{(reg_addr == CNTRL2 )}});
// Read/Write probes
wire reg_write = |per_we & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
// 3) REGISTERS
// CNTRL1 Register
wire [15:0] cntrl1;
assign cntrl1 = {slice_header_s6, 9'b0, pic_num[5:0]};
// CNTRL2 Register
reg [15:0] cntrl2;
wire cntrl2_wr = reg_wr[CNTRL2];
always @ (posedge clk_reg or negedge reset_n)
if (!reset_n) cntrl2 <= 16'h0000;
else if (cntrl2_wr) cntrl2 <= per_din;
// Reset sync
reg reset_n_sync;
always @ (posedge clk_reg or negedge reset_n)
begin
if (!reset_n)
reset_n_sync <= 1'b0;
else
reset_n_sync <= reset_n;
end
assign freq_ctrl0 = cntrl2[0];
assign freq_ctrl1 = cntrl2[1];
assign pin_disable_DF = cntrl2[2];
// 4) DATA OUTPUT GENERATION
// Data output mux
wire [15:0] cntrl1_rd = cntrl1 & {16{reg_rd[CNTRL1]}};
wire [15:0] cntrl2_rd = cntrl2 & {16{reg_rd[CNTRL2]}};
assign per_dout = cntrl1_rd | cntrl2_rd ;
//////////////////
// NOVA decoder //
//////////////////
nova nova (
.clk(clk),
.reset_n(reset_n_sync),
.freq_ctrl0(freq_ctrl0),
.freq_ctrl1(freq_ctrl1),
.BitStream_buffer_input(BitStream_buffer_input),
.BitStream_ram_ren(BitStream_ram_ren),
.BitStream_ram_addr(BitStream_ram_addr),
.pic_num(pic_num),
.pin_disable_DF(pin_disable_DF),
.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
.ext_frame_RAM0_data(ext_frame_RAM0_data),
.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
.ext_frame_RAM1_data(ext_frame_RAM1_data),
.dis_frame_RAM_din(dis_frame_RAM_din),
.slice_header_s6(slice_header_s6)
);
endmodule

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// --------------------------------------------------
// Simple CPU writable register
// Outputs can be used to control power down signals
// --------------------------------------------------
module powerdown_control (
input clk,
input reset_n,
//---register access---
input [13:0] per_addr,
input [31:0] per_din,
input per_en,
input per_we,
input per_rd,
input [31:0] power_ack,
output reg [31:0] per_dout,
output reg [31:0] power_control,
output reg [31:0] power_iso
);
parameter [13:0] BASE_ADDR = 14'h400;
always @(posedge clk or negedge reset_n)
begin
if ( reset_n == 1'b0 )
begin
power_control = 32'h00000000;
power_iso = 32'h00000000;
end
else
begin
// Write reg
if ( per_en == 1'b1 && per_we == 1'b0 && per_addr[13:4] == BASE_ADDR[13:4])
begin
case (per_addr[3:0])
4'h0 : power_control = per_din;
4'h1 : power_iso = per_din;
endcase
end
end
end
// read_reg
always @(*)
begin
if ( per_en == 1'b1 && per_rd == 1'b1 && per_addr[13:4] == BASE_ADDR[13:4])
begin
case (per_addr[3:0])
4'h0 : per_dout = power_control;
4'h1 : per_dout = power_iso;
4'h2 : per_dout = power_ack;
default : per_dout = 32'h00000000;
endcase
end
else
per_dout = 32'h00000000;
end
endmodule

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module usb_sys (// WISHBONE Interface
clk_i, rst_i,
wb_addr_i, wb_data_i, wb_data_o,
wb_we_i, wb_stb_i, inta_o, intb_o,
// UTMI Interface
phy_clk_pad_i, phy_rst_pad_o,
DataOut_pad_o, TxValid_pad_o, TxReady_pad_i,
RxValid_pad_i, RxActive_pad_i, RxError_pad_i,
// QSG DataIn_pad_i, LineState_pad_i, power_control, power_ack
DataIn_pad_i, LineState_pad_i
);
//QSG input power_control;
//QSG output power_ack;
input clk_i;
input rst_i;
input [17:0] wb_addr_i;
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input wb_we_i;
input wb_stb_i;
output inta_o;
output intb_o;
input phy_clk_pad_i;
output phy_rst_pad_o;
output [7:0] DataOut_pad_o;
output TxValid_pad_o;
input TxReady_pad_i;
input [7:0] DataIn_pad_i;
input RxValid_pad_i;
input RxActive_pad_i;
input RxError_pad_i;
input [1:0] LineState_pad_i;
wire [13:0] usb_buf_addr;
wire [31:0] usb_buf_dout;
wire [31:0] usb_buf_din;
wire usb_buf_wen;
wire usb_buf_ren;
usbf_top i_usbf (
//QSG .power_control(power_control),
//QSG .power_ack(power_ack),
// WISHBONE Interface
.clk_i(clk_i),
.rst_i(rst_i),
.wb_addr_i(wb_addr_i),
.wb_data_i(wb_data_i),
.wb_data_o(wb_data_o),
.wb_ack_o(),
.wb_we_i(wb_we_i),
.wb_stb_i(wb_stb_i),
.wb_cyc_i(1'b0),
.inta_o(inta_o),
.intb_o(intb_o),
.dma_req_o(),
.dma_ack_i(16'b0),
.susp_o(),
.resume_req_i(1'b0),
// UTMI Interface
.phy_clk_pad_i(phy_clk_pad_i),
.phy_rst_pad_o(phy_rst_pad_o),
.DataOut_pad_o(DataOut_pad_o),
.TxValid_pad_o(TxValid_pad_o),
.TxReady_pad_i(TxReady_pad_i),
.RxValid_pad_i (RxValid_pad_i),
.RxActive_pad_i (RxActive_pad_i),
.RxError_pad_i (RxError_pad_i),
.DataIn_pad_i (DataIn_pad_i),
.XcvSelect_pad_o (),
.TermSel_pad_o (),
.SuspendM_pad_o (),
.LineState_pad_i (LineState_pad_i),
.OpMode_pad_o(),
.usb_vbus_pad_i(1'b0),
.VControl_Load_pad_o(),
.VControl_pad_o(),
.VStatus_pad_i(8'b0),
// Buffer Memory Interface
.sram_adr_o(usb_buf_addr),
.sram_data_i(usb_buf_dout),
.sram_data_o(usb_buf_din),
.sram_re_o(usb_buf_ren),
.sram_we_o(usb_buf_wen)
);
MemGen_32_14 usb_buffer_mem (
.chip_en(1'b1),
.clock(clk_i),
.addr(usb_buf_addr),
.rd_data(usb_buf_dout),
.rd_en(usb_buf_ren),
.wr_data(usb_buf_din),
.wr_en(usb_buf_wen )
);
endmodule

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TEX=hpdmc.tex
DVI=$(TEX:.tex=.dvi)
PS=$(TEX:.tex=.ps)
PDF=$(TEX:.tex=.pdf)
AUX=$(TEX:.tex=.aux)
LOG=$(TEX:.tex=.log)
all: $(PDF)
%.dvi: %.tex
latex $<
%.ps: %.dvi
dvips $<
%.pdf: %.ps
ps2pdf $<
clean:
rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG)
.PHONY: clean

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\documentclass[a4paper,11pt]{article}
\usepackage{fullpage}
\usepackage[latin1]{inputenc}
\usepackage[T1]{fontenc}
\usepackage[normalem]{ulem}
\usepackage[english]{babel}
\usepackage{listings,babel}
\lstset{breaklines=true,basicstyle=\ttfamily}
\usepackage{graphicx}
\usepackage{moreverb}
\usepackage{url}
\usepackage{float}
\usepackage{tabularx}
\title{High Performance Dynamic Memory Controller}
\author{S\'ebastien Bourdeauducq}
\date{December 2009}
\begin{document}
\setlength{\parindent}{0pt}
\setlength{\parskip}{5pt}
\maketitle{}
\section{Specifications}
This controller is targeted at high bandwidth applications such as live video processing.
It is designed to drive 32-bit DDR SDRAM memory (which can be physically made up of two 16-bit chips).
The memory contents are accessed through a 64-bit FML (Fast Memory Link) bus with a burst length of 4. FML is a burst-oriented bus designed to ease the design of DRAM controllers. Its signaling resembles WISHBONE, but basically removes all corner cases with burst modes to save on logic resources and aspirin.
HPDMC provides high flexibility and savings on hardware by implementing a bypass mode which gives the CPU low-level access to the SDRAM command interface (address pins, bank address pins, and CKE, CS, WE, CAS and RAS). The SDRAM initialization sequence is assigned to the CPU, which should use this mode to implement it. Timing parameters are also configurable at runtime. These control interfaces are accessed on a 32-bit CSR bus, separate from the data bus. The CSR bus is a proprietary bus designed for Milkymist that helps reduce the FPGA resource usage and avoid failed timing paths on the system bus.
Due to the use of \verb!IDDR!, \verb!ODDR! and \verb!IDELAY! primitives, HPDMC currently only supports the Virtex-4 FPGAs.
\section{Architecture}
\begin{figure}[H]
\centering
\includegraphics[height=100mm]{blockdiagram.eps}
\caption{Block diagram of the HPDMC architecture.}\label{fig:blockdiagram}
\end{figure}
\subsection{Control interface}
The control interface provides a register bank on a low-speed dedicated CSR bus, which is used to control the operating mode of the core, set timings, and initialize the SDRAM.
The interface can access directly the SDRAM address and command bus in the so-called \textit{bypass mode}. In this mode, the memory controller is disabled and the CPU can control each pin of the SDRAM control bus through the bypass register.
This mode should be used at system boot-up to perform the SDRAM initialization sequence. HPDMC does not provide a hardware state machine that does such initialization.
The mapped registers are the following (addresses are in bytes to match the addresses seen by the CPU when the CSR bus is bridged to Wishbone) :
\subsubsection{System register, offset 0x00}
\begin{tabularx}{\textwidth}{|l|l|l|X|}
\hline
\bf Bits & \bf Access & \bf Default & \bf Description \\
\hline
0 & RW & 1 & Bypass mode enable. Setting this bit transfers control of the SDRAM command and address bus from HPDMC to the system CPU. This bit should be set during the SDRAM initialization sequence and cleared during normal memory access. \\
\hline
1 & RW & 1 & Reset. This bit should be cleared during normal operation and set while reconfiguring the memory subsystem. \\
\hline
2 & RW & 0 & CKE control. This bit directly drives the CKE pin of the SDRAM and should be always set except during the first stage of the initialization sequence. The core does not support SDRAM power-down modes, so clearing this bit during normal operation results in undefined behaviour. \\
\hline
31 -- 3 & --- & 0 & Reserved. \\
\hline
\end{tabularx}
\subsubsection{Bypass register, offset 0x04}
The bypass register gives the system CPU low-level access to the SDRAM. It must be used at system power-up to initialize the SDRAM, as the controller does not provide this initialization. Such software initialization of the SDRAM provides greater flexibility and saves valuable hardware resources.
Writing once to this register issues \textbf{one} transaction to the SDRAM command bus, ie. the values written to the CS, WE, RAS and CAS bits are only taken into account for one clock cycle, and then the signals go back to their default inactive state.
The values written to this register have an effect on the SDRAM only if the controller is put in bypass mode using the system register.\\
\begin{tabularx}{\textwidth}{|l|l|l|X|}
\hline
\bf Bits & \bf Access & \bf Default & \bf Description \\
\hline
0 & W & 0 & CS control. Setting this bit activates the CS line of the SDRAM during the command transaction that results from writing to the bypass register. As the SDRAM control bus is active low, setting this bit actually puts a '0' logic level to the CS line. \\
\hline
1 & W & 0 & WE control (same as above). \\
\hline
2 & W & 0 & CAS control (same as above). \\
\hline
3 & W & 0 & RAS control (same as above). \\
\hline
16 -- 4 & RW & 0 & Address. Defines the current state of the address pins. \\
\hline
18 -- 17 & RW & 0 & Bank address. Defines the current state of the bank address pins. \\
\hline
31 -- 19 & --- & 0 & Reserved. \\
\hline
\end{tabularx}\\
\textit{NB. When this register is written, the address pins change synchronously at the same time as the command pins, so there is no need to pre-position the address bits before issuing a command. Commands like loading the mode register can therefore be performed with a single write to this register.}
\subsubsection{Timing register, offset 0x08}
This register allows the CPU to tune the behaviour of HPDMC so that it meets SDRAM timing requirements while avoiding unnecessary wait cycles.
The controller must be held in reset using the system register when the timing register is modified.\\
\begin{tabularx}{\textwidth}{|l|l|l|X|}
\hline
\bf Bits & \bf Access & \bf Default & \bf Description \\
\hline
2 -- 0 & RW & 2 & Number of clock cycles the scheduler must wait following a Precharge command. Usually referred to as $t_{RP}$ in SDRAM datasheets. \\
\hline
5 -- 3 & RW & 2 & Number of clock cycles the scheduler must wait following an Activate command. Usually referred to as $t_{RCD}$ in SDRAM datasheets. \\
\hline
6 & RW & 0 & CAS latency : 0 = CL2, 1 = CL3. CL2.5 is not supported. \\
\hline
17 -- 7 & RW & 740 & Autorefresh period, in clock cycles. This is the time between \textbf{each} Auto Refresh command that is issued to the SDRAM, not the delay between two consecutive refreshes of a particular row. Usually referred to as $t_{REFI}$ in SDRAM datasheets, which is often 7.8$\mu$s (64ms is an improbable value for this field). \\
\hline
21 -- 18 & RW & 8 & Number of clock cycles the controller must wait following an Auto Refresh command. Usually referred to as $t_{RFC}$ in SDRAM datasheets. \\
\hline
23 -- 22 & RW & 1 & Number of clock cycles the controller must wait following the last data sent to the SDRAM during a write. Usually referred to as $t_{WR}$ in SDRAM datasheets. \\
\hline
31 -- 24 & --- & 0 & Reserved. \\
\hline
\end{tabularx}\\
\textit{NB. The default values are example only, and must be adapted to your particular setup.}
\subsubsection{Delay register, offset 0x0C}
This register controls the amount of delay that is introduced on the data lines when reading from memory. It directly controls the \verb!IDELAY! elements that are inserted between the pins and the \verb!IDDR! registers.
Writing once to the register toggles the \verb!IDELAY! control signals \textbf{once}, that is to say, the signals will be active for one clock cycle and then go back to their default zero state.
This register also controls the amount of phase shift that is introduced between the system clock and DQS (typically 90 degrees). HPDMC provides three signals, \verb!dqs_psen!, \verb!dqs_psincdec! and \verb!dqs_psdone! that should be connected to the DCM used to generate the DQS clock which is controlled by this register.
The enable and incrementation bits work the same as for \verb!IDELAY!. They should only be used when the ready bit (5) is set.\\
\begin{tabularx}{\textwidth}{|l|l|l|X|}
\hline
\bf Bits & \bf Access & \bf Default & \bf Description \\
\hline
0 & W & 0 & Resets delay to 0. If this bit is set, the others are ignored. \\
\hline
1 & W & 0 & Increments or decrements delay by one tap (typically 78ps). If the bit 2 is set at the same time this bit is written, the tap delay is incremented. Otherwise, it is decremented. \\
\hline
2 & W & 0 & Selects between incrementation and decrementation of the input tap delay. \\
\hline
3 & W & 0 & Increments or decrements the phase shift on DQS. If the bit 4 is set at the same time this bit is written, the phase shift is incremented. Otherwise, it is decremented. The phase shift is typically between -255 and 255 and is expressed in 1/256ths of the clock period. \\
\hline
4 & W & 0 & Selects between incrementation and decrementation of the DQS phase shift. \\
\hline
5 & R & 0 & When this bit is set, the DCM used to generate DQS is ready for phase shift. \\
\hline
7--6 & R & 0 & Retreives the values of the pll\_stat inputs of the core. These inputs are internally double-latched so that they can directly accept asynchronous signals. They are intended to monitor the lock status of the DCMs used to generate the SDRAM and DQS clocks. \\
\hline
31--8 & --- & 0 & Reserved. \\
\hline
\end{tabularx}
This register can be written to at any time.
\subsection{SDRAM management unit}
The SDRAM management unit is a state machine which controls sequentially the SDRAM address and command bus. Unless the core is in bypass mode, the management unit has full control over the SDRAM bus.
This unit is responsible for precharging banks, activating rows, periodically refreshing the DRAM, and sending read and write commands to the SDRAM.
It has inputs connected to the control interface registers to retreive the $t_{RP}$, $t_{RCD}$, $t_{REFI}$ and $t_{RFC}$ timing values, as well as the row idle time.
It handles read and write requests through a port made up of four elements :
\begin{itemize}
\item a strobe input
\item a write enable input (which tells if the command to send to the SDRAM should be a read or a write)
\item an address input
\item an acknowledgement output
\end{itemize}
The protocol used on these signals is close to the one employed in Wishbone. The strobe signal indicates when a new command should be completed, and remains asserted (with other signals kept constant) until the acknowledgement signal is asserted. At the next clock cycle, a new command should be presented, or the strobe signal should be de-asserted.
In HPDMC, those signals are driven by the bus interface.
The management unit also signals the data path when it has sent a read or a write command into the SDRAM. The signal is asserted exactly at the same time as the command is asserted.
It receives \verb!read_safe!, \verb!write_safe! and \verb!precharge_safe! signals from the data path, whose meanings are explained below.
\subsection{Data path controller}
The data path controller is responsible for :
\begin{itemize}
\item deciding the direction of the DQ and DQS pins
\item delaying read, write and precharge commands from the management unit that would create conflicts
\end{itemize}
The delaying of the commands is acheived through the use of three signals :
\begin{itemize}
\item \verb!read_safe! : when this signal is asserted, it is safe to send a Read command to the SDRAM. This is used to prevent conflicts on the data bus : this signal is asserted when, taking into account the CAS latency and the burst length, the resulting burst would not overlap the currently running one.
\item \verb!write_safe! : same thing, for the Write command.
\item \verb!concerned_bank[3..0]! : when the management unit issues a Read or Write command, it must inform the data path controller about the bank which the transfer takes place in, using this one-hot encoded signal.
\item \verb!precharge_safe[3..0]! : when a bit in this signal is asserted, it is safe to precharge the corresponding bank. The management unit must use this signal so as not to precharge a bank interrupting a read burst or causing a write-to-precharge violation.
\end{itemize}
The data path controller is also connected to the control interface, to retreive $t_{WR}$ and the CAS latency.
\subsection{Data path}
Data is captured from or sent to the SDRAM using \verb!IDDR! and \verb!ODDR! primitives, in order to limit timing nightmares with ISE.
When writing to the DDRAM, the \verb!ODDR! primitive puts out data synchronously to the rising and falling edges of the system clock. This was chosen to ease timing between the FML (which is clocked by the system clock) and the I/O elements without introducing additional latency cycles. The data should therefore be strobed by DQS after a short time following each system clock edge. A delay corresponding to a 90 degrees phase shift gives the best margins, and can be controlled using the delay register.
When reading from the DDRAM, the \verb!IDDR! element is also clocked by the system clock for the same reason. The data must therefore be delayed by typically one quarter of the clock cycle so that it becomes center-aligned with the system clock edges. \verb!IDELAY! primitives are used for this purpose. DQS lines are not used for reading.
\verb!ODDR!, \verb!IDDR! and \verb!IDELAY! are only supported on Virtex-4 FPGAs, but have equivalents in other families.
\subsection{Bus interface}
The bus interface is responsible for sending commands to the SDRAM management unit according to the request coming from the FML, and acknowledging bus cycles at the appropriate time.
\section{Using the core}
\subsection{Connecting}
The differential clock going to the SDRAM chips should be generated using a dedicated FPGA clocking resource, such as a DCM. It is bad practice to simply add an inverter on the negative clock line, as the inverter will also add a delay.
This DCM can also introduce a 90 degree delay on the clock and the resulting signal be used to generate DQS by connecting it to the \verb!dqs_clk! input of the HPDMC top-level.
HPDMC uses \verb!IDELAY! elements internally, but does not include the required \verb!IDELAYCTRL! primitive. You must instantiate an \verb!IDELAYCTRL! in your design, generate the 200MHz reference clock and connect it to the \verb!IDELAYCTRL! through a \verb!BUFG!. The other signals of \verb!IDELAYCTRL! can be left unused.
\subsection{Programming}
When the system is powered up, HPDMC comes up in bypass mode and the SDRAM initialization sequence should be performed from then, by controlling the pins at a low level using the bypass register.
The SDRAM must be programmed to use a fixed burst length of 8\footnote{It might seem surprising that the burst length of the SDRAM and FML are not the same. This is because DDR SDRAM counts the words on both clock edges. Here, a burst of 8 32-bit words sent at double data rate on the SDRAM side corresponds to a burst of 4 64-bit words at single data rate on the FML side.}, and a CAS latency of 2 (preferred) or 3. CAS latency 2.5 is not supported.
HPDMC's timing registers may also have to be reprogrammed to match the memory chip's parameters. If a DIMM is used, it is possible to read those parameters from the serial presence detect (SPD) EEPROM and program HPDMC accordingly.
Once the SDRAM is initialized and the timing registers are programmed, the controller can be brought up by clearing the bypass and reset bits from the system register.
You may also need to tune the data capture delay. Reset the tap count to 0 by writing bit 0 to the delay register, then increment the delay to the desired value by repeatedly writing bits 1 and 2 simultaneously.
The DQS phase shift may also be adjusted. The procedure is the same, except that the delay cannot be reset and that the ready bit should be set when writing the enable and incrementation bits. The memory is now ready to be accessed over the FML interface.
\section*{Copyright notice}
Copyright \copyright 2007-2009 S\'ebastien Bourdeauducq. \\
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution.
\end{document}

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/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc #(
parameter csr_addr = 4'h0,
/*
* The depth of the SDRAM array, in bytes.
* Capacity (in bytes) is 2^sdram_depth.
*/
parameter sdram_depth = 26,
/*
* The number of column address bits of the SDRAM.
*/
parameter sdram_columndepth = 9
) (
input sys_clk,
input sys_clk_n,
/*
* Clock used to generate DQS.
* Typically sys_clk phased out by 90 degrees,
* as data is sent synchronously to sys_clk.
*/
input dqs_clk,
input dqs_clk_n,
input sys_rst,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Simple FML 4x64 interface to the memory contents */
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_ack,
input [7:0] fml_sel,
input [63:0] fml_di,
output [63:0] fml_do,
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
output reg sdram_cke,
output reg sdram_cs_n,
output reg sdram_we_n,
output reg sdram_cas_n,
output reg sdram_ras_n,
output reg [12:0] sdram_adr,
output reg [1:0] sdram_ba,
output [3:0] sdram_dm,
inout [31:0] sdram_dq,
inout [3:0] sdram_dqs,
/* Interface to the DCM generating DQS */
output dqs_psen,
output dqs_psincdec,
input dqs_psdone,
input [1:0] pll_stat
);
/* Register all control signals, leaving the possibility to use IOB registers */
wire sdram_cke_r;
wire sdram_cs_n_r;
wire sdram_we_n_r;
wire sdram_cas_n_r;
wire sdram_ras_n_r;
wire [12:0] sdram_adr_r;
wire [1:0] sdram_ba_r;
always @(posedge sys_clk) begin
sdram_cke <= sdram_cke_r;
sdram_cs_n <= sdram_cs_n_r;
sdram_we_n <= sdram_we_n_r;
sdram_cas_n <= sdram_cas_n_r;
sdram_ras_n <= sdram_ras_n_r;
sdram_ba <= sdram_ba_r;
sdram_adr <= sdram_adr_r;
end
/* Mux the control signals according to the "bypass" selection.
* CKE always comes from the control interface.
*/
wire bypass;
wire sdram_cs_n_bypass;
wire sdram_we_n_bypass;
wire sdram_cas_n_bypass;
wire sdram_ras_n_bypass;
wire [12:0] sdram_adr_bypass;
wire [1:0] sdram_ba_bypass;
wire sdram_cs_n_mgmt;
wire sdram_we_n_mgmt;
wire sdram_cas_n_mgmt;
wire sdram_ras_n_mgmt;
wire [12:0] sdram_adr_mgmt;
wire [1:0] sdram_ba_mgmt;
assign sdram_cs_n_r = bypass ? sdram_cs_n_bypass : sdram_cs_n_mgmt;
assign sdram_we_n_r = bypass ? sdram_we_n_bypass : sdram_we_n_mgmt;
assign sdram_cas_n_r = bypass ? sdram_cas_n_bypass : sdram_cas_n_mgmt;
assign sdram_ras_n_r = bypass ? sdram_ras_n_bypass : sdram_ras_n_mgmt;
assign sdram_adr_r = bypass ? sdram_adr_bypass : sdram_adr_mgmt;
assign sdram_ba_r = bypass ? sdram_ba_bypass : sdram_ba_mgmt;
/* Control interface */
wire sdram_rst;
wire [2:0] tim_rp;
wire [2:0] tim_rcd;
wire tim_cas;
wire [10:0] tim_refi;
wire [3:0] tim_rfc;
wire [1:0] tim_wr;
wire idelay_rst;
wire idelay_ce;
wire idelay_inc;
hpdmc_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.bypass(bypass),
.sdram_rst(sdram_rst),
.sdram_cke(sdram_cke_r),
.sdram_cs_n(sdram_cs_n_bypass),
.sdram_we_n(sdram_we_n_bypass),
.sdram_cas_n(sdram_cas_n_bypass),
.sdram_ras_n(sdram_ras_n_bypass),
.sdram_adr(sdram_adr_bypass),
.sdram_ba(sdram_ba_bypass),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_cas(tim_cas),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.tim_wr(tim_wr),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc),
.dqs_psen(dqs_psen),
.dqs_psincdec(dqs_psincdec),
.dqs_psdone(dqs_psdone),
.pll_stat(pll_stat)
);
/* SDRAM management unit */
wire mgmt_stb;
wire mgmt_we;
wire [sdram_depth-3-1:0] mgmt_address;
wire mgmt_ack;
wire read;
wire write;
wire [3:0] concerned_bank;
wire read_safe;
wire write_safe;
wire [3:0] precharge_safe;
hpdmc_mgmt #(
.sdram_depth(sdram_depth),
.sdram_columndepth(sdram_columndepth)
) mgmt (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.stb(mgmt_stb),
.we(mgmt_we),
.address(mgmt_address),
.ack(mgmt_ack),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.sdram_cs_n(sdram_cs_n_mgmt),
.sdram_we_n(sdram_we_n_mgmt),
.sdram_cas_n(sdram_cas_n_mgmt),
.sdram_ras_n(sdram_ras_n_mgmt),
.sdram_adr(sdram_adr_mgmt),
.sdram_ba(sdram_ba_mgmt)
);
/* Bus interface */
wire data_ack;
hpdmc_busif #(
.sdram_depth(sdram_depth)
) busif (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.mgmt_stb(mgmt_stb),
.mgmt_we(mgmt_we),
.mgmt_address(mgmt_address),
.mgmt_ack(mgmt_ack),
.data_ack(data_ack)
);
/* Data path controller */
wire direction;
wire direction_r;
hpdmc_datactl datactl(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.ack(data_ack),
.direction(direction),
.direction_r(direction_r),
.tim_cas(tim_cas),
.tim_wr(tim_wr)
);
/* Data path */
hpdmc_ddrio ddrio(
.sys_clk(sys_clk),
.sys_clk_n(sys_clk_n),
.dqs_clk(dqs_clk),
.dqs_clk_n(dqs_clk_n),
.direction(direction),
.direction_r(direction_r),
/* Bit meaning is the opposite between
* the FML selection signal and SDRAM DM pins.
*/
.mo(~fml_sel),
.do(fml_di),
.di(fml_do),
.sdram_dm(sdram_dm),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc)
);
endmodule

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/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_banktimer(
input sys_clk,
input sdram_rst,
input tim_cas,
input [1:0] tim_wr,
input read,
input write,
output reg precharge_safe
);
reg [2:0] counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter <= 3'd0;
precharge_safe <= 1'b1;
end else begin
if(read) begin
/* see p.26 of datasheet :
* "A Read burst may be followed by, or truncated with, a Precharge command
* to the same bank. The Precharge command should be issued x cycles after
* the Read command, where x equals the number of desired data element
* pairs"
*/
counter <= 3'd4;
precharge_safe <= 1'b0;
end else if(write) begin
counter <= {1'b1, tim_wr};
precharge_safe <= 1'b0;
end else begin
if(counter == 3'b1)
precharge_safe <= 1'b1;
if(~precharge_safe)
counter <= counter - 3'b1;
end
end
end
endmodule

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/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Simple FML interface for HPDMC */
module hpdmc_busif #(
parameter sdram_depth = 26
) (
input sys_clk,
input sdram_rst,
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_ack,
output mgmt_stb,
output mgmt_we,
output [sdram_depth-3-1:0] mgmt_address, /* in 64-bit words */
input mgmt_ack,
input data_ack
);
reg mgmt_stb_en;
assign mgmt_stb = fml_stb & mgmt_stb_en;
assign mgmt_we = fml_we;
assign mgmt_address = fml_adr[sdram_depth-1:3];
assign fml_ack = data_ack;
always @(posedge sys_clk) begin
if(sdram_rst)
mgmt_stb_en = 1'b1;
else begin
if(mgmt_ack)
mgmt_stb_en = 1'b0;
if(data_ack)
mgmt_stb_en = 1'b1;
end
end
endmodule

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/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_ctlif #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output reg bypass,
output reg sdram_rst,
output reg sdram_cke,
output reg sdram_cs_n,
output reg sdram_we_n,
output reg sdram_cas_n,
output reg sdram_ras_n,
output reg [12:0] sdram_adr,
output reg [1:0] sdram_ba,
/* Clocks we must wait following a PRECHARGE command (usually tRP). */
output reg [2:0] tim_rp,
/* Clocks we must wait following an ACTIVATE command (usually tRCD). */
output reg [2:0] tim_rcd,
/* CAS latency, 0 = 2 */
output reg tim_cas,
/* Auto-refresh period (usually tREFI). */
output reg [10:0] tim_refi,
/* Clocks we must wait following an AUTO REFRESH command (usually tRFC). */
output reg [3:0] tim_rfc,
/* Clocks we must wait following the last word written to the SDRAM (usually tWR). */
output reg [1:0] tim_wr,
output reg idelay_rst,
output reg idelay_ce,
output reg idelay_inc,
output reg dqs_psen,
output reg dqs_psincdec,
input dqs_psdone,
input [1:0] pll_stat
);
reg psready;
always @(posedge sys_clk) begin
if(dqs_psdone)
psready <= 1'b1;
else if(dqs_psen)
psready <= 1'b0;
end
wire csr_selected = csr_a[13:10] == csr_addr;
/* Double-latching on pll_stat (asynchronous) */
reg [1:0] pll_stat1;
reg [1:0] pll_stat2;
always @(posedge sys_clk) begin
pll_stat1 <= pll_stat;
pll_stat2 <= pll_stat1;
end
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do <= 32'd0;
bypass <= 1'b1;
sdram_rst <= 1'b1;
sdram_cke <= 1'b0;
sdram_adr <= 13'd0;
sdram_ba <= 2'd0;
tim_rp <= 3'd2;
tim_rcd <= 3'd2;
tim_cas <= 1'b0;
tim_refi <= 11'd740;
tim_rfc <= 4'd8;
tim_wr <= 2'd2;
end else begin
sdram_cs_n <= 1'b1;
sdram_we_n <= 1'b1;
sdram_cas_n <= 1'b1;
sdram_ras_n <= 1'b1;
idelay_rst <= 1'b0;
idelay_ce <= 1'b0;
idelay_inc <= 1'b0;
dqs_psen <= 1'b0;
dqs_psincdec <= 1'b0;
csr_do <= 32'd0;
if(csr_selected) begin
if(csr_we) begin
case(csr_a[1:0])
2'b00: begin
bypass <= csr_di[0];
sdram_rst <= csr_di[1];
sdram_cke <= csr_di[2];
end
2'b01: begin
sdram_cs_n <= ~csr_di[0];
sdram_we_n <= ~csr_di[1];
sdram_cas_n <= ~csr_di[2];
sdram_ras_n <= ~csr_di[3];
sdram_adr <= csr_di[16:4];
sdram_ba <= csr_di[18:17];
end
2'b10: begin
tim_rp <= csr_di[2:0];
tim_rcd <= csr_di[5:3];
tim_cas <= csr_di[6];
tim_refi <= csr_di[17:7];
tim_rfc <= csr_di[21:18];
tim_wr <= csr_di[23:22];
end
2'b11: begin
idelay_rst <= csr_di[0];
idelay_ce <= csr_di[1];
idelay_inc <= csr_di[2];
dqs_psen <= csr_di[3];
dqs_psincdec <= csr_di[4];
end
endcase
end
case(csr_a[1:0])
2'b00: csr_do <= {sdram_cke, sdram_rst, bypass};
2'b01: csr_do <= {sdram_ba, sdram_adr, 4'h0};
2'b10: csr_do <= {tim_wr, tim_rfc, tim_refi, tim_cas, tim_rcd, tim_rp};
2'b11: csr_do <= {pll_stat2, psready, 5'd0};
endcase
end
end
end
endmodule

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/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_datactl(
input sys_clk,
input sdram_rst,
input read,
input write,
input [3:0] concerned_bank,
output reg read_safe,
output reg write_safe,
output [3:0] precharge_safe,
output reg ack,
output reg direction,
output direction_r,
input tim_cas,
input [1:0] tim_wr
);
/*
* read_safe: whether it is safe to register a Read command
* into the SDRAM at the next cycle.
*/
reg [2:0] read_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
read_safe_counter <= 3'd0;
read_safe <= 1'b1;
end else begin
if(read) begin
read_safe_counter <= 3'd4;
read_safe <= 1'b0;
end else if(write) begin
/* after a write, read is unsafe for 5 cycles (4 transfers + tWTR=1) */
read_safe_counter <= 3'd5;
read_safe <= 1'b0;
end else begin
if(read_safe_counter == 3'd1)
read_safe <= 1'b1;
if(~read_safe)
read_safe_counter <= read_safe_counter - 3'd1;
end
end
end
/*
* write_safe: whether it is safe to register a Write command
* into the SDRAM at the next cycle.
*/
reg [2:0] write_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
write_safe_counter <= 3'd0;
write_safe <= 1'b1;
end else begin
if(read) begin
write_safe_counter <= {1'b1, tim_cas, ~tim_cas};
write_safe <= 1'b0;
end else if(write) begin
write_safe_counter <= 3'd3;
write_safe <= 1'b0;
end else begin
if(write_safe_counter == 3'd1)
write_safe <= 1'b1;
if(~write_safe)
write_safe_counter <= write_safe_counter - 3'd1;
end
end
end
/* Generate ack signal.
* After write is asserted, it should pulse after 2 cycles.
* After read is asserted, it should pulse after CL+3 cycles, that is
* 5 cycles when tim_cas = 0
* 6 cycles when tim_cas = 1
*/
reg ack_read3;
reg ack_read2;
reg ack_read1;
reg ack_read0;
always @(posedge sys_clk) begin
if(sdram_rst) begin
ack_read3 <= 1'b0;
ack_read2 <= 1'b0;
ack_read1 <= 1'b0;
ack_read0 <= 1'b0;
end else begin
if(tim_cas) begin
ack_read3 <= read;
ack_read2 <= ack_read3;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end else begin
ack_read2 <= read;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end
end
end
reg ack0;
always @(posedge sys_clk) begin
if(sdram_rst) begin
ack0 <= 1'b0;
ack <= 1'b0;
end else begin
ack0 <= ack_read0|write;
ack <= ack0;
end
end
/* during a 4-word write, we drive the pins for 5 cycles
* and 1 cycle in advance (first word is invalid)
* so that we remove glitches on DQS without resorting
* to asynchronous logic.
*/
/* direction must be glitch-free, as it directly drives the
* tri-state enable for DQ and DQS.
*/
reg write_d;
reg [2:0] counter_writedirection;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter_writedirection <= 3'd0;
direction <= 1'b0;
end else begin
if(write_d) begin
counter_writedirection <= 3'b101;
direction <= 1'b1;
end else begin
if(counter_writedirection == 3'b001)
direction <= 1'b0;
if(direction)
counter_writedirection <= counter_writedirection - 3'd1;
end
end
end
assign direction_r = write_d|(|counter_writedirection);
always @(posedge sys_clk) begin
if(sdram_rst)
write_d <= 1'b0;
else
write_d <= write;
end
/* Counters that prevent a busy bank from being precharged */
hpdmc_banktimer banktimer0(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[0]),
.write(write & concerned_bank[0]),
.precharge_safe(precharge_safe[0])
);
hpdmc_banktimer banktimer1(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[1]),
.write(write & concerned_bank[1]),
.precharge_safe(precharge_safe[1])
);
hpdmc_banktimer banktimer2(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[2]),
.write(write & concerned_bank[2]),
.precharge_safe(precharge_safe[2])
);
hpdmc_banktimer banktimer3(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[3]),
.write(write & concerned_bank[3]),
.precharge_safe(precharge_safe[3])
);
endmodule

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/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_mgmt #(
parameter sdram_depth = 26,
parameter sdram_columndepth = 9
) (
input sys_clk,
input sdram_rst,
input [2:0] tim_rp,
input [2:0] tim_rcd,
input [10:0] tim_refi,
input [3:0] tim_rfc,
input stb,
input we,
input [sdram_depth-3-1:0] address, /* in 64-bit words */
output reg ack,
output reg read,
output reg write,
output [3:0] concerned_bank,
input read_safe,
input write_safe,
input [3:0] precharge_safe,
output sdram_cs_n,
output sdram_we_n,
output sdram_cas_n,
output sdram_ras_n,
output [12:0] sdram_adr,
output [1:0] sdram_ba
);
/*
* Address Mapping :
* | ROW ADDRESS | BANK NUMBER | COL ADDRESS | for 32-bit words
* |depth-1 coldepth+2|coldepth+1 coldepth|coldepth-1 0|
* (depth for 32-bit words, which is sdram_depth-2)
*/
parameter rowdepth = sdram_depth-2-1-(sdram_columndepth+2)+1;
wire [sdram_depth-2-1:0] address32 = {address, 1'b0};
wire [sdram_columndepth-1:0] col_address = address32[sdram_columndepth-1:0];
wire [1:0] bank_address = address32[sdram_columndepth+1:sdram_columndepth];
wire [rowdepth-1:0] row_address = address32[sdram_depth-2-1:sdram_columndepth+2];
reg [3:0] bank_address_onehot;
always @(*) begin
case(bank_address)
2'b00: bank_address_onehot <= 4'b0001;
2'b01: bank_address_onehot <= 4'b0010;
2'b10: bank_address_onehot <= 4'b0100;
2'b11: bank_address_onehot <= 4'b1000;
endcase
end
/* Track open rows */
reg [3:0] has_openrow;
reg [rowdepth-1:0] openrows[0:3];
reg [3:0] track_close;
reg [3:0] track_open;
always @(posedge sys_clk) begin
if(sdram_rst) begin
has_openrow = 4'h0;
end else begin
has_openrow = (has_openrow | track_open) & ~track_close;
if(track_open[0]) openrows[0] <= row_address;
if(track_open[1]) openrows[1] <= row_address;
if(track_open[2]) openrows[2] <= row_address;
if(track_open[3]) openrows[3] <= row_address;
end
end
/* Bank precharge safety */
assign concerned_bank = bank_address_onehot;
wire current_precharge_safe =
(precharge_safe[0] | ~bank_address_onehot[0])
&(precharge_safe[1] | ~bank_address_onehot[1])
&(precharge_safe[2] | ~bank_address_onehot[2])
&(precharge_safe[3] | ~bank_address_onehot[3]);
/* Check for page hits */
wire bank_open = has_openrow[bank_address];
wire page_hit = bank_open & (openrows[bank_address] == row_address);
/* Address drivers */
reg sdram_adr_loadrow;
reg sdram_adr_loadcol;
reg sdram_adr_loadA10;
assign sdram_adr =
({13{sdram_adr_loadrow}} & row_address)
|({13{sdram_adr_loadcol}} & col_address)
|({13{sdram_adr_loadA10}} & 13'd1024);
assign sdram_ba = bank_address;
/* Command drivers */
reg sdram_cs;
reg sdram_we;
reg sdram_cas;
reg sdram_ras;
assign sdram_cs_n = ~sdram_cs;
assign sdram_we_n = ~sdram_we;
assign sdram_cas_n = ~sdram_cas;
assign sdram_ras_n = ~sdram_ras;
/* Timing counters */
/* The number of clocks we must wait following a PRECHARGE command (usually tRP). */
reg [2:0] precharge_counter;
reg reload_precharge_counter;
wire precharge_done = (precharge_counter == 3'd0);
always @(posedge sys_clk) begin
if(reload_precharge_counter)
precharge_counter <= tim_rp;
else if(~precharge_done)
precharge_counter <= precharge_counter - 3'd1;
end
/* The number of clocks we must wait following an ACTIVATE command (usually tRCD). */
reg [2:0] activate_counter;
reg reload_activate_counter;
wire activate_done = (activate_counter == 3'd0);
always @(posedge sys_clk) begin
if(reload_activate_counter)
activate_counter <= tim_rcd;
else if(~activate_done)
activate_counter <= activate_counter - 3'd1;
end
/* The number of clocks we have left before we must refresh one row in the SDRAM array (usually tREFI). */
reg [10:0] refresh_counter;
reg reload_refresh_counter;
wire must_refresh = refresh_counter == 11'd0;
always @(posedge sys_clk) begin
if(sdram_rst)
refresh_counter <= 11'd0;
else begin
if(reload_refresh_counter)
refresh_counter <= tim_refi;
else if(~must_refresh)
refresh_counter <= refresh_counter - 11'd1;
end
end
/* The number of clocks we must wait following an AUTO REFRESH command (usually tRFC). */
reg [3:0] autorefresh_counter;
reg reload_autorefresh_counter;
wire autorefresh_done = (autorefresh_counter == 4'd0);
always @(posedge sys_clk) begin
if(reload_autorefresh_counter)
autorefresh_counter <= tim_rfc;
else if(~autorefresh_done)
autorefresh_counter <= autorefresh_counter - 4'd1;
end
/* FSM that pushes commands into the SDRAM */
reg [3:0] state;
reg [3:0] next_state;
parameter IDLE = 4'd0;
parameter ACTIVATE = 4'd1;
parameter READ = 4'd2;
parameter WRITE = 4'd3;
parameter PRECHARGEALL = 4'd4;
parameter AUTOREFRESH = 4'd5;
parameter AUTOREFRESH_WAIT = 4'd6;
always @(posedge sys_clk) begin
if(sdram_rst)
state <= IDLE;
else begin
//$display("state: %d -> %d", state, next_state);
state <= next_state;
end
end
always @(*) begin
next_state = state;
reload_precharge_counter = 1'b0;
reload_activate_counter = 1'b0;
reload_refresh_counter = 1'b0;
reload_autorefresh_counter = 1'b0;
sdram_cs = 1'b0;
sdram_we = 1'b0;
sdram_cas = 1'b0;
sdram_ras = 1'b0;
sdram_adr_loadrow = 1'b0;
sdram_adr_loadcol = 1'b0;
sdram_adr_loadA10 = 1'b0;
track_close = 4'b0000;
track_open = 4'b0000;
read = 1'b0;
write = 1'b0;
ack = 1'b0;
case(state)
IDLE: begin
if(must_refresh)
next_state = PRECHARGEALL;
else begin
if(stb) begin
if(page_hit) begin
if(we) begin
if(write_safe) begin
/* Write */
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b1;
sdram_adr_loadcol = 1'b1;
write = 1'b1;
ack = 1'b1;
end
end else begin
if(read_safe) begin
/* Read */
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b0;
sdram_adr_loadcol = 1'b1;
read = 1'b1;
ack = 1'b1;
end
end
end else begin
if(bank_open) begin
if(current_precharge_safe) begin
/* Precharge Bank */
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b1;
track_close = bank_address_onehot;
reload_precharge_counter = 1'b1;
next_state = ACTIVATE;
end
end else begin
/* Activate */
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b0;
sdram_adr_loadrow = 1'b1;
track_open = bank_address_onehot;
reload_activate_counter = 1'b1;
if(we)
next_state = WRITE;
else
next_state = READ;
end
end
end
end
end
ACTIVATE: begin
if(precharge_done) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b0;
sdram_adr_loadrow = 1'b1;
track_open = bank_address_onehot;
reload_activate_counter = 1'b1;
if(we)
next_state = WRITE;
else
next_state = READ;
end
end
READ: begin
if(activate_done) begin
if(read_safe) begin
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b0;
sdram_adr_loadcol = 1'b1;
read = 1'b1;
ack = 1'b1;
next_state = IDLE;
end
end
end
WRITE: begin
if(activate_done) begin
if(write_safe) begin
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b1;
sdram_adr_loadcol = 1'b1;
write = 1'b1;
ack = 1'b1;
next_state = IDLE;
end
end
end
PRECHARGEALL: begin
if(precharge_safe == 4'b1111) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b1;
sdram_adr_loadA10 = 1'b1;
reload_precharge_counter = 1'b1;
track_close = 4'b1111;
next_state = AUTOREFRESH;
end
end
AUTOREFRESH: begin
if(precharge_done) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b1;
sdram_we = 1'b0;
reload_refresh_counter = 1'b1;
reload_autorefresh_counter = 1'b1;
next_state = AUTOREFRESH_WAIT;
end
end
AUTOREFRESH_WAIT: begin
if(autorefresh_done)
next_state = IDLE;
end
endcase
end
endmodule

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/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_ddrio(
input sys_clk,
input sys_clk_n,
input dqs_clk,
input dqs_clk_n,
input direction,
input direction_r,
input [7:0] mo,
input [63:0] do,
output [63:0] di,
output [3:0] sdram_dm,
inout [31:0] sdram_dq,
inout [3:0] sdram_dqs,
input idelay_rst,
input idelay_ce,
input idelay_inc
);
/******/
/* DQ */
/******/
wire [31:0] sdram_dq_t;
wire [31:0] sdram_dq_out;
wire [31:0] sdram_dq_in;
hpdmc_iobuf32 iobuf_dq(
.T(sdram_dq_t),
.I(sdram_dq_out),
.O(sdram_dq_in),
.IO(sdram_dq)
);
hpdmc_oddr32 oddr_dq_t(
.Q(sdram_dq_t),
.C0(sys_clk),
.C1(sys_clk_n),
.CE(1'b1),
.D0({32{~direction_r}}),
.D1({32{~direction_r}}),
.R(1'b0),
.S(1'b0)
);
hpdmc_oddr32 oddr_dq(
.Q(sdram_dq_out),
.C0(sys_clk),
.C1(sys_clk_n),
.CE(1'b1),
.D0(do[63:32]),
.D1(do[31:0]),
.R(1'b0),
.S(1'b0)
);
hpdmc_iddr32 iddr_dq(
.Q0(di[31:0]),
.Q1(di[63:32]),
.C0(sys_clk),
.C1(sys_clk_n),
.CE(1'b1),
.D(sdram_dq_in),
.R(1'b0),
.S(1'b0)
);
/*******/
/* DM */
/*******/
hpdmc_oddr4 oddr_dm(
.Q(sdram_dm),
.C0(sys_clk),
.C1(sys_clk_n),
.CE(1'b1),
.D0(mo[7:4]),
.D1(mo[3:0]),
.R(1'b0),
.S(1'b0)
);
/*******/
/* DQS */
/*******/
wire [3:0] sdram_dqs_t;
wire [3:0] sdram_dqs_out;
hpdmc_obuft4 obuft_dqs(
.T(sdram_dqs_t),
.I(sdram_dqs_out),
.O(sdram_dqs)
);
hpdmc_oddr4 oddr_dqs_t(
.Q(sdram_dqs_t),
.C0(dqs_clk),
.C1(dqs_clk_n),
.CE(1'b1),
.D0({4{~direction_r}}),
.D1({4{~direction_r}}),
.R(1'b0),
.S(1'b0)
);
hpdmc_oddr4 oddr_dqs(
.Q(sdram_dqs_out),
.C0(dqs_clk),
.C1(dqs_clk_n),
.CE(1'b1),
.D0(4'hf),
.D1(4'h0),
.R(1'b0),
.S(1'b0)
);
endmodule

522
demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_iddr32.v Normal file
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@ -0,0 +1,522 @@
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_iddr32 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT_Q0 = 1'b0,
parameter INIT_Q1 = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [31:0] Q0,
output [31:0] Q1,
input C0,
input C1,
input CE,
input [31:0] D,
input R,
input S
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr0 (
.Q0(Q0[0]),
.Q1(Q1[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[0]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr1 (
.Q0(Q0[1]),
.Q1(Q1[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[1]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr2 (
.Q0(Q0[2]),
.Q1(Q1[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[2]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr3 (
.Q0(Q0[3]),
.Q1(Q1[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[3]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr4 (
.Q0(Q0[4]),
.Q1(Q1[4]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[4]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr5 (
.Q0(Q0[5]),
.Q1(Q1[5]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[5]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr6 (
.Q0(Q0[6]),
.Q1(Q1[6]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[6]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr7 (
.Q0(Q0[7]),
.Q1(Q1[7]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[7]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr8 (
.Q0(Q0[8]),
.Q1(Q1[8]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[8]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr9 (
.Q0(Q0[9]),
.Q1(Q1[9]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[9]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr10 (
.Q0(Q0[10]),
.Q1(Q1[10]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[10]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr11 (
.Q0(Q0[11]),
.Q1(Q1[11]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[11]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr12 (
.Q0(Q0[12]),
.Q1(Q1[12]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[12]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr13 (
.Q0(Q0[13]),
.Q1(Q1[13]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[13]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr14 (
.Q0(Q0[14]),
.Q1(Q1[14]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[14]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr15 (
.Q0(Q0[15]),
.Q1(Q1[15]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[15]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr16 (
.Q0(Q0[16]),
.Q1(Q1[16]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[16]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr17 (
.Q0(Q0[17]),
.Q1(Q1[17]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[17]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr18 (
.Q0(Q0[18]),
.Q1(Q1[18]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[18]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr19 (
.Q0(Q0[19]),
.Q1(Q1[19]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[19]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr20 (
.Q0(Q0[20]),
.Q1(Q1[20]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[20]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr21 (
.Q0(Q0[21]),
.Q1(Q1[21]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[21]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr22 (
.Q0(Q0[22]),
.Q1(Q1[22]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[22]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr23 (
.Q0(Q0[23]),
.Q1(Q1[23]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[23]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr24 (
.Q0(Q0[24]),
.Q1(Q1[24]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[24]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr25 (
.Q0(Q0[25]),
.Q1(Q1[25]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[25]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr26 (
.Q0(Q0[26]),
.Q1(Q1[26]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[26]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr27 (
.Q0(Q0[27]),
.Q1(Q1[27]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[27]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr28 (
.Q0(Q0[28]),
.Q1(Q1[28]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[28]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr29 (
.Q0(Q0[29]),
.Q1(Q1[29]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[29]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr30 (
.Q0(Q0[30]),
.Q1(Q1[30]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[30]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr31 (
.Q0(Q0[31]),
.Q1(Q1[31]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[31]),
.R(R),
.S(S)
);
endmodule

225
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@ -0,0 +1,225 @@
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_iobuf32(
input [31:0] T,
input [31:0] I,
output [31:0] O,
inout [31:0] IO
);
IOBUF iobuf0(
.T(T[0]),
.I(I[0]),
.O(O[0]),
.IO(IO[0])
);
IOBUF iobuf1(
.T(T[1]),
.I(I[1]),
.O(O[1]),
.IO(IO[1])
);
IOBUF iobuf2(
.T(T[2]),
.I(I[2]),
.O(O[2]),
.IO(IO[2])
);
IOBUF iobuf3(
.T(T[3]),
.I(I[3]),
.O(O[3]),
.IO(IO[3])
);
IOBUF iobuf4(
.T(T[4]),
.I(I[4]),
.O(O[4]),
.IO(IO[4])
);
IOBUF iobuf5(
.T(T[5]),
.I(I[5]),
.O(O[5]),
.IO(IO[5])
);
IOBUF iobuf6(
.T(T[6]),
.I(I[6]),
.O(O[6]),
.IO(IO[6])
);
IOBUF iobuf7(
.T(T[7]),
.I(I[7]),
.O(O[7]),
.IO(IO[7])
);
IOBUF iobuf8(
.T(T[8]),
.I(I[8]),
.O(O[8]),
.IO(IO[8])
);
IOBUF iobuf9(
.T(T[9]),
.I(I[9]),
.O(O[9]),
.IO(IO[9])
);
IOBUF iobuf10(
.T(T[10]),
.I(I[10]),
.O(O[10]),
.IO(IO[10])
);
IOBUF iobuf11(
.T(T[11]),
.I(I[11]),
.O(O[11]),
.IO(IO[11])
);
IOBUF iobuf12(
.T(T[12]),
.I(I[12]),
.O(O[12]),
.IO(IO[12])
);
IOBUF iobuf13(
.T(T[13]),
.I(I[13]),
.O(O[13]),
.IO(IO[13])
);
IOBUF iobuf14(
.T(T[14]),
.I(I[14]),
.O(O[14]),
.IO(IO[14])
);
IOBUF iobuf15(
.T(T[15]),
.I(I[15]),
.O(O[15]),
.IO(IO[15])
);
IOBUF iobuf16(
.T(T[16]),
.I(I[16]),
.O(O[16]),
.IO(IO[16])
);
IOBUF iobuf17(
.T(T[17]),
.I(I[17]),
.O(O[17]),
.IO(IO[17])
);
IOBUF iobuf18(
.T(T[18]),
.I(I[18]),
.O(O[18]),
.IO(IO[18])
);
IOBUF iobuf19(
.T(T[19]),
.I(I[19]),
.O(O[19]),
.IO(IO[19])
);
IOBUF iobuf20(
.T(T[20]),
.I(I[20]),
.O(O[20]),
.IO(IO[20])
);
IOBUF iobuf21(
.T(T[21]),
.I(I[21]),
.O(O[21]),
.IO(IO[21])
);
IOBUF iobuf22(
.T(T[22]),
.I(I[22]),
.O(O[22]),
.IO(IO[22])
);
IOBUF iobuf23(
.T(T[23]),
.I(I[23]),
.O(O[23]),
.IO(IO[23])
);
IOBUF iobuf24(
.T(T[24]),
.I(I[24]),
.O(O[24]),
.IO(IO[24])
);
IOBUF iobuf25(
.T(T[25]),
.I(I[25]),
.O(O[25]),
.IO(IO[25])
);
IOBUF iobuf26(
.T(T[26]),
.I(I[26]),
.O(O[26]),
.IO(IO[26])
);
IOBUF iobuf27(
.T(T[27]),
.I(I[27]),
.O(O[27]),
.IO(IO[27])
);
IOBUF iobuf28(
.T(T[28]),
.I(I[28]),
.O(O[28]),
.IO(IO[28])
);
IOBUF iobuf29(
.T(T[29]),
.I(I[29]),
.O(O[29]),
.IO(IO[29])
);
IOBUF iobuf30(
.T(T[30]),
.I(I[30]),
.O(O[30]),
.IO(IO[30])
);
IOBUF iobuf31(
.T(T[31]),
.I(I[31]),
.O(O[31]),
.IO(IO[31])
);
endmodule

52
demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_obuft4.v Normal file
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/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_obuft4(
input [3:0] T,
input [3:0] I,
output [3:0] O
);
OBUFT obuft0(
.T(T[0]),
.I(I[0]),
.O(O[0])
);
OBUFT obuft1(
.T(T[1]),
.I(I[1]),
.O(O[1])
);
OBUFT obuft2(
.T(T[2]),
.I(I[2]),
.O(O[2])
);
OBUFT obuft3(
.T(T[3]),
.I(I[3]),
.O(O[3])
);
endmodule

489
demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr32.v Normal file
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@ -0,0 +1,489 @@
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_oddr32 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [31:0] Q,
input C0,
input C1,
input CE,
input [31:0] D0,
input [31:0] D1,
input R,
input S
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr0 (
.Q(Q[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[0]),
.D1(D1[0]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr1 (
.Q(Q[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[1]),
.D1(D1[1]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr2 (
.Q(Q[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[2]),
.D1(D1[2]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr3 (
.Q(Q[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[3]),
.D1(D1[3]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr4 (
.Q(Q[4]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[4]),
.D1(D1[4]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr5 (
.Q(Q[5]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[5]),
.D1(D1[5]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr6 (
.Q(Q[6]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[6]),
.D1(D1[6]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr7 (
.Q(Q[7]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[7]),
.D1(D1[7]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr8 (
.Q(Q[8]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[8]),
.D1(D1[8]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr9 (
.Q(Q[9]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[9]),
.D1(D1[9]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr10 (
.Q(Q[10]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[10]),
.D1(D1[10]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr11 (
.Q(Q[11]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[11]),
.D1(D1[11]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr12 (
.Q(Q[12]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[12]),
.D1(D1[12]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr13 (
.Q(Q[13]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[13]),
.D1(D1[13]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr14 (
.Q(Q[14]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[14]),
.D1(D1[14]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr15 (
.Q(Q[15]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[15]),
.D1(D1[15]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr16 (
.Q(Q[16]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[16]),
.D1(D1[16]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr17 (
.Q(Q[17]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[17]),
.D1(D1[17]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr18 (
.Q(Q[18]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[18]),
.D1(D1[18]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr19 (
.Q(Q[19]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[19]),
.D1(D1[19]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr20 (
.Q(Q[20]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[20]),
.D1(D1[20]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr21 (
.Q(Q[21]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[21]),
.D1(D1[21]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr22 (
.Q(Q[22]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[22]),
.D1(D1[22]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr23 (
.Q(Q[23]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[23]),
.D1(D1[23]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr24 (
.Q(Q[24]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[24]),
.D1(D1[24]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr25 (
.Q(Q[25]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[25]),
.D1(D1[25]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr26 (
.Q(Q[26]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[26]),
.D1(D1[26]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr27 (
.Q(Q[27]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[27]),
.D1(D1[27]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr28 (
.Q(Q[28]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[28]),
.D1(D1[28]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr29 (
.Q(Q[29]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[29]),
.D1(D1[29]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr30 (
.Q(Q[30]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[30]),
.D1(D1[30]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr31 (
.Q(Q[31]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[31]),
.D1(D1[31]),
.R(R),
.S(S)
);
endmodule

97
demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr4.v Normal file
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@ -0,0 +1,97 @@
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_oddr4 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [3:0] Q,
input C0,
input C1,
input CE,
input [3:0] D0,
input [3:0] D1,
input R,
input S
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr0 (
.Q(Q[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[0]),
.D1(D1[0]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr1 (
.Q(Q[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[1]),
.D1(D1[1]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr2 (
.Q(Q[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[2]),
.D1(D1[2]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr3 (
.Q(Q[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[3]),
.D1(D1[3]),
.R(R),
.S(S)
);
endmodule

3
demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/Makefile.spartan6 Normal file
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@ -0,0 +1,3 @@
SOURCES_HPDMC=tb_hpdmc.v ddr.v oddr2.v iddr2.v obuft.v iobuf.v $(wildcard ../rtl/*.v) $(wildcard ../rtl/spartan6/*.v)
include common.mak

14
demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/common.mak Normal file
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@ -0,0 +1,14 @@
SOURCES_MODEL=tb_model.v ddr.v
all: hpdmc
model: $(SOURCES_MODEL)
cver $(SOURCES_MODEL)
hpdmc: $(SOURCES)
cver $(SOURCES_HPDMC)
clean:
rm -f verilog.log hpdmc.vcd
.PHONY: clean model hpdmc

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/****************************************************************************************
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
`define sg75E
`define x16
// Timing parameters based on Speed Grade 04/07
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg5B // Timing Parameters for -5B (CL = 3)
parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 10.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 70.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
parameter tRP = 15.0; // tRP ns Precharge command period
parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
`endif
`ifdef sg6T // Timing Parameters for -6T (CL = 2.5)
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
parameter tRP = 15.0; // tRP ns Precharge command period
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
`endif
`ifdef sg6 // Timing Parameters for -6 (CL = 2.5)
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
parameter tRP = 15.0; // tRP ns Precharge command period
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
`endif
`ifdef sg75E // Timing Parameters for -75E (CL = 2)
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
parameter tRP = 15.0; // tRP ns Precharge command period
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
`endif
`ifdef sg75Z // Timing Parameters for -75Z (CL = 2)
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time
parameter tRP = 20.0; // tRP ns Precharge command period
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
`endif
`ifdef sg75 // Timing Parameters for -75 (CL = 2.5)
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time
parameter tRP = 20.0; // tRP ns Precharge command period
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
`endif
// Size Parameters based on Part Width
`ifdef x4
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
`endif
`ifdef x8
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
`endif
`ifdef x16
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
`endif
parameter BA_BITS = 2; // Set this parmaeter to control how many Bank Address bits are used
parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
parameter no_halt = 0; // If set to 1, the model won't halt on command sequence/major errors
parameter DEBUG = 1; // Turn on DEBUG message
`define FULL_MEM

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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 05/29/07 revision
///////////////////////////////////////////////////////////////////////////////
module IDDR #(
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
parameter INIT_Q1 = 1'b0,
parameter INIT_Q2 = 1'b0,
parameter SRTYPE = "SYNC"
) (
output Q1,
output Q2,
input C,
input CE,
input D,
input R,
input S
);
reg q1_out = INIT_Q1, q2_out = INIT_Q2;
reg q1_out_int, q2_out_int;
reg q1_out_pipelined, q2_out_same_edge_int;
wire c_in;
wire ce_in;
wire d_in;
wire gsr_in;
wire r_in;
wire s_in;
buf buf_c(c_in, C);
buf buf_ce(ce_in, CE);
buf buf_d(d_in, D);
buf buf_q1(Q1, q1_out);
buf buf_q2(Q2, q2_out);
buf buf_r(r_in, R);
buf buf_s(s_in, S);
initial begin
if((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1);
$finish;
end
if((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q2);
$finish;
end
if((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
$finish;
end
if((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on IDDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end
always @(r_in, s_in) begin
if(r_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q1_out_int = 1'b0;
assign q1_out_pipelined = 1'b0;
assign q2_out_same_edge_int = 1'b0;
assign q2_out_int = 1'b0;
end else if(r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q1_out_int = 1'b1;
assign q1_out_pipelined = 1'b1;
assign q2_out_same_edge_int = 1'b1;
assign q2_out_int = 1'b1;
end else if((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end else if(r_in == 1'b0 && s_in == 1'b0) begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end
end
always @(posedge c_in) begin
if(r_in == 1'b1) begin
q1_out_int <= 1'b0;
q1_out_pipelined <= 1'b0;
q2_out_same_edge_int <= 1'b0;
end else if(r_in == 1'b0 && s_in == 1'b1) begin
q1_out_int <= 1'b1;
q1_out_pipelined <= 1'b1;
q2_out_same_edge_int <= 1'b1;
end else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
q1_out_int <= d_in;
q1_out_pipelined <= q1_out_int;
q2_out_same_edge_int <= q2_out_int;
end
end
always @(negedge c_in) begin
if(r_in == 1'b1)
q2_out_int <= 1'b0;
else if(r_in == 1'b0 && s_in == 1'b1)
q2_out_int <= 1'b1;
else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0)
q2_out_int <= d_in;
end
always @(c_in, q1_out_int, q2_out_int, q2_out_same_edge_int, q1_out_pipelined) begin
case(DDR_CLK_EDGE)
"OPPOSITE_EDGE" : begin
q1_out <= q1_out_int;
q2_out <= q2_out_int;
end
"SAME_EDGE" : begin
q1_out <= q1_out_int;
q2_out <= q2_out_same_edge_int;
end
"SAME_EDGE_PIPELINED" : begin
q1_out <= q1_out_pipelined;
q2_out <= q2_out_same_edge_int;
end
default: begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
$finish;
end
endcase
end
endmodule

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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 04/08/09 revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module IDDR2 (Q0, Q1, C0, C1, CE, D, R, S);
output Q0;
output Q1;
input C0;
input C1;
input CE;
input D;
input R;
input S;
parameter DDR_ALIGNMENT = "NONE";
parameter INIT_Q0 = 1'b0;
parameter INIT_Q1 = 1'b0;
parameter SRTYPE = "SYNC";
pullup P1 (CE);
pulldown P2 (R);
pulldown P3 (S);
reg q0_out, q1_out;
reg q0_out_int, q1_out_int;
reg q0_c0_out_int, q1_c0_out_int;
wire PC0, PC1;
buf buf_q0 (Q0, q0_out);
buf buf_q1 (Q1, q1_out);
initial begin
if ((INIT_Q0 != 1'b0) && (INIT_Q0 != 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q0);
$finish;
end
if ((INIT_Q1 != 1'b0) && (INIT_Q1 != 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1);
$finish;
end
if ((DDR_ALIGNMENT != "C1") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "NONE")) begin
$display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on IDDR2 instance %m is set to %s. Legal values for this attribute are C0, C1 or NONE.", DDR_ALIGNMENT);
$finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on IDDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end // initial begin
assign PC0 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C0 : C1;
assign PC1 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C1 : C0;
initial begin
assign q0_out_int = INIT_Q0;
assign q1_out_int = INIT_Q1;
assign q0_c0_out_int = INIT_Q0;
assign q1_c0_out_int = INIT_Q1;
end
always @(R or S) begin
deassign q0_out_int;
deassign q1_out_int;
deassign q0_c0_out_int;
deassign q1_c0_out_int;
if (SRTYPE == "ASYNC") begin
if (R == 1) begin
assign q0_out_int = 0;
assign q1_out_int = 0;
assign q0_c0_out_int = 0;
assign q1_c0_out_int = 0;
end
else if (R == 0 && S == 1) begin
assign q0_out_int = 1;
assign q1_out_int = 1;
end
end // if (SRTYPE == "ASYNC")
end // always @ (GSR or R or S)
always @(posedge PC0) begin
if (R == 1 && SRTYPE == "SYNC") begin
q0_out_int <= 0;
q0_c0_out_int <= 0;
q1_c0_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q0_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
q0_out_int <= D;
q0_c0_out_int <= q0_out_int;
q1_c0_out_int <= q1_out_int;
end
end // always @ (posedge PC0)
always @(posedge PC1) begin
if (R == 1 && SRTYPE == "SYNC") begin
q1_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q1_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
q1_out_int <= D;
end
end // always @ (posedge PC1)
always @(q0_out_int or q1_out_int or q1_c0_out_int or q0_c0_out_int) begin
case (DDR_ALIGNMENT)
"NONE" : begin
q0_out <= q0_out_int;
q1_out <= q1_out_int;
end
"C0" : begin
q0_out <= q0_out_int;
q1_out <= q1_c0_out_int;
end
"C1" : begin
q0_out <= q0_out_int;
q1_out <= q1_c0_out_int;
end
endcase // case(DDR_ALIGNMENT)
end // always @ (q0_out_int or q1_out_int or q1_c0_out_int or q0_c0_out_int)
specify
if (C0) (C0 => Q0) = (100, 100);
if (C0) (C0 => Q1) = (100, 100);
if (C1) (C1 => Q1) = (100, 100);
if (C1) (C1 => Q0) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // IDDR2

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/*
* Simplified IDELAY model.
* Only fixed delay type is implemented and assumed.
*/
`timescale 1ns / 1ps
module IDELAY #(
parameter IOBDELAY_TYPE = "DEFAULT",
parameter IOBDELAY_VALUE = 0
) (
input C,
input CE,
input I,
input INC,
input RST,
output reg O
);
always @(I)
# (IOBDELAY_VALUE*0.078) O = I;
endmodule

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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 04/22/09 revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module IOBUF (O, IO, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
inout IO;
input I, T;
bufif0 T1 (IO, I, T);
buf B1 (O, IO);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
$finish;
end
endcase
end // initial begin
endmodule

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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 05/23/07 revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module OBUFT (O, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
input I, T;
bufif0 T1 (O, I, T);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFT instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
end
endmodule

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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 05/29/07 revision
///////////////////////////////////////////////////////////////////////////////
module ODDR #(
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
parameter INIT = 1'b0,
parameter SRTYPE = "SYNC"
) (
output Q,
input C,
input CE,
input D1,
input D2,
input R,
input S
);
reg q_out = INIT, qd2_posedge_int;
wire c_in;
wire ce_in;
wire d1_in;
wire d2_in;
wire gsr_in;
wire r_in;
wire s_in;
buf buf_c(c_in, C);
buf buf_ce(ce_in, CE);
buf buf_d1(d1_in, D1);
buf buf_d2(d2_in, D2);
buf buf_q(Q, q_out);
buf buf_r(r_in, R);
buf buf_s(s_in, S);
initial begin
if((INIT != 0) && (INIT != 1)) begin
$display("Attribute Syntax Error : The attribute INIT on ODDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT);
$finish;
end
if((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on ODDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", DDR_CLK_EDGE);
$finish;
end
if((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on ODDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end
always @(r_in, s_in) begin
if(r_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q_out = 1'b0;
assign qd2_posedge_int = 1'b0;
end else if(r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q_out = 1'b1;
assign qd2_posedge_int = 1'b1;
end else if((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
deassign q_out;
deassign qd2_posedge_int;
end else if(r_in == 1'b0 && s_in == 1'b0) begin
deassign q_out;
deassign qd2_posedge_int;
end
end
always @(posedge c_in) begin
if(r_in == 1'b1) begin
q_out <= 1'b0;
qd2_posedge_int <= 1'b0;
end else if(r_in == 1'b0 && s_in == 1'b1) begin
q_out <= 1'b1;
qd2_posedge_int <= 1'b1;
end else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
q_out <= d1_in;
qd2_posedge_int <= d2_in;
end
end
always @(negedge c_in) begin
if(r_in == 1'b1)
q_out <= 1'b0;
else if(r_in == 1'b0 && s_in == 1'b1)
q_out <= 1'b1;
else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
if(DDR_CLK_EDGE == "SAME_EDGE")
q_out <= qd2_posedge_int;
else if(DDR_CLK_EDGE == "OPPOSITE_EDGE")
q_out <= d2_in;
end
end
endmodule

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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 01/12/09 revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module ODDR2 (Q, C0, C1, CE, D0, D1, R, S);
output Q;
input C0;
input C1;
input CE;
input D0;
input D1;
input R;
input S;
parameter DDR_ALIGNMENT = "NONE";
parameter INIT = 1'b0;
parameter SRTYPE = "SYNC";
pullup P1 (CE);
pulldown P2 (R);
pulldown P3 (S);
reg q_out, q_d1_c0_out_int;
wire PC0, PC1;
buf buf_q (Q, q_out);
initial begin
if ((INIT != 1'b0) && (INIT != 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT on ODDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT);
$finish;
end
if ((DDR_ALIGNMENT != "NONE") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "C1")) begin
$display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on ODDR2 instance %m is set to %s. Legal values for this attribute are NONE, C0 or C1.", DDR_ALIGNMENT);
$finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on ODDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end // initial begin
initial begin
assign q_out = INIT;
assign q_d1_c0_out_int = INIT;
end
always @(R or S) begin
deassign q_out;
deassign q_d1_c0_out_int;
if (SRTYPE == "ASYNC") begin
if (R == 1) begin
assign q_out = 0;
assign q_d1_c0_out_int = 0;
end
else if (R == 0 && S == 1) begin
assign q_out = 1;
assign q_d1_c0_out_int = 1;
end
end // if (SRTYPE == "ASYNC")
end // always @ (GSR or R or S)
assign PC0 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C0 : C1;
assign PC1 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C1 : C0;
always @(posedge PC0) begin
if (R == 1 && SRTYPE == "SYNC") begin
q_out <= 0;
q_d1_c0_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q_out <= 1;
q_d1_c0_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
q_out <= D0;
q_d1_c0_out_int <= D1 ;
end // if (CE == 1 && R == 0 && S == 0)
end // always @ (posedge C0)
always @(posedge PC1) begin
if (R == 1 && SRTYPE == "SYNC") begin
q_out <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q_out <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
if (DDR_ALIGNMENT == "NONE")
q_out <= D1;
else
q_out <= q_d1_c0_out_int;
end // if (CE == 1 && R == 0 && S == 0)
end // always @ (negedge c_in)
specify
if (C0) (C0 => Q) = (100, 100);
if (C1) (C1 => Q) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // ODDR2

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initial begin : test
cke <= 1'b0;
cs_n <= 1'b1;
ras_n <= 1'b1;
cas_n <= 1'b1;
we_n <= 1'b1;
ba <= {BA_BITS{1'bz}};
a <= {ADDR_BITS{1'bz}};
dq_en <= 1'b0;
dqs_en <= 1'b0;
cke <= 1'b1;
power_up;
$display("Powerup complete");
precharge('h00000000, 1);
nop(trp);
load_mode('h1, 'h00002000);
nop(tmrd-1);
load_mode('h0, 'h0000013A);
nop(tmrd-1);
precharge('h00000000, 1);
nop(trp);
refresh;
nop(trfc);
refresh;
nop(trfc);
load_mode('h0, 'h0000003A);
nop(tmrd-1);
nop('h000000C8);
activate('h00000000, 'h00000000);
nop(trcd-1);
write('h00000000, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30003000, 32'h20002000, 32'h10001000, 32'h0});
nop(BL/2+twr);
activate('h00000001, 'h00000000);
nop(trcd-1);
write('h00000001, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30013001, 32'h20012001, 32'h10011001, 32'h10001});
nop(BL/2+twr);
activate('h00000002, 'h00000000);
nop(trcd-1);
write('h00000002, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30023002, 32'h20022002, 32'h10021002, 32'h20002});
nop(BL/2+twr);
activate('h00000003, 'h00000000);
nop(trcd-1);
write('h00000003, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30033003, 32'h20032003, 32'h10031003, 32'h30003});
nop(BL/2+twr);
activate('h00000000, 'h00000000);
nop(trrd-1);
activate('h00000001, 'h00000000);
nop(trrd-1);
activate('h00000002, 'h00000000);
nop(trrd-1);
activate('h00000003, 'h00000000);
read('h00000000, 'h00000000, 1);
nop(BL/2-1);
read('h00000001, 'h00000000, 1);
nop(BL/2-1);
read('h00000002, 'h00000000, 1);
nop(BL/2-1);
read('h00000003, 'h00000000, 1);
nop(BL/2+twr-2);
activate('h00000001, 'h00000000);
nop(trrd-1);
activate('h00000000, 'h00000000);
nop(trcd-1);
$display("%m At time %t: WRITE Burst", $time);write('h00000000, 'h00000004, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30403040, 32'h20402040, 32'h10401040, 32'h400040});
nop(BL/2+4);
$display("%m At time %t: Consecutive WRITE to WRITE", $time);write('h00000000, 'h00000008, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30803080, 32'h20802080, 32'h10801080, 32'h800080});
nop(BL/2-1);
write('h00000000, 'h0000000C, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h31203120, 32'h21202120, 32'h11201120, 32'h1200120});
nop(BL/2-1);
$display("%m At time %t: Nonconsecutive WRITE to WRITE", $time);write('h00000000, 'h00000010, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h31603160, 32'h21602160, 32'h11601160, 32'h1600160});
nop(BL/2+4);
write('h00000000, 'h00000014, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h32003200, 32'h22002200, 32'h12001200, 32'h2000200});
nop(BL/2+twr+4);
$display("%m At time %t: Random WRITE Cycles", $time);write('h00000000, 'h00000018, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h32403240, 32'h22402240, 32'h12401240, 32'h2400240});
nop(BL/2-1);
write('h00000000, 'h0000001C, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h32803280, 32'h22802280, 32'h12801280, 32'h2800280});
nop(BL/2-1);
write('h00000000, 'h00000020, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h33203320, 32'h23202320, 32'h13201320, 32'h3200320});
nop(BL/2-1);
write('h00000000, 'h00000024, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h33603360, 32'h23602360, 32'h13601360, 32'h3600360});
nop(BL/2-1);
$display("%m At time %t: WRITE to READ - Uninterrupting", $time);write('h00000000, 'h00000028, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h34003400, 32'h24002400, 32'h14001400, 32'h4000400});
nop(BL/2+1);
read('h00000000, 'h00000028, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Interrupting", $time);write('h00000000, 'h0000002C, 0, { 4'h1, 4'h1, 4'h0, 4'h0}, { 32'h34403440, 32'h24402440, 32'h14401440, 32'h4400440});
nop(BL/2+1);
read('h00000000, 'h0000002C, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Odd Number of Data, Interrupting", $time);write('h00000000, 'h00000030, 0, { 4'h1, 4'h1, 4'h1, 4'h0}, { 32'h34803480, 32'h24802480, 32'h14801480, 32'h4800480});
nop(BL/2+1);
read('h00000000, 'h00000030, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to PRECHARGE - Uninterrupting", $time);write('h00000000, 'h00000034, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h35203520, 32'h25202520, 32'h15201520, 32'h5200520});
nop(BL/2+twr);
precharge('h00000000, 0);
nop(trp-1);
$display("%m At time %t: WRITE with AUTO PRECHARGE", $time);activate('h00000000, 'h00000000);
nop(trcd-1);
write('h00000000, 'h00000040, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h36603660, 32'h26602660, 32'h16601660, 32'h6600660});
nop(BL/2+twr+trp);
activate('h00000000, 'h00000000);
nop(trcd-1);
$display("%m At time %t: READ Burst", $time);read('h00000000, 'h00000000, 0);
nop(BL/2-1);
$display("%m At time %t: Consecutive READ Bursts", $time);read('h00000000, 'h00000004, 0);
nop(BL/2-2);
read('h00000000, 'h00000008, 0);
nop(BL/2-1);
$display("%m At time %t: Nonconsecutive READ Bursts", $time);read('h00000000, 'h0000000C, 0);
nop(BL/2);
read('h00000000, 'h00000010, 0);
nop(BL/2);
$display("%m At time %t: Random READ Accesses", $time);read('h00000000, 'h00000014, 0);
read('h00000000, 'h00000018, 0);
read('h00000000, 'h0000001C, 0);
read('h00000000, 'h00000020, 0);
nop(BL/2);
$display("%m At time %t: Terminating a READ Burst", $time);read('h00000000, 'h00000024, 0);
burst_term;
nop(BL/2-2);
$display("%m At time %t: READ to WRITE", $time);read('h00000000, 'h00000028, 0);
burst_term;
nop(CL);
write('h00000000, 'h0000002C, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h34C034C0, 32'h24C024C0, 32'h14C014C0, 32'h4C004C0});
nop(BL/2+1);
$display("%m At time %t: READ to PRECHARGE", $time);read('h00000000, 'h00000030, 0);
nop('h00000001);
precharge('h00000000, 0);
nop(trp-1);
$display("%m At time %t: READ with AUTO PRECHARGE", $time);activate('h00000000, 'h00000000);
nop(trcd-1);
read('h00000000, 'h00000034, 1);
nop(CL+BL/2+twr);
$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 0", $time);activate('h00000000, 'h00000000);
nop(trcd-1);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h1}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 0", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h2}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 0", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h4}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 0", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h8}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h1, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h2, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h4, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h8, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h1, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h2, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h4, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h0, 4'h8, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h1, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h2, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h4, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 0);
nop(CL+BL/2-1);
$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF});
nop(BL/2);
write('h00000000, 'h00000064, 0, { 4'h8, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0});
nop(BL/2+1);
read('h00000000, 'h00000064, 1);
nop(CL+BL/2-1);
test_done = 1;
end

390
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/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
//`define ENABLE_VCD
`define TEST_SOMETRANSFERS
//`define TEST_RANDOMTRANSFERS
module tb_hpdmc();
/* 100MHz system clock */
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
/* DQS clock is phased out by 90 degrees, resulting in 2.5ns delay */
reg dqs_clk;
always @(clk) #2.5 dqs_clk = clk;
wire sdram_cke;
wire sdram_cs_n;
wire sdram_we_n;
wire sdram_cas_n;
wire sdram_ras_n;
wire [3:0] sdram_dm;
wire [12:0] sdram_adr;
wire [1:0] sdram_ba;
wire [31:0] sdram_dq;
wire [3:0] sdram_dqs;
ddr sdram1(
.Addr(sdram_adr),
.Ba(sdram_ba),
.Clk(clk),
.Clk_n(~clk),
.Cke(sdram_cke),
.Cs_n(sdram_cs_n),
.Ras_n(sdram_ras_n),
.Cas_n(sdram_cas_n),
.We_n(sdram_we_n),
.Dm(sdram_dm[3:2]),
.Dqs(sdram_dqs[3:2]),
.Dq(sdram_dq[31:16])
);
ddr sdram0(
.Addr(sdram_adr),
.Ba(sdram_ba),
.Clk(clk),
.Clk_n(~clk),
.Cke(sdram_cke),
.Cs_n(sdram_cs_n),
.Ras_n(sdram_ras_n),
.Cas_n(sdram_cas_n),
.We_n(sdram_we_n),
.Dm(sdram_dm[1:0]),
.Dqs(sdram_dqs[1:0]),
.Dq(sdram_dq[15:0])
);
reg rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
reg [25:0] fml_adr;
reg fml_stb;
reg fml_we;
wire fml_ack;
reg [7:0] fml_sel;
reg [63:0] fml_di;
wire [63:0] fml_do;
hpdmc dut(
.sys_clk(clk),
.sys_clk_n(~clk),
.dqs_clk(dqs_clk),
.dqs_clk_n(~dqs_clk),
.sys_rst(rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_di(fml_di),
.fml_do(fml_do),
.sdram_cke(sdram_cke),
.sdram_cs_n(sdram_cs_n),
.sdram_we_n(sdram_we_n),
.sdram_cas_n(sdram_cas_n),
.sdram_ras_n(sdram_ras_n),
.sdram_dm(sdram_dm),
.sdram_adr(sdram_adr),
.sdram_ba(sdram_ba),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs),
.dqs_psen(),
.dqs_psincdec(),
.dqs_psdone(1'b1)
);
task waitclock;
begin
@(posedge clk);
#1;
end
endtask
task waitnclock;
input [15:0] n;
integer i;
begin
for(i=0;i<n;i=i+1)
waitclock;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("Configuration Write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("Configuration Read : %x=%x", address, csr_do);
end
endtask
real reads;
real read_clocks;
task readburst;
input [31:0] address;
integer i;
begin
$display("READ [%x]", address);
fml_adr = address;
fml_stb = 1'b1;
fml_we = 1'b0;
i = 0;
while(~fml_ack) begin
i = i+1;
waitclock;
end
$display("%t: Memory Read : %x=%x acked in %d clocks", $time, address, fml_do, i);
fml_stb = 1'b0;
reads = reads + 1;
read_clocks = read_clocks + i;
for(i=0;i<3;i=i+1) begin
waitclock;
$display("%t: (R burst continuing) %x", $time, fml_do);
end
waitclock;
end
endtask
real writes;
real write_clocks;
task writeburst;
input [31:0] address;
integer i;
begin
$display("WRITE [%x]", address);
fml_adr = address;
fml_stb = 1'b1;
fml_we = 1'b1;
fml_sel = 8'hff;
fml_di = {$random, $random};
i = 0;
while(~fml_ack) begin
i = i+1;
waitclock;
end
$display("%t: Memory Write : %x=%x acked in %d clocks", $time, address, fml_di, i);
fml_stb = 1'b0;
writes = writes + 1;
write_clocks = write_clocks + i;
for(i=0;i<3;i=i+1) begin
waitclock;
fml_di = {$random, $random};
$display("%t: (W burst continuing) %x", $time, fml_di);
end
waitclock;
end
endtask
integer n, addr;
always begin
`ifdef ENABLE_VCD
$dumpfile("hpdmc.vcd");
`endif
/* Reset / Initialize our logic */
rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
fml_adr = 26'd0;
fml_di = 64'd0;
fml_sel = 8'd0;
fml_stb = 1'b0;
fml_we = 1'b0;
waitclock;
rst = 1'b0;
waitclock;
/* SDRAM initialization sequence. */
/* The controller already comes up in Bypass mode with CKE disabled. */
/* Wait 200us */
#200000;
/* Bring CKE high */
csrwrite(32'h00, 32'h07);
/* Precharge All:
* CS=1
* WE=1
* CAS=0
* RAS=1
* A=A10
* BA=Don't Care
*/
csrwrite(32'h04, 32'b00_0010000000000_1011);
waitnclock(2);
/* Load Extended Mode Register:
* CS=1
* WE=1
* CAS=1
* RAS=1
* A=Value
* BA=01
*
* Extended mode register encoding :
* A12-A2 reserved, must be 0
* A1 weak drive strength
* A0 DLL disable
*/
csrwrite(32'h04, 32'b01_0000000000000_1111);
waitnclock(2);
/* Load Mode Register, DLL in Reset:
* CS=1
* WE=1
* CAS=1
* RAS=1
* A=Value
* BA=00
*
* Mode register encoding :
* A12-A7 = 000000 Normal operation w/o DLL reset
* 000010 Normal operation in DLL reset
* A6-A4 = 010 CL2
* A3 = 0 Sequential burst
* A2-A0 = 011 Burst length = 8
*/
csrwrite(32'h04, 32'b00__000010_010_0_011__1111);
waitnclock(200);
/* Precharge All */
csrwrite(32'h04, 32'b00_0010000000000_1011);
waitnclock(2);
/* Auto Refresh
* CS=1
* WE=0
* CAS=1
* RAS=1
* A=Don't Care
* BA=Don't Care
*/
csrwrite(32'h04, 32'b00_0000000000000_1101);
waitnclock(8);
/* Auto Refresh */
csrwrite(32'h04, 32'b00_0000000000000_1101);
waitnclock(8);
/* Load Mode Register, DLL enabled */
csrwrite(32'h04, 32'b00__000000_010_0_011__1111);
waitnclock(200);
/* SDRAM initialization completed */
`ifdef ENABLE_VCD
/* Now, we want to know what the controller will send to the SDRAM chips */
$dumpvars(0, dut);
`endif
/* Bring up the controller ! */
csrwrite(32'h00, 32'h04);
`ifdef TEST_SOMETRANSFERS
/*
* Try some transfers.
*/
writeburst(32'h00);
writeburst(32'h20);
//writeburst(32'h40);
readburst(32'h00);
readburst(32'h20);
/*readburst(32'h40);
writeburst(32'h40);
readburst(32'h40);*/
`endif
`ifdef TEST_RANDOMTRANSFERS
writes = 0;
write_clocks = 0;
reads = 0;
read_clocks = 0;
for(n=0;n<500;n=n+1) begin
addr = $random;
if($random > 32'h80000000) begin
writeburst(addr);
//writeburst(addr+32'h20);
//writeburst(addr+32'h40);
end else begin
readburst(addr);
//readburst(addr+32'h20);
//readburst(addr+32'h40);
end
end
$display("");
$display("=======================================================");
$display(" Tested: %.0f reads, %.0f writes ", reads, writes);
$display("=======================================================");
$display(" Average read latency: %f cycles", read_clocks/reads);
$display(" Average write latency: %f cycles", write_clocks/writes);
$display("=======================================================");
$display(" Average read bandwidth: %f MBit/s @ 100MHz", (4/(4+read_clocks/reads))*64*100);
$display(" Average write bandwidth: %f MBit/s @ 100MHz", (4/(4+write_clocks/writes))*64*100);
$display("=======================================================");
`endif
$finish;
end
endmodule

556
demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/tb_model.v Normal file
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@ -0,0 +1,556 @@
/****************************************************************************************
*
* File Name: tb.v
* Version: 5.7
* Model: BUS Functional
*
* Dependencies: ddr.v, ddr_parameters.v
*
* Description: Micron SDRAM DDR (Double Data Rate) test bench
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* --------------------------------------------------------------------------------
* 2.1 SPH 03/19/2002 - Second Release
* - Fix tWR and several incompatability
* between different simulators
* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks.
* - Added tDQSH and tDQSL timing checks.
* 3.1 CAH 05/28/2003 - update all models to release version 3.1
* (no changes to this model)
* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3
* 3.3 JMK 09/11/2003 - Added initialization sequence checks.
* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v"
* - Fixed tWTR check
* 4.1 JMK 01/14/2001 - Grouped specify parameters by speed grade
* - Fixed mem_sizes parameter
* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs
* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module
* - Changed Dq_buf size to [15:0]
* 5.0 JMK 06/16/2004 - Added read to write checking.
* - Added read with precharge truncation to write checking.
* - Added associative memory array to reduce memory consumption.
* - Added checking for required DQS edges during write.
* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write.
* - Fixed wdqs_valid window.
* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored.
* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate.
* - Added tRFC checking during Load Mode and Precharge.
* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences.
* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.
* JMK 02/11/2005 - Changed the display format for numbers to hex.
* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.
* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error.
* - Renamed parameters file with .vh extension.
* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb
* - Added x32 functionality
* 6.0 BAS 05/31/2007 - Added read_verify command
****************************************************************************************/
`timescale 1ns / 1ps
module tb;
`include "ddr_parameters.vh"
reg clk ;
reg clk_n ;
reg cke ;
reg cs_n ;
reg ras_n ;
reg cas_n ;
reg we_n ;
reg [BA_BITS - 1 : 0] ba ;
reg [ADDR_BITS - 1 : 0] a ;
reg dq_en ;
reg [DM_BITS - 1 : 0] dm_out ;
reg [DQ_BITS - 1 : 0] dq_out ;
reg [DM_BITS-1 : 0] dm_fifo [0 : 13];
reg [DQ_BITS-1 : 0] dq_fifo [0 : 13];
reg [DQ_BITS-1 : 0] dq_in_pos ;
reg [DQ_BITS-1 : 0] dq_in_neg ;
reg dqs_en ;
reg [DQS_BITS - 1 : 0] dqs_out ;
reg [12 : 0] mode_reg ; //Mode Register
reg [12 : 0] ext_mode_reg; //Extended Mode Register
wire BO = mode_reg[3]; //Burst Order
wire [7 : 0] BL = (1<<mode_reg[2:0]); //Burst Length
// XXX modification by lekernel - removed CL2.5 support which crashes free simulators
// can be rewritten to make it work, but as CL2.5 is not used by Milkymist I'm lazy :)
// was wire [2 : 0] CL = (mode_reg[6:4] == 3'b110) ? 2.5 : mode_reg[6:4]; //CAS Latency
wire [2 : 0] CL = mode_reg[6:4]; //CAS Latency
wire dqs_n_en = ~ext_mode_reg[10]; //dqs# Enable
wire [2 : 0] AL = ext_mode_reg[5:3]; //Additive Latency
wire [3 : 0] RL = CL ; //Read Latency
wire [3 : 0] WL = 1 ; //Write Latency
wire [DM_BITS - 1 : 0] dm = dq_en ? dm_out : {DM_BITS{1'bz}};
wire [DQ_BITS - 1 : 0] dq = dq_en ? dq_out : {DQ_BITS{1'bz}};
wire [DQS_BITS - 1 : 0] dqs = dqs_en ? dqs_out : {DQS_BITS{1'bz}};
wire [DQS_BITS - 1 : 0] dqs_n = (dqs_en & dqs_n_en) ? ~dqs_out : {DQS_BITS{1'bz}};
wire [DQS_BITS - 1 : 0] rdqs_n = {DM_BITS{1'bz}};
wire [15 : 0] dqs_in = dqs;
wire [63 : 0] dq_in = dq;
ddr sdramddr (
clk ,
clk_n ,
cke ,
cs_n ,
ras_n ,
cas_n ,
we_n ,
ba ,
a ,
dm ,
dq ,
dqs
);
// timing definition in tCK units
real tck ;
integer tmrd ;
integer trap ;
integer tras ;
integer trc ;
integer trfc ;
integer trcd ;
integer trp ;
integer trrd ;
integer twr ;
initial begin
`ifdef period
tck = `period ;
`else
tck = tCK;
`endif
tmrd = ciel(tMRD/tck);
trap = ciel(tRAP/tck);
tras = ciel(tRAS/tck);
trc = ciel(tRC/tck);
trfc = ciel(tRFC/tck);
trcd = ciel(tRCD/tck);
trp = ciel(tRP/tck);
trrd = ciel(tRRD/tck);
twr = ciel(tWR/tck);
end
initial clk <= 1'b1;
initial clk_n <= 1'b0;
always @(posedge clk) begin
clk <= #(tck/2) 1'b0;
clk_n <= #(tck/2) 1'b1;
clk <= #(tck) 1'b1;
clk_n <= #(tck) 1'b0;
end
function integer ciel;
input number;
real number;
if (number > $rtoi(number))
ciel = $rtoi(number) + 1;
else
ciel = number;
endfunction
task power_up;
begin
cke <= 1'b0;
repeat(10) @(negedge clk);
$display ("%m at time %t TB: A 200 us delay is required before CKE can be brought high.", $time);
@ (negedge clk) cke = 1'b1;
nop (400/tck+1);
end
endtask
task load_mode;
input [BA_BITS - 1 : 0] bank;
input [ADDR_BITS - 1 : 0] addr;
begin
case (bank)
0: mode_reg = addr;
1: ext_mode_reg = addr;
endcase
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b0;
cas_n = 1'b0;
we_n = 1'b0;
ba = bank;
a = addr;
@(negedge clk);
end
endtask
task refresh;
begin
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b0;
cas_n = 1'b0;
we_n = 1'b1;
@(negedge clk);
end
endtask
task burst_term;
integer i;
begin
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b1;
cas_n = 1'b1;
we_n = 1'b0;
@(negedge clk);
for (i=0; i<BL; i=i+1) begin
dm_fifo[2*RL + i] = {DM_BITS{1'bz}} ;
dq_fifo[2*RL + i] = {DQ_BITS{1'bz}} ;
end
end
endtask
task self_refresh;
input count;
integer count;
begin
cke = 1'b0;
cs_n = 1'b0;
ras_n = 1'b0;
cas_n = 1'b0;
we_n = 1'b1;
repeat(count) @(negedge clk);
end
endtask
task precharge;
input [BA_BITS - 1 : 0] bank;
input ap; //precharge all
begin
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b0;
cas_n = 1'b1;
we_n = 1'b0;
ba = bank;
a = (ap<<10);
@(negedge clk);
end
endtask
task activate;
input [BA_BITS - 1 : 0] bank;
input [ADDR_BITS - 1 : 0] row;
begin
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b0;
cas_n = 1'b1;
we_n = 1'b1;
ba = bank;
a = row;
@(negedge clk);
end
endtask
//write task supports burst lengths <= 16
task write;
input [BA_BITS - 1 : 0] bank;
input [COL_BITS - 1 : 0] col;
input ap; //Auto Precharge
input [16*DM_BITS - 1 : 0] dm;
input [16*DQ_BITS - 1 : 0] dq;
reg [ADDR_BITS - 1 : 0] atemp [1:0];
reg [DQ_BITS/DM_BITS - 1 : 0] dm_temp;
integer i,j;
begin
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b1;
cas_n = 1'b0;
we_n = 1'b0;
ba = bank;
atemp[0] = col & 10'h3ff; //ADDR[ 9: 0] = COL[ 9: 0]
atemp[1] = (col>>10)<<11; //ADDR[ N:11] = COL[ N:10]
a = atemp[0] | atemp[1] | (ap<<10);
for (i=0; i<=BL; i=i+1) begin
dqs_en <= #(WL*tck + i*tck/2) 1'b1;
if (i%2 === 0) begin
dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b0}};
end else begin
dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b1}};
end
dq_en <= #(WL*tck + i*tck/2 + tck/4) 1'b1;
for (j=0; j<DM_BITS; j=j+1) begin
dm_temp = dm>>((i*DM_BITS + j)*DQ_BITS/DM_BITS);
dm_out[j] <= #(WL*tck + i*tck/2 + tck/4) &dm_temp;
end
dq_out <= #(WL*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS;
case (i)
15: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[16*DM_BITS-1 : 15*DM_BITS];
14: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[15*DM_BITS-1 : 14*DM_BITS];
13: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[14*DM_BITS-1 : 13*DM_BITS];
12: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[13*DM_BITS-1 : 12*DM_BITS];
11: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[12*DM_BITS-1 : 11*DM_BITS];
10: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[11*DM_BITS-1 : 10*DM_BITS];
9: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[10*DM_BITS-1 : 9*DM_BITS];
8: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 9*DM_BITS-1 : 8*DM_BITS];
7: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 8*DM_BITS-1 : 7*DM_BITS];
6: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 7*DM_BITS-1 : 6*DM_BITS];
5: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 6*DM_BITS-1 : 5*DM_BITS];
4: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 5*DM_BITS-1 : 4*DM_BITS];
3: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 4*DM_BITS-1 : 3*DM_BITS];
2: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 3*DM_BITS-1 : 2*DM_BITS];
1: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 2*DM_BITS-1 : 1*DM_BITS];
0: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 1*DM_BITS-1 : 0*DM_BITS];
endcase
case (i)
15: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[16*DQ_BITS-1 : 15*DQ_BITS];
14: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[15*DQ_BITS-1 : 14*DQ_BITS];
13: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[14*DQ_BITS-1 : 13*DQ_BITS];
12: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[13*DQ_BITS-1 : 12*DQ_BITS];
11: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[12*DQ_BITS-1 : 11*DQ_BITS];
10: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[11*DQ_BITS-1 : 10*DQ_BITS];
9: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[10*DQ_BITS-1 : 9*DQ_BITS];
8: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 9*DQ_BITS-1 : 8*DQ_BITS];
7: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 8*DQ_BITS-1 : 7*DQ_BITS];
6: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 7*DQ_BITS-1 : 6*DQ_BITS];
5: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 6*DQ_BITS-1 : 5*DQ_BITS];
4: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 5*DQ_BITS-1 : 4*DQ_BITS];
3: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 4*DQ_BITS-1 : 3*DQ_BITS];
2: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 3*DQ_BITS-1 : 2*DQ_BITS];
1: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 2*DQ_BITS-1 : 1*DQ_BITS];
0: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 1*DQ_BITS-1 : 0*DQ_BITS];
endcase
dq_en <= #(WL*tck + i*tck/2 + tck/4) 1'b1;
end
dqs_en <= #(WL*tck + BL*tck/2 + tck/2) 1'b0;
dq_en <= #(WL*tck + BL*tck/2 + tck/4) 1'b0;
@(negedge clk);
end
endtask
task read;
input [BA_BITS - 1 : 0]bank;
input [COL_BITS - 1 : 0] col;
input ap; //Auto Precharge
reg [ADDR_BITS - 1 : 0] atemp [1:0];
begin
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b1;
cas_n = 1'b0;
we_n = 1'b1;
ba = bank;
atemp[0] = col & 10'h3ff; //ADDR[ 9: 0] = COL[ 9: 0]
atemp[1] = (col>>10)<<11; //ADDR[ N:11] = COL[ N:10]
a = atemp[0] | atemp[1] | (ap<<10);
@(negedge clk);
end
endtask
// read with data verification
task read_verify;
input [BA_BITS - 1 : 0] bank;
input [COL_BITS - 1 : 0] col;
input ap; //Auto Precharge
input [16*DM_BITS - 1 : 0] dm; //Expected Data Mask
input [16*DQ_BITS - 1 : 0] dq; //Expected Data
integer i;
reg [2:0] brst_col;
begin
read (bank, col, ap);
for (i=0; i<BL; i=i+1) begin
// perform burst ordering
brst_col = col ^ i;
if (!BO) begin
brst_col = col + i;
end
if (BL == 4) begin
brst_col[2] = 1'b0 ;
end else if (BL == 2) begin
brst_col[2:1] = 2'b00 ;
end
dm_fifo[2*RL + i] = dm >> (i*DM_BITS);
dq_fifo[2*RL + i] = dq >> (i*DQ_BITS);
end
end
endtask
task nop;
input count;
integer count;
begin
cke = 1'b1;
cs_n = 1'b0;
ras_n = 1'b1;
cas_n = 1'b1;
we_n = 1'b1;
repeat(count) @(negedge clk);
end
endtask
task deselect;
input count;
integer count;
begin
cke = 1'b1;
cs_n = 1'b1;
ras_n = 1'b1;
cas_n = 1'b1;
we_n = 1'b1;
repeat(count) @(negedge clk);
end
endtask
task power_down;
input count;
integer count;
begin
cke = 1'b0;
cs_n = 1'b1;
ras_n = 1'b1;
cas_n = 1'b1;
we_n = 1'b1;
repeat(count) @(negedge clk);
end
endtask
function [16*DQ_BITS - 1 : 0] sort_data;
input [16*DQ_BITS - 1 : 0] dq;
input [2:0] col;
integer i;
reg [2:0] brst_col;
reg [DQ_BITS - 1 :0] burst;
begin
sort_data = 0;
for (i=0; i<BL; i=i+1) begin
// perform burst ordering
brst_col = col ^ i;
if (!BO) begin
brst_col[1:0] = col + i;
end
burst = dq >> (brst_col*DQ_BITS);
sort_data = sort_data | burst<<(i*DQ_BITS);
end
end
endfunction
// receiver(s) for data_verify process
always @(dqs_in[0]) begin #(tDQSQ); dqs_receiver(0); end
always @(dqs_in[1]) begin #(tDQSQ); dqs_receiver(1); end
always @(dqs_in[2]) begin #(tDQSQ); dqs_receiver(2); end
always @(dqs_in[3]) begin #(tDQSQ); dqs_receiver(3); end
always @(dqs_in[4]) begin #(tDQSQ); dqs_receiver(4); end
always @(dqs_in[5]) begin #(tDQSQ); dqs_receiver(5); end
always @(dqs_in[6]) begin #(tDQSQ); dqs_receiver(6); end
always @(dqs_in[7]) begin #(tDQSQ); dqs_receiver(7); end
task dqs_receiver;
input i;
integer i;
begin
if (dqs_in[i]) begin
case (i)
0: dq_in_pos[ 7: 0] <= dq_in[ 7: 0];
1: dq_in_pos[15: 8] <= dq_in[15: 8];
/* 2: dq_in_pos[23:16] <= dq_in[23:16];
3: dq_in_pos[31:24] <= dq_in[31:24];
4: dq_in_pos[39:32] <= dq_in[39:32];
5: dq_in_pos[47:40] <= dq_in[47:40];
6: dq_in_pos[55:48] <= dq_in[55:48];
7: dq_in_pos[63:56] <= dq_in[63:56];*/
endcase
end else if (!dqs_in[i]) begin
case (i)
0: dq_in_neg[ 7: 0] <= dq_in[ 7: 0];
1: dq_in_neg[15: 8] <= dq_in[15: 8];
/* 2: dq_in_neg[23:16] <= dq_in[23:16];
3: dq_in_neg[31:24] <= dq_in[31:24];
4: dq_in_pos[39:32] <= dq_in[39:32];
5: dq_in_pos[47:40] <= dq_in[47:40];
6: dq_in_pos[55:48] <= dq_in[55:48];
7: dq_in_pos[63:56] <= dq_in[63:56];*/
endcase
end
end
endtask
// perform data verification as a result of read_verify task call
always @(clk) begin : data_verify
integer i;
reg [DM_BITS-1 : 0] data_mask;
reg [8*DM_BITS-1 : 0] bit_mask;
for (i=0; i<=14; i=i+1) begin
dm_fifo[i] = dm_fifo[i+1];
dq_fifo[i] = dq_fifo[i+1];
end
dm_fifo[13] = 'bz;
dq_fifo[13] = 'bz;
// dm_fifo[30] = 0;
// dq_fifo[30] = 0;
data_mask = dm_fifo[0];
data_mask = dm_fifo[0];
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = {bit_mask, {8{~data_mask[i]}}};
end
if (clk) begin
if ((dq_in_neg & bit_mask) != (dq_fifo[0] & bit_mask))
$display ("%m at time %t: ERROR: Read data miscompare: Expected = %h, Actual = %h, Mask = %h", $time, dq_fifo[0], dq_in_neg, bit_mask);
end else begin
if ((dq_in_pos & bit_mask) != (dq_fifo[0] & bit_mask))
$display ("%m at time %t: ERROR: Read data miscompare: Expected = %h, Actual = %h, Mask = %h", $time, dq_fifo[0], dq_in_pos, bit_mask);
end
end
reg test_done;
initial test_done = 0;
// End-of-test triggered in 'subtest.vh'
always @(test_done) begin : all_done
if (test_done == 1) begin
#5000
$display ("Simulation is Complete");
$stop(0);
$finish;
end
end
// Test included from external file
`include "subtest.vh"
endmodule

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demo_chip_rtl/rtl/lib_cells/IOBUF.v Executable file
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module IOBUF (
input I, T,
inout IO,
output O
);
PADBID U1 ( .I(I), .OEN(T), .PAD(IO), .C(O) );
endmodule

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module OBUFT (
input I, T,
output O
);
PAD U1 ( .IN_PORT(I), .SELECT(T), .INOUT_PORT(O), .OUT_PORT() );
endmodule

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module IDDR2 #(
parameter DDR_ALIGNMENT = "NONE",
parameter INIT_Q0 = 1'b0,
parameter INIT_Q1 = 1'b0,
parameter SRTYPE = "SYNC"
)
(Q0, Q1, C0, C1, CE, D, R, S);
output reg Q0;
output reg Q1;
input C0;
input C1;
input CE;
input D;
input R;
input S;
always @(posedge C0 or posedge R ) begin
if (R)
Q0 <= 1'b0;
else
if (CE)
Q0 <= D;
end
always @(posedge C1 or posedge R ) begin
if (R)
Q1 <= 1'b0;
else
if (CE)
Q1 <= D;
end
endmodule // IDDR2
module ODDR2 #(
parameter DDR_ALIGNMENT = "NONE",
parameter INIT = 1'b0,
parameter SRTYPE = "SYNC"
)(Q, C0, C1, CE, D0, D1, R, S);
output Q;
input C0;
input C1;
input CE;
input D0;
input D1;
input R;
input S;
wire data_0, data_1;
assign data_0 = ( C0 && CE ) ? D0 : 1'b0;
assign data_1 = ( C1 && CE ) ? D1 : 1'b0;
assign Q = data_0 || data_1;
endmodule // ODDR2

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demo_chip_rtl/rtl/lib_cells/ddr_pad_lib.v Executable file
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module IOBUF (
input I, T,
inout IO,
output O
);
PADBID U1 ( .I(I), .OEN(T), .PAD(IO), .C(O) );
endmodule
module OBUFT (
input I, T,
output O
);
PADBID U1 ( .I(I), .OEN(T), .PAD(IO), .C() );
endmodule

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demo_chip_rtl/rtl/mem_wrapper/MemGen_32_12.v Executable file
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module MemGen_32_12 (
chip_en,
clock,
addr,
rd_en,
rd_data,
wr_en,
wr_data
);
parameter data_width = 32;
parameter addr_width = 12;
parameter mem_depth = 4096;
input chip_en;
input clock;
input [addr_width-1:0] addr;
output [data_width-1:0] rd_data;
input rd_en;
input wr_en;
input [data_width-1:0] wr_data;
reg [data_width-1:0] rd_data;
reg [3:0] mem_sel ;
wire [31:0] mem_data_out [3:0];
always @(*)
begin
if ( chip_en == 1'b1 )
case (addr[11:10])
2'h0 : begin mem_sel = 4'b0001; rd_data = mem_data_out[0]; end
2'h1 : begin mem_sel = 4'b0010; rd_data = mem_data_out[1]; end
2'h2 : begin mem_sel = 4'b0100; rd_data = mem_data_out[2]; end
2'h3 : begin mem_sel = 4'b1000; rd_data = mem_data_out[3]; end
endcase
else
begin
mem_sel = 4'b0000;
rd_data = 32'h00000000;
end
end
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin
MemGen_16_10 U_lo (.chip_en(mem_sel[i]), .clock(clock), .addr(addr[9:0]), .rd_en(rd_en), .rd_data(mem_data_out[i][15:0]), .wr_en(wr_en), .wr_data(wr_data[15:0]) );
MemGen_16_10 U_hi (.chip_en(mem_sel[i]), .clock(clock), .addr(addr[9:0]), .rd_en(rd_en), .rd_data(mem_data_out[i][31:16]), .wr_en(wr_en), .wr_data(wr_data[31:16]) );
end
endgenerate
endmodule

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demo_chip_rtl/rtl/mem_wrapper/MemGen_32_14.v Executable file
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module MemGen_32_14 (
chip_en,
clock,
addr,
rd_en,
rd_data,
wr_en,
wr_data
);
parameter data_width = 32;
parameter addr_width = 14;
parameter mem_depth = 16384;
input chip_en;
input clock;
input [addr_width-1:0] addr;
output [data_width-1:0] rd_data;
input rd_en;
input wr_en;
input [data_width-1:0] wr_data;
reg [data_width-1:0] rd_data;
reg [15:0] mem_sel ;
wire [31:0] mem_data_out [15:0];
always @(*)
begin
if ( chip_en == 1'b1 )
case (addr[13:10])
4'h0 : begin mem_sel = 16'b0000000000000001; rd_data = mem_data_out[0]; end
4'h1 : begin mem_sel = 16'b0000000000000010; rd_data = mem_data_out[1]; end
4'h2 : begin mem_sel = 16'b0000000000000100; rd_data = mem_data_out[2]; end
4'h3 : begin mem_sel = 16'b0000000000001000; rd_data = mem_data_out[3]; end
4'h4 : begin mem_sel = 16'b0000000000010000; rd_data = mem_data_out[4]; end
4'h5 : begin mem_sel = 16'b0000000000100000; rd_data = mem_data_out[5]; end
4'h6 : begin mem_sel = 16'b0000000001000000; rd_data = mem_data_out[6]; end
4'h7 : begin mem_sel = 16'b0000000010000000; rd_data = mem_data_out[7]; end
4'h8 : begin mem_sel = 16'b0000000100000000; rd_data = mem_data_out[8]; end
4'h9 : begin mem_sel = 16'b0000001000000000; rd_data = mem_data_out[9]; end
4'hA : begin mem_sel = 16'b0000010000000000; rd_data = mem_data_out[10]; end
4'hB : begin mem_sel = 16'b0000100000000000; rd_data = mem_data_out[11]; end
4'hC : begin mem_sel = 16'b0001000000000000; rd_data = mem_data_out[12]; end
4'hD : begin mem_sel = 16'b0010000000000000; rd_data = mem_data_out[13]; end
4'hE : begin mem_sel = 16'b0100000000000000; rd_data = mem_data_out[14]; end
4'hF : begin mem_sel = 16'b1000000000000000; rd_data = mem_data_out[15]; end
endcase
else
begin
mem_sel = 4'b0000;
rd_data = 32'h00000000;
end
end
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin
MemGen_16_10 U_lo (.chip_en(mem_sel[i]), .clock(clock), .addr(addr[9:0]), .rd_en(rd_en), .rd_data(mem_data_out[i][15:0]), .wr_en(wr_en), .wr_data(wr_data[15:0]) );
MemGen_16_10 U_hi (.chip_en(mem_sel[i]), .clock(clock), .addr(addr[9:0]), .rd_en(rd_en), .rd_data(mem_data_out[i][31:16]), .wr_en(wr_en), .wr_data(wr_data[31:16]) );
end
endgenerate
endmodule

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NET AUDIO_BIT_CLK LOC="AF18"; # Bank 4, Vcco=3.3V, No DCI
NET AUDIO_SDATA_IN LOC="AE18"; # Bank 4, Vcco=3.3V, No DCI
NET AUDIO_SDATA_OUT LOC="AG16"; # Bank 4, Vcco=3.3V, No DCI
NET AUDIO_SYNC LOC="AF19"; # Bank 4, Vcco=3.3V, No DCI
NET BUS_ERROR_1 LOC="F6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET BUS_ERROR_2 LOC="T10"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET CFG_ADDR_OUT0 LOC="AE12"; # Bank 2, Vcco=3.3V
NET CFG_ADDR_OUT1 LOC="AE13"; # Bank 2, Vcco=3.3V
NET CLK_27MHZ_FPGA LOC="AG18"; # Bank 4, Vcco=3.3V, No DCI
NET CLK_33MHZ_FPGA LOC="AH17"; # Bank 4, Vcco=3.3V, No DCI
NET CLK_FPGA_N LOC="K19"; # Bank 3, Vcco=2.5V, No DCI
NET CLK_FPGA_P LOC="L19"; # Bank 3, Vcco=2.5V, No DCI
NET CLKBUF_Q0_N LOC="H3"; # Bank 116, MGTREFCLKN_116, GTP_DUAL_X0Y4
NET CLKBUF_Q0_P LOC="H4"; # Bank 116, MGTREFCLKP_116, GTP_DUAL_X0Y4
NET CLKBUF_Q1_N LOC="J19"; # Bank 3, Vcco=2.5V, No DCI
NET CLKBUF_Q1_P LOC="K18"; # Bank 3, Vcco=2.5V, No DCI
NET CPLD_IO_1 LOC="W10"; # Bank 18, Vcco=3.3V, No DCI
NET CPU_TCK LOC="E6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET CPU_TDO LOC="E7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET CPU_TMS LOC="U10"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET CPU_TRST LOC="V10"; # Bank 18, Vcco=3.3V, No DCI
NET DDR2_A0 LOC="L30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A1 LOC="M30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A2 LOC="N29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A3 LOC="P29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A4 LOC="K31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A5 LOC="L31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A6 LOC="P31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A7 LOC="P30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A8 LOC="M31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A9 LOC="R28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A10 LOC="J31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A11 LOC="R29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A12 LOC="T31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_A13 LOC="H29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_BA0 LOC="G31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_BA1 LOC="J30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_BA2 LOC="R31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_CAS_B LOC="E31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_CKE0 LOC="T28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_CKE1 LOC="U30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_CLK0_N LOC="AJ29"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_CLK0_P LOC="AK29"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_CLK1_N LOC="F28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_CLK1_P LOC="E28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_CS0_B LOC="L29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_CS1_B LOC="J29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D0 LOC="AF30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D1 LOC="AK31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D2 LOC="AF31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D3 LOC="AD30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D4 LOC="AJ30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D5 LOC="AF29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D6 LOC="AD29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D7 LOC="AE29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D8 LOC="AH27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D9 LOC="AF28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D10 LOC="AH28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D11 LOC="AA28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D12 LOC="AG25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D13 LOC="AJ26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D14 LOC="AG28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D15 LOC="AB28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D16 LOC="AC28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D17 LOC="AB25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D18 LOC="AC27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D19 LOC="AA26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D20 LOC="AB26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D21 LOC="AA24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D22 LOC="AB27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D23 LOC="AA25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D24 LOC="AC29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D25 LOC="AB30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D26 LOC="W31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D27 LOC="V30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D28 LOC="AC30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D29 LOC="W29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D30 LOC="V27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D31 LOC="W27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D32 LOC="V29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D33 LOC="Y27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D34 LOC="Y26"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D35 LOC="W24"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D36 LOC="V28"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D37 LOC="W25"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D38 LOC="W26"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D39 LOC="V24"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D40 LOC="R24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D41 LOC="P25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D42 LOC="N24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D43 LOC="P26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D44 LOC="T24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D45 LOC="N25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D46 LOC="P27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D47 LOC="N28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D48 LOC="M28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D49 LOC="L28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D50 LOC="F25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D51 LOC="H25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D52 LOC="K27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D53 LOC="K28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D54 LOC="H24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D55 LOC="G26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D56 LOC="G25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D57 LOC="M26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D58 LOC="J24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D59 LOC="L26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D60 LOC="J27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D61 LOC="M25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D62 LOC="L25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_D63 LOC="L24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DM0 LOC="AJ31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DM1 LOC="AE28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DM2 LOC="Y24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DM3 LOC="Y31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DM4 LOC="V25"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DM5 LOC="P24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DM6 LOC="F26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DM7 LOC="J25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS0_N LOC="AA30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS0_P LOC="AA29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS1_N LOC="AK27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS1_P LOC="AK28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS2_N LOC="AJ27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS2_P LOC="AK26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS3_N LOC="AA31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS3_P LOC="AB31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS4_N LOC="Y29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS4_P LOC="Y28"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS5_N LOC="E27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS5_P LOC="E26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS6_N LOC="G28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS6_P LOC="H28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS7_N LOC="H27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_DQS7_P LOC="G27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_ODT0 LOC="F31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_ODT1 LOC="F30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_RAS_B LOC="H30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_SCL LOC="E29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_SDA LOC="F29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DDR2_WE_B LOC="K29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DVI_D0 LOC="AB8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D1 LOC="AC8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D2 LOC="AN12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D3 LOC="AP12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D4 LOC="AA9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D5 LOC="AA8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D6 LOC="AM13"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D7 LOC="AN13"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D8 LOC="AA10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D9 LOC="AB10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D10 LOC="AP14"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_D11 LOC="AN14"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_DE LOC="AE8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_GPIO1 LOC="N30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET DVI_H LOC="AM12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_RESET_B LOC="AK6"; # Bank 18, Vcco=3.3V, No DCI
NET DVI_V LOC="AM11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_XCLK_N LOC="AL10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET DVI_XCLK_P LOC="AL11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET FAN_ALERT_B LOC="T30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET FLASH_ADV_B LOC="F13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET FLASH_AUDIO_RESET_B LOC="AG17"; # Bank 4, Vcco=3.3V, No DCI
NET FLASH_CE_B LOC="AE14"; # Bank 2, Vcco=3.3V
NET FLASH_CLK LOC="N9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET FLASH_OE_B LOC="AF14"; # Bank 2, Vcco=3.3V
NET FLASH_WAIT LOC="G13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET FPGA_AVDD LOC="T18"; # Bank 0, Vcco=3.3V
NET FPGA_CCLK-R LOC="N15"; # Bank 0, Vcco=3.3V
NET FPGA_CPU_RESET_B LOC="E9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET FPGA_CS_B LOC="N22"; # Bank 0, Vcco=3.3V
NET FPGA_CS0_B LOC="AF21"; # Bank 2, Vcco=3.3V
NET FPGA_DIFF_CLK_OUT_N LOC="J21"; # Bank 3, Vcco=2.5V, No DCI
NET FPGA_DIFF_CLK_OUT_P LOC="J20"; # Bank 3, Vcco=2.5V, No DCI
NET FPGA_DIN LOC="P15"; # Bank 0, Vcco=3.3V
NET FPGA_DONE LOC="M15"; # Bank 0, Vcco=3.3V
NET FPGA_DOUT_BUSY LOC="AD15"; # Bank 0, Vcco=3.3V
NET FPGA_DX_N LOC="W17"; # Bank 0, Vcco=3.3V
NET FPGA_DX_P LOC="W18"; # Bank 0, Vcco=3.3V
NET FPGA_EXP_TCK LOC="AB15"; # Bank 0, Vcco=3.3V
NET FPGA_EXP_TMS LOC="AC14"; # Bank 0, Vcco=3.3V
NET FPGA_HSWAPEN LOC="M23"; # Bank 0, Vcco=3.3V
NET FPGA_INIT_B LOC="N14"; # Bank 0, Vcco=3.3V
NET FPGA_M0 LOC="AD21"; # Bank 0, Vcco=3.3V
NET FPGA_M1 LOC="AC22"; # Bank 0, Vcco=3.3V
NET FPGA_M2 LOC="AD22"; # Bank 0, Vcco=3.3V
NET FPGA_PROG_B LOC="M22"; # Bank 0, Vcco=3.3V
NET FPGA_RDWR_B LOC="N23"; # Bank 0, Vcco=3.3V
NET FPGA_ROTARY_INCA LOC="AH30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET FPGA_ROTARY_INCB LOC="AG30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET FPGA_ROTARY_PUSH LOC="AH29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET FPGA_SERIAL1_RX LOC="AG15"; # Bank 4, Vcco=3.3V, No DCI
NET FPGA_SERIAL1_TX LOC="AG20"; # Bank 4, Vcco=3.3V, No DCI
NET FPGA_SERIAL2_RX LOC="G10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET FPGA_SERIAL2_TX LOC="F10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET FPGA_TDI LOC="AC15"; # Bank 0, Vcco=3.3V
NET FPGA_TDO LOC="AD14"; # Bank 0, Vcco=3.3V
NET FPGA_V_N LOC="V17"; # Bank 0, Vcco=3.3V (SYSMON External Input: VN) J9-10
NET FPGA_V_P LOC="U18"; # Bank 0, Vcco=3.3V (SYSMON External Input: VP) J9-9
NET FPGA_VBATT LOC="L23"; # Bank 0, Vcco=3.3V
NET FPGA_VREFP LOC="V18"; # Bank 0, Vcco=3.3V
NET FPGA_VRN_B11 LOC="N33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET FPGA_VRN_B13 LOC="AG33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET FPGA_VRN_B17 LOC="AD31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET FPGA_VRN_B19 LOC="N27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET FPGA_VRN_B20 LOC="L10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET FPGA_VRN_B21 LOC="AJ25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET FPGA_VRN_B22 LOC="AF8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET FPGA_VRP_B11 LOC="M33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET FPGA_VRP_B13 LOC="AH33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET FPGA_VRP_B17 LOC="AE31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET FPGA_VRP_B19 LOC="M27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET FPGA_VRP_B20 LOC="L11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET FPGA_VRP_B21 LOC="AH25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET FPGA_VRP_B22 LOC="AE9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET GPIO_DIP_SW1 LOC="U25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_DIP_SW2 LOC="AG27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_DIP_SW3 LOC="AF25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_DIP_SW4 LOC="AF26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_DIP_SW5 LOC="AE27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_DIP_SW6 LOC="AE26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_DIP_SW7 LOC="AC25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_DIP_SW8 LOC="AC24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_LED_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI
NET GPIO_LED_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI
NET GPIO_LED_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI
NET GPIO_LED_3 LOC="AD26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_LED_4 LOC="G16"; # Bank 3, Vcco=2.5V, No DCI
NET GPIO_LED_5 LOC="AD25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_LED_6 LOC="AD24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_LED_7 LOC="AE24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_LED_C LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET GPIO_LED_E LOC="AG23"; # Bank 2, Vcco=3.3V
NET GPIO_LED_N LOC="AF13"; # Bank 2, Vcco=3.3V
NET GPIO_LED_S LOC="AG12"; # Bank 2, Vcco=3.3V
NET GPIO_LED_W LOC="AF23"; # Bank 2, Vcco=3.3V
NET GPIO_SW_C LOC="AJ6"; # Bank 18, Vcco=3.3V, No DCI
NET GPIO_SW_E LOC="AK7"; # Bank 18, Vcco=3.3V, No DCI
NET GPIO_SW_N LOC="U8"; # Bank 18, Vcco=3.3V, No DCI
NET GPIO_SW_S LOC="V8"; # Bank 18, Vcco=3.3V, No DCI
NET GPIO_SW_W LOC="AJ7"; # Bank 18, Vcco=3.3V, No DCI
NET HDR1_2 LOC="H33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_4 LOC="F34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_6 LOC="H34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_8 LOC="G33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_10 LOC="G32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_12 LOC="H32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_14 LOC="J32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_16 LOC="J34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_18 LOC ="L33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_20 LOC="M32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_22 LOC="P34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_24 LOC="N34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_26 LOC="AA34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[5]) J6-26
NET HDR1_28 LOC="AD32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_30 LOC="Y34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[5]) J6-30
NET HDR1_32 LOC="Y32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_34 LOC="W32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_36 LOC="AH34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_38 LOC="AE32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_40 LOC="AG32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_42 LOC="AH32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_44 LOC="AK34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_46 LOC="AK33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_48 LOC="AJ32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_50 LOC="AK32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_52 LOC="AL34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_54 LOC="AL33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_56 LOC="AM33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_58 LOC="AJ34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_60 LOC="AM32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_62 LOC="AN34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR1_64 LOC="AN33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR2_2_SM_8_N LOC="K34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[15]) J4-2
NET HDR2_4_SM_8_P LOC="L34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[15]) J4-4
NET HDR2_6_SM_7_N LOC="K32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[14]) J4-6
NET HDR2_8_SM_7_P LOC="K33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[14]) J4-8
NET HDR2_10_DIFF_0_N LOC="N32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[13]) J4-10
NET HDR2_12_DIFF_0_P LOC="P32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[13]) J4-12
NET HDR2_14_DIFF_1_N LOC="R34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[12]) J4-14
NET HDR2_16_DIFF_1_P LOC="T33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[12]) J4-16
NET HDR2_18_DIFF_2_N LOC="R32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[11]) J4-18
NET HDR2_20_DIFF_2_P LOC="R33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[11]) J4-20
NET HDR2_22_SM_10_N LOC="T34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[10]) J4-22
NET HDR2_24_SM_10_P LOC="U33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[10]) J4-24
NET HDR2_26_SM_11_N LOC="U31"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[9]) J4-26
NET HDR2_28_SM_11_P LOC="U32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[9]) J4-28
NET HDR2_30_DIFF_3_N LOC="V33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[8]) J4-30
NET HDR2_32_DIFF_3_P LOC="V32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[8]) J4-32
NET HDR2_34_SM_15_N LOC="V34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[7]) J4-34
NET HDR2_36_SM_15_P LOC="W34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[7]) J4-36
NET HDR2_38_SM_6_N LOC="AA33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[6]) J4-38
NET HDR2_40_SM_6_P LOC="Y33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[6]) J4-40
NET HDR2_42_SM_14_N LOC="AE34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[0]) J4-42
NET HDR2_44_SM_14_P LOC="AF34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[0]) J4-44
NET HDR2_46_SM_12_N LOC="AE33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[1]) J4-46
NET HDR2_48_SM_12_P LOC="AF33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[1]) J4-48
NET HDR2_50_SM_5_N LOC="AD34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[4]) J4-50
NET HDR2_52_SM_5_P LOC="AC34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[4]) J4-52
NET HDR2_54_SM_13_N LOC="AB32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[3]) J4-54
NET HDR2_56_SM_13_P LOC="AC32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[3]) J4-56
NET HDR2_58_SM_4_N LOC="AB33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[2]) J4-58
NET HDR2_60_SM_4_P LOC="AC33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[2]) J4-60
NET HDR2_62_SM_9_N LOC="AP32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET HDR2_64_SM_9_P LOC="AN32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET IIC_SCL_MAIN LOC="F9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET IIC_SCL_SFP LOC="R26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET IIC_SCL_VIDEO LOC="U27"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET IIC_SDA_MAIN LOC="F8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET IIC_SDA_SFP LOC="U28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET IIC_SDA_VIDEO LOC="T29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET KEYBOARD_CLK LOC="T26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET KEYBOARD_DATA LOC="T25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET LCD_FPGA_DB4 LOC="T9"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET LCD_FPGA_DB5 LOC="G7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET LCD_FPGA_DB6 LOC="G6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET LCD_FPGA_DB7 LOC="T11"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET LCD_FPGA_E LOC="AC9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET LCD_FPGA_RS LOC="J17"; # Bank 3, Vcco=2.5V, No DCI
NET LCD_FPGA_RW LOC="AC10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET LOOPBK_114_N LOC="AG1"; # Bank 118, MGTRXN1_118, GTP_DUAL_X0Y1
NET LOOPBK_114_N LOC="AH2"; # Bank 118, MGTTXN1_118, GTP_DUAL_X0Y1
NET LOOPBK_114_P LOC="AH1"; # Bank 118, MGTRXP1_118, GTP_DUAL_X0Y1
NET LOOPBK_114_P LOC="AJ2"; # Bank 118, MGTTXP1_118, GTP_DUAL_X0Y1
NET LOOPBK_116_N LOC="R1"; # Bank 112, MGTRXN1_112, GTP_DUAL_X0Y3
NET LOOPBK_116_N LOC="T2"; # Bank 112, MGTTXN1_112, GTP_DUAL_X0Y3
NET LOOPBK_116_P LOC="T1"; # Bank 112, MGTRXP1_112, GTP_DUAL_X0Y3
NET LOOPBK_116_P LOC="U2"; # Bank 112, MGTTXP1_112, GTP_DUAL_X0Y3
NET MOUSE_CLK LOC="R27"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET MOUSE_DATA LOC="U26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET PC4_HALT_B LOC="W9"; # Bank 18, Vcco=3.3V, No DCI
NET PCIE_CLK_QO_N LOC="AF3"; # Bank 118, MGTREFCLKN_118, GTP_DUAL_X0Y1
NET PCIE_CLK_QO_P LOC="AF4"; # Bank 118, MGTREFCLKP_118, GTP_DUAL_X0Y1
NET PCIE_PRSNT_B_FPGA LOC="AF24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET PCIE_RX_N LOC="AF1"; # Bank 118, MGTRXN0_118, GTP_DUAL_X0Y1
NET PCIE_RX_P LOC="AE1"; # Bank 118, MGTRXP0_118, GTP_DUAL_X0Y1
NET PCIE_TX_N LOC="AE2"; # Bank 118, MGTTXN0_118, GTP_DUAL_X0Y1
NET PCIE_TX_P LOC="AD2"; # Bank 118, MGTTXP0_118, GTP_DUAL_X0Y1
NET PHY_COL LOC="B32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_CRS LOC="E34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_INT LOC="H20"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_MDC LOC="H19"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_MDIO LOC="H13"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_RESET LOC="J14"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_RXCLK LOC="H17"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_RXCTL_RXDV LOC="E32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD0 LOC="A33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD1 LOC="B33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD2 LOC="C33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD3 LOC="C32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD4 LOC="D32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD5 LOC="C34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD6 LOC="D34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD7 LOC="F33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXER LOC="E33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_TXC_GTXCLK LOC="J16"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_TXCLK LOC="K17"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_TXCTL_TXEN LOC="AJ10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET PHY_TXD0 LOC="AF11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET PHY_TXD1 LOC="AE11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET PHY_TXD2 LOC="AH9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET PHY_TXD3 LOC="AH10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET PHY_TXD4 LOC="AG8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET PHY_TXD5 LOC="AH8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET PHY_TXD6 LOC="AG10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET PHY_TXD7 LOC="AG11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET PHY_TXER LOC="AJ9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET PIEZO_SPEAKER LOC="G30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET RESERVED1 LOC="AB23"; # Bank 0, Vcco=3.3V
NET RESERVED2 LOC="AC23"; # Bank 0, Vcco=3.3V
NET RREF LOC="V4"; # Bank 112, MGTRREF_112, GTP_DUAL_X0Y3
NET SATA1_RX_N LOC="Y1"; # Bank 114, MGTRXN0_114, GTP_DUAL_X0Y2
NET SATA1_RX_P LOC="W1"; # Bank 114, MGTRXP0_114, GTP_DUAL_X0Y2
NET SATA1_TX_N LOC="W2"; # Bank 114, MGTTXN0_114, GTP_DUAL_X0Y2
NET SATA1_TX_P LOC="V2"; # Bank 114, MGTTXP0_114, GTP_DUAL_X0Y2
NET SATA2_RX_N LOC="AA1"; # Bank 114, MGTRXN1_114, GTP_DUAL_X0Y2
NET SATA2_RX_P LOC="AB1"; # Bank 114, MGTRXP1_114, GTP_DUAL_X0Y2
NET SATA2_TX_N LOC="AB2"; # Bank 114, MGTTXN1_114, GTP_DUAL_X0Y2
NET SATA2_TX_P LOC="AC2"; # Bank 114, MGTTXP1_114, GTP_DUAL_X0Y2
NET SATACLK_QO_N LOC="Y3"; # Bank 114, MGTREFCLKN_114, GTP_DUAL_X0Y2
NET SATACLK_QO_P LOC="Y4"; # Bank 114, MGTREFCLKP_114, GTP_DUAL_X0Y2
NET SFP_RX_N LOC="H1"; # Bank 116, MGTRXN0_116, GTP_DUAL_X0Y4
NET SFP_RX_P LOC="G1"; # Bank 116, MGTRXP0_116, GTP_DUAL_X0Y4
NET SFP_TX_DISABLE_FPGA LOC="K24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET SFP_TX_N LOC="G2"; # Bank 116, MGTTXN0_116, GTP_DUAL_X0Y4
NET SFP_TX_P LOC="F2"; # Bank 116, MGTTXP0_116, GTP_DUAL_X0Y4
NET SGMII_RX_N LOC="P1"; # Bank 112, MGTRXN0_112, GTP_DUAL_X0Y3
NET SGMII_RX_P LOC="N1"; # Bank 112, MGTRXP0_112, GTP_DUAL_X0Y3
NET SGMII_TX_N LOC="N2"; # Bank 112, MGTTXN0_112, GTP_DUAL_X0Y3
NET SGMII_TX_P LOC="M2"; # Bank 112, MGTTXP0_112, GTP_DUAL_X0Y3
NET SGMIICLK_QO_N LOC="P3"; # Bank 112, MGTREFCLKN_112, GTP_DUAL_X0Y3
NET SGMIICLK_QO_P LOC="P4"; # Bank 112, MGTREFCLKP_112, GTP_DUAL_X0Y3
NET SMA_DIFF_CLK_IN_N LOC="H15"; # Bank 3, Vcco=2.5V, No DCI
NET SMA_DIFF_CLK_IN_P LOC="H14"; # Bank 3, Vcco=2.5V, No DCI
NET SMA_RX_N LOC="J1"; # Bank 116, MGTRXN1_116, GTP_DUAL_X0Y4
NET SMA_RX_P LOC="K1"; # Bank 116, MGTRXP1_116, GTP_DUAL_X0Y4
NET SMA_TX_N LOC="K2"; # Bank 116, MGTTXN1_116, GTP_DUAL_X0Y4
NET SMA_TX_P LOC="L2"; # Bank 116, MGTTXP1_116, GTP_DUAL_X0Y4
NET SPI_CE_B LOC="V9"; # Bank 18, Vcco=3.3V, No DCI
NET SRAM_ADV_LD_B LOC="H8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_BW0 LOC="D10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_BW1 LOC="D11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_BW2 LOC="J11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_BW3 LOC="K11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_CLK LOC="AG21"; # Bank 4, Vcco=3.3V, No DCI
NET SRAM_CLK LOC="G8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_CS_B LOC="J10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D16 LOC="N10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D17 LOC="E13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D18 LOC="E12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D19 LOC="L9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D20 LOC="M10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D21 LOC="E11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D22 LOC="F11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D23 LOC="L8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D24 LOC="M8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D25 LOC="G12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D26 LOC="G11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D27 LOC="C13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D28 LOC="B13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D29 LOC="K9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D30 LOC="K8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_D31 LOC="J9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_DQP0 LOC="D12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_DQP1 LOC="C12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_DQP2 LOC="H10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_DQP3 LOC="H9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_FLASH_A0 LOC="K12"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A1 LOC="K13"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A2 LOC="H23"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A3 LOC="G23"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A4 LOC="H12"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A5 LOC="J12"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A6 LOC="K22"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A7 LOC="K23"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A8 LOC="K14"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A9 LOC="L14"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A10 LOC="H22"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A11 LOC="G22"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A12 LOC="J15"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A13 LOC="K16"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A14 LOC="K21"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A15 LOC="J22"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A16 LOC="L16"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A17 LOC="L15"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A18 LOC="L20"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A19 LOC="L21"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A20 LOC="AE23"; # Bank 2, Vcco=3.3V
NET SRAM_FLASH_A21 LOC="AE22"; # Bank 2, Vcco=3.3V
NET SRAM_FLASH_D0 LOC="AD19"; # Bank 2, Vcco=3.3V
NET SRAM_FLASH_D1 LOC="AE19"; # Bank 2, Vcco=3.3V
NET SRAM_FLASH_D2 LOC="AE17"; # Bank 2, Vcco=3.3V
NET SRAM_FLASH_D3 LOC="AF16"; # Bank 2, Vcco=3.3V
NET SRAM_FLASH_D4 LOC="AD20"; # Bank 2, Vcco=3.3V
NET SRAM_FLASH_D5 LOC="AE21"; # Bank 2, Vcco=3.3V
NET SRAM_FLASH_D6 LOC="AE16"; # Bank 2, Vcco=3.3V
NET SRAM_FLASH_D7 LOC="AF15"; # Bank 2, Vcco=3.3V
NET SRAM_FLASH_D8 LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI
NET SRAM_FLASH_D9 LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI
NET SRAM_FLASH_D10 LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI
NET SRAM_FLASH_D11 LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI
NET SRAM_FLASH_D12 LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI
NET SRAM_FLASH_D13 LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI
NET SRAM_FLASH_D14 LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI
NET SRAM_FLASH_D15 LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI
NET SRAM_FLASH_WE_B LOC="AF20"; # Bank 2, Vcco=3.3V
NET SRAM_MODE LOC="A13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SRAM_OE_B LOC="B12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPA00 LOC="G5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPA01_USB_A0 LOC="N7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPA02_USB_A1 LOC="N5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPA03 LOC="P5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPA04 LOC="R6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPA05 LOC="M6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPA06 LOC="L6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPBRDY LOC="H5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPCE LOC="M5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPIRQ LOC="M7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPOE_USB_RD_B LOC="N8"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_MPWE_USB_WR_B LOC="R9"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D0 LOC="P9"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D1 LOC="T8"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D2 LOC="J7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D3 LOC="H7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D4 LOC="R7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D5 LOC="U7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D6 LOC="P7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D7 LOC="P6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D8 LOC="R8"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D9 LOC="L5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D10 LOC="L4"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D11 LOC="K6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D12 LOC="J5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D13 LOC="T6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D14 LOC="K7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET SYSACE_USB_D15 LOC="J6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET TRC_CLK LOC="AD9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET TRC_TS1E LOC="AK9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET TRC_TS1O LOC="AF10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET TRC_TS2E LOC="AK8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET TRC_TS2O LOC="AF9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET TRC_TS3 LOC="AJ11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET TRC_TS4 LOC="AK11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET TRC_TS5 LOC="AD11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET TRC_TS6 LOC="AD10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET USB_CS_B LOC="P10"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET USB_INT LOC="F5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET USB_RESET_B LOC="R11"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET USER_CLK LOC="AH15"; # Bank 4, Vcco=3.3V, No DCI
NET VGA_IN_BLUE0 LOC="AC4"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_BLUE1 LOC="AC5"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_BLUE2 LOC="AB6"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_BLUE3 LOC="AB7"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_BLUE4 LOC="AA5"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_BLUE5 LOC="AB5"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_BLUE6 LOC="AC7"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_BLUE7 LOC="AD7"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_CLAMP LOC="AH7"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_COAST LOC="AG7"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_DATA_CLK LOC="AH18"; # Bank 4, Vcco=3.3V, No DCI
NET VGA_IN_GREEN0 LOC="Y8"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_GREEN1 LOC="Y9"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_GREEN2 LOC="AD4"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_GREEN3 LOC="AD5"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_GREEN4 LOC="AA6"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_GREEN5 LOC="Y7"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_GREEN6 LOC="AD6"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_GREEN7 LOC="AE6"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_HSOUT LOC="AE7"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_ODD_EVEN_B LOC="W6"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_RED0 LOC="AG5"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_RED1 LOC="AF5"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_RED2 LOC="W7"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_RED3 LOC="V7"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_RED4 LOC="AH5"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_RED5 LOC="AG6"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_RED6 LOC="Y11"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_RED7 LOC="W11"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_SOGOUT LOC="AF6"; # Bank 18, Vcco=3.3V, No DCI
NET VGA_IN_VSOUT LOC="Y6"; # Bank 18, Vcco=3.3V, No DCI

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`timescale 1ns / 1ps
/*
* File : ALU.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 7-Jun-2011 GEA Initial design.
* 2.0 26-Jul-2012 GEA Many changes have been made.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* An Arithmetic Logic Unit for a MIPS32 processor. This module computes all
* arithmetic operations, including the following:
*
* Add, Subtract, Multiply, And, Or, Nor, Xor, Shift, Count leading 1s/0s.
*/
module ALU(
input clock,
input reset,
input EX_Stall,
input EX_Flush,
input [31:0] A, B,
input [4:0] Operation,
input signed [4:0] Shamt,
output reg signed [31:0] Result,
output BZero, // Used for Movc
output reg EXC_Ov,
output ALU_Stall // Stalls due to long ALU operations
);
`include "MIPS_Parameters.v"
/***
Performance Notes:
The ALU is the longest delay path in the Execute stage, and one of the longest
in the entire processor. This path varies based on the logic blocks that are
chosen to implement various functions, but there is certainly room to improve
the speed of arithmetic operations. The ALU could also be placed in a separate
pipeline stage after the Execute forwarding has completed.
***/
/***
Divider Logic:
The hardware divider requires 32 cycles to complete. Because it writes its
results to HILO and not to the pipeline, the pipeline can proceed without
stalling. When a later instruction tries to access HILO, the pipeline will
stall if the divide operation has not yet completed.
***/
// Internal state registers
reg [63:0] HILO;
reg HILO_Access; // Behavioral; not DFFs
reg [5:0] CLO_Result, CLZ_Result; // Behavioral; not DFFs
reg div_fsm;
// Internal signals
wire [31:0] HI, LO;
wire HILO_Commit;
wire signed [31:0] As, Bs;
wire AddSub_Add;
wire signed [31:0] AddSub_Result;
wire signed [63:0] Mult_Result;
wire [63:0] Multu_Result;
wire [31:0] Quotient;
wire [31:0] Remainder;
wire Div_Stall;
wire Div_Start, Divu_Start;
wire DivOp;
wire Div_Commit;
// Assignments
assign HI = HILO[63:32];
assign LO = HILO[31:0];
assign HILO_Commit = ~(EX_Stall | EX_Flush);
assign As = A;
assign Bs = B;
assign AddSub_Add = ((Operation == AluOp_Add) | (Operation == AluOp_Addu));
assign AddSub_Result = (AddSub_Add) ? (A + B) : (A - B);
assign Mult_Result = As * Bs;
assign Multu_Result = A * B;
assign BZero = (B == 32'h00000000);
assign DivOp = (Operation == AluOp_Div) || (Operation == AluOp_Divu);
assign Div_Commit = (div_fsm == 1'b1) && (Div_Stall == 1'b0);
assign Div_Start = (div_fsm == 1'b0) && (Operation == AluOp_Div) && (HILO_Commit == 1'b1);
assign Divu_Start = (div_fsm == 1'b0) && (Operation == AluOp_Divu) && (HILO_Commit == 1'b1);
assign ALU_Stall = (div_fsm == 1'b1) && (HILO_Access == 1'b1);
always @(*) begin
case (Operation)
AluOp_Add : Result <= AddSub_Result;
AluOp_Addu : Result <= AddSub_Result;
AluOp_And : Result <= A & B;
AluOp_Clo : Result <= {26'b0, CLO_Result};
AluOp_Clz : Result <= {26'b0, CLZ_Result};
AluOp_Mfhi : Result <= HI;
AluOp_Mflo : Result <= LO;
AluOp_Mul : Result <= Mult_Result[31:0];
AluOp_Nor : Result <= ~(A | B);
AluOp_Or : Result <= A | B;
AluOp_Sll : Result <= B << Shamt;
AluOp_Sllc : Result <= {B[15:0], 16'b0};
AluOp_Sllv : Result <= B << A[4:0];
AluOp_Slt : Result <= (As < Bs) ? 32'h00000001 : 32'h00000000;
AluOp_Sltu : Result <= (A < B) ? 32'h00000001 : 32'h00000000;
AluOp_Sra : Result <= Bs >>> Shamt;
AluOp_Srav : Result <= Bs >>> As[4:0];
AluOp_Srl : Result <= B >> Shamt;
AluOp_Srlv : Result <= B >> A[4:0];
AluOp_Sub : Result <= AddSub_Result;
AluOp_Subu : Result <= AddSub_Result;
AluOp_Xor : Result <= A ^ B;
default : Result <= 32'bx;
endcase
end
always @(posedge clock) begin
if (reset) begin
HILO <= 64'h00000000_00000000;
end
else if (Div_Commit) begin
HILO <= {Remainder, Quotient};
end
else if (HILO_Commit) begin
case (Operation)
AluOp_Mult : HILO <= Mult_Result;
AluOp_Multu : HILO <= Multu_Result;
AluOp_Madd : HILO <= HILO + Mult_Result;
AluOp_Maddu : HILO <= HILO + Multu_Result;
AluOp_Msub : HILO <= HILO - Mult_Result;
AluOp_Msubu : HILO <= HILO - Multu_Result;
AluOp_Mthi : HILO <= {A, LO};
AluOp_Mtlo : HILO <= {HI, B};
default : HILO <= HILO;
endcase
end
else begin
HILO <= HILO;
end
end
// Detect accesses to HILO. RAW and WAW hazards are possible while a
// divide operation is computing, so reads and writes to HILO must stall
// while the divider is busy.
// (This logic could be put into an earlier pipeline stage or into the
// datapath bits to improve timing.)
always @(Operation) begin
case (Operation)
AluOp_Div : HILO_Access <= 1;
AluOp_Divu : HILO_Access <= 1;
AluOp_Mfhi : HILO_Access <= 1;
AluOp_Mflo : HILO_Access <= 1;
AluOp_Mult : HILO_Access <= 1;
AluOp_Multu : HILO_Access <= 1;
AluOp_Madd : HILO_Access <= 1;
AluOp_Maddu : HILO_Access <= 1;
AluOp_Msub : HILO_Access <= 1;
AluOp_Msubu : HILO_Access <= 1;
AluOp_Mthi : HILO_Access <= 1;
AluOp_Mtlo : HILO_Access <= 1;
default : HILO_Access <= 0;
endcase
end
// Divider FSM: The divide unit is either available or busy.
always @(posedge clock) begin
if (reset) begin
div_fsm <= 2'd0;
end
else begin
case (div_fsm)
1'd0 : div_fsm <= (DivOp & HILO_Commit) ? 1'd1 : 1'd0;
1'd1 : div_fsm <= (~Div_Stall) ? 1'd0 : 1'd1;
endcase
end
end
// Detect overflow for signed operations. Note that MIPS32 has no overflow
// detection for multiplication/division operations.
always @(*) begin
case (Operation)
AluOp_Add : EXC_Ov <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));
AluOp_Sub : EXC_Ov <= ((A[31] ^ B[31]) & (A[31] ^ AddSub_Result[31]));
default : EXC_Ov <= 0;
endcase
end
// Count Leading Ones
always @(A) begin
casex (A)
32'b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd0;
32'b10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd1;
32'b110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd2;
32'b1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd3;
32'b1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd4;
32'b1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd5;
32'b1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd6;
32'b1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd7;
32'b1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd8;
32'b1111_1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd9;
32'b1111_1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd10;
32'b1111_1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd11;
32'b1111_1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd12;
32'b1111_1111_1111_10xx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd13;
32'b1111_1111_1111_110x_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd14;
32'b1111_1111_1111_1110_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd15;
32'b1111_1111_1111_1111_0xxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd16;
32'b1111_1111_1111_1111_10xx_xxxx_xxxx_xxxx : CLO_Result <= 6'd17;
32'b1111_1111_1111_1111_110x_xxxx_xxxx_xxxx : CLO_Result <= 6'd18;
32'b1111_1111_1111_1111_1110_xxxx_xxxx_xxxx : CLO_Result <= 6'd19;
32'b1111_1111_1111_1111_1111_0xxx_xxxx_xxxx : CLO_Result <= 6'd20;
32'b1111_1111_1111_1111_1111_10xx_xxxx_xxxx : CLO_Result <= 6'd21;
32'b1111_1111_1111_1111_1111_110x_xxxx_xxxx : CLO_Result <= 6'd22;
32'b1111_1111_1111_1111_1111_1110_xxxx_xxxx : CLO_Result <= 6'd23;
32'b1111_1111_1111_1111_1111_1111_0xxx_xxxx : CLO_Result <= 6'd24;
32'b1111_1111_1111_1111_1111_1111_10xx_xxxx : CLO_Result <= 6'd25;
32'b1111_1111_1111_1111_1111_1111_110x_xxxx : CLO_Result <= 6'd26;
32'b1111_1111_1111_1111_1111_1111_1110_xxxx : CLO_Result <= 6'd27;
32'b1111_1111_1111_1111_1111_1111_1111_0xxx : CLO_Result <= 6'd28;
32'b1111_1111_1111_1111_1111_1111_1111_10xx : CLO_Result <= 6'd29;
32'b1111_1111_1111_1111_1111_1111_1111_110x : CLO_Result <= 6'd30;
32'b1111_1111_1111_1111_1111_1111_1111_1110 : CLO_Result <= 6'd31;
32'b1111_1111_1111_1111_1111_1111_1111_1111 : CLO_Result <= 6'd32;
default : CLO_Result <= 6'd0;
endcase
end
// Count Leading Zeros
always @(A) begin
casex (A)
32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd0;
32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd1;
32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd2;
32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd3;
32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd4;
32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd5;
32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd6;
32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd7;
32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd8;
32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd9;
32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd10;
32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd11;
32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd12;
32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd13;
32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd14;
32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd15;
32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd16;
32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd17;
32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : CLZ_Result <= 6'd18;
32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : CLZ_Result <= 6'd19;
32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : CLZ_Result <= 6'd20;
32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : CLZ_Result <= 6'd21;
32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : CLZ_Result <= 6'd22;
32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : CLZ_Result <= 6'd23;
32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : CLZ_Result <= 6'd24;
32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : CLZ_Result <= 6'd25;
32'b0000_0000_0000_0000_0000_0000_001x_xxxx : CLZ_Result <= 6'd26;
32'b0000_0000_0000_0000_0000_0000_0001_xxxx : CLZ_Result <= 6'd27;
32'b0000_0000_0000_0000_0000_0000_0000_1xxx : CLZ_Result <= 6'd28;
32'b0000_0000_0000_0000_0000_0000_0000_01xx : CLZ_Result <= 6'd29;
32'b0000_0000_0000_0000_0000_0000_0000_001x : CLZ_Result <= 6'd30;
32'b0000_0000_0000_0000_0000_0000_0000_0001 : CLZ_Result <= 6'd31;
32'b0000_0000_0000_0000_0000_0000_0000_0000 : CLZ_Result <= 6'd32;
default : CLZ_Result <= 6'd0;
endcase
end
// Multicycle divide unit
Divide Divider (
.clock (clock),
.reset (reset),
.OP_div (Div_Start),
.OP_divu (Divu_Start),
.Dividend (A),
.Divisor (B),
.Quotient (Quotient),
.Remainder (Remainder),
.Stall (Div_Stall)
);
endmodule

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`timescale 1ns / 1ps
/*
* File : Add.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 7-Jun-2011 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* A simple 32-bit 2-input adder.
*/
module Add(
input [31:0] A,
input [31:0] B,
output [31:0] C
);
assign C = (A + B);
endmodule

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`timescale 1ns / 1ps
/*
* File : CPZero.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 16-Sep-2011 GEA Initial design.
* 2.0 14-May-2012 GEA Complete rework.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The MIPS-32 Coprocessor 0 (CP0). This is the processor management unit that allows
* interrupts, traps, system calls, and other exceptions. It distinguishes
* user and kernel modes, provides status information, and can override program
* flow. This processor is designed for "bare metal" memory access and thus does
* not have virtual memory hardware as a part of it. However, the subset of CP0
* is MIPS-32-compliant.
*/
module CPZero(
input clock,
//-- CP0 Functionality --//
input Mfc0, // CPU instruction is Mfc0
input Mtc0, // CPU instruction is Mtc0
input IF_Stall,
input ID_Stall, // Commits are not made during stalls
input COP1, // Instruction for Coprocessor 1
input COP2, // Instruction for Coprocessor 2
input COP3, // Instruction for Coprocessor 3
input ERET, // Instruction is ERET (Exception Return)
input [4:0] Rd, // Specifies Cp0 register
input [2:0] Sel, // Specifies Cp0 'select'
input [31:0] Reg_In, // Data from GP register to replace CP0 register
output reg [31:0] Reg_Out, // Data from CP0 register for GP register
output KernelMode, // Kernel mode indicator for pipeline transit
output ReverseEndian, // Reverse Endian memory indicator for User Mode
//-- Hw Interrupts --//
input [4:0] Int, // Five hardware interrupts external to the processor
//-- Exceptions --//
input reset, // Cold Reset (EXC_Reset)
// input EXC_SReset, // Soft Reset (not implemented)
input EXC_NMI, // Non-Maskable Interrupt
input EXC_AdIF, // Address Error Exception from i-fetch (mapped to AdEL)
input EXC_AdEL, // Address Error Exception from data memory load
input EXC_AdES, // Address Error Exception from data memory store
input EXC_Ov, // Integer Overflow Exception
input EXC_Tr, // Trap Exception
input EXC_Sys, // System Call Exception
input EXC_Bp, // Breakpoint Exception
input EXC_RI, // Reserved Instruction Exception
//-- Exception Data --//
input [31:0] ID_RestartPC, // PC for exception, whether PC of instruction or of branch (PC-4) if BDS
input [31:0] EX_RestartPC, // Same as 'ID_RestartPC' but in EX stage
input [31:0] M_RestartPC, // Same as 'ID_RestartPC' but in MEM stage
input ID_IsFlushed,
input IF_IsBD, // Indicator of IF exception being a branch delay slot instruction
input ID_IsBD, // Indicator of ID exception being a branch delay slot instruction
input EX_IsBD, // Indicator of EX exception being a branch delay slot instruction
input M_IsBD, // Indicator of M exception being a branch delay slot instruction
input [31:0] BadAddr_M, // Bad 'Virtual' Address for exceptions AdEL, AdES in MEM stage
input [31:0] BadAddr_IF, // Bad 'Virtual' Address for AdIF (i.e. AdEL) in IF stage
input ID_CanErr, // Cumulative signal, i.e. (ID_ID_CanErr | ID_EX_CanErr | ID_M_CanErr)
input EX_CanErr, // Cumulative signal, i.e. (EX_EX_CanErr | EX_M_CanErr)
input M_CanErr, // Memory stage can error (i.e. cause exception)
//-- Exception Control Flow --/
output IF_Exception_Stall,
output ID_Exception_Stall,
output EX_Exception_Stall,
output M_Exception_Stall,
output IF_Exception_Flush,
output ID_Exception_Flush,
output EX_Exception_Flush,
output M_Exception_Flush,
output Exc_PC_Sel, // Mux selector for exception PC override
output reg [31:0] Exc_PC_Out, // Address for PC at the beginning of an exception
output [7:0] IP // Pending Interrupts from Cause register (for diagnostic purposes)
);
`include "MIPS_Parameters.v"
/***
Exception Control Flow Notes
- Exceptions can occur in every pipeline stage. This implies that more than one exception
can be raised in a single cycle. When this occurs, only the forward-most exception
(i.e. MEM over EX) is handled. This and the following note guarantee program order.
- An exception in any pipeline stage must stall that stage until all following stages are
exception-free. This is because it only makes sense for exceptions to occur in program order.
- A pipeline stage which causes an exception must flush, i.e. prevent any commits it would
have normally made and convert itself to a NOP for the next pipeline stage. Furthermore,
it must flush all previous pipeline stages as well in order to retain program order.
- Instructions reading CP0 (mtc0) read in ID without further action. Writes to CP0 (mtc0,
eret) also write in ID, but only after forward pipeline stages have been cleared
of possible exceptions. This prevents many insidious bugs, such as switching to User Mode
in ID when a legitimate memory access in kernel mode is processing in MEM, or conversely
a switch to Kernel Mode in ID when an instruction in User Mode is attempting a kernel region
memory access (when a kernel mode signal does not propagate through the pipeline).
- Commits occur in ID (CP0), EX (HILO), MEM, and WB (registers).
- Hardware interrupts are detected and inserted in the ID stage, but only when there are no
other possible exceptions in the pipeline. Because they appear 'asynchronous' to the
processor, the remaining instructions in forward stages (EX, MEM, WB) can either be
flushed or completed. It is simplest to have them complete to avoid restarts, but the
interrupt latency is higher if e.g. the MEM stage stalls on a memory access (this would
be unavoidable on single-cycle processors). This implementation allows all forward instructions
to complete, for a greater instruction throughput but higher interrupt latency.
- Software interrupts should appear synchronous in the program order, meaning that all
instructions previous to them should complete and no instructions after them should start
until the interrupts has been processed.
Exception Name Short Name Pipeline Stage
Address Error Ex (AdEL, AdES) MEM, IF
Integer Overflow Ex (Ov) EX
Trap Ex (Tr) MEM
Syscall (Sys) ID
Breakpoint (Bp) ID
Reserved Instruction (RI) ID
Coprocessor Unusable (CpU) ID
Interrupt (Int) ID
Reset, SReset, NMI ID
***/
// Exceptions Generated Internally
wire EXC_CpU;
// Hardware Interrupt #5, caused by Timer/Perf counter
wire Int5;
// Top-level Authoritative Interrupt Signal
wire EXC_Int;
// General Exception detection (all but Interrupts, Reset, Soft Reset, and NMI)
wire EXC_General = EXC_AdIF | EXC_AdEL | EXC_AdES | EXC_Ov | EXC_Tr | EXC_Sys | EXC_Bp | EXC_RI | EXC_CpU;
// Misc
wire CP0_WriteCond;
reg [3:0] Cause_ExcCode_bits;
reg reset_r;
always @(posedge clock) begin
reset_r <= reset;
end
/***
MIPS-32 COPROCESSOR 0 (Cp0) REGISTERS
These are defined in "MIPS32 Architecture for Programmers Volume III:
The MIPS32 Privileged Resource Architecture" from MIPS Technologies, Inc.
Optional registers are omitted. Changes to the processor (such as adding
an MMU/TLB, etc. must be reflected in these registers.
*/
// BadVAddr Register (Register 8, Select 0)
reg [31:0] BadVAddr;
// Count Register (Register 9, Select 0)
reg [31:0] Count;
// Compare Register (Register 11, Select 0)
reg [31:0] Compare;
// Status Register (Register 12, Select 0)
wire [2:0] Status_CU_321 = 3'b000;
reg Status_CU_0; // Access Control to CPs, [2]->Cp3, ... [0]->Cp0
wire Status_RP = 0;
wire Status_FR = 0;
reg Status_RE; // Reverse Endian Memory for User Mode
wire Status_MX = 0;
wire Status_PX = 0;
reg Status_BEV; // Exception vector locations (0->Norm, 1->Bootstrap)
wire Status_TS = 0;
wire Status_SR = 0; // Soft reset not implemented
reg Status_NMI; // Non-Maskable Interrupt
wire Status_RES = 0;
wire [1:0] Status_Custom = 2'b00;
reg [7:0] Status_IM; // Interrupt mask
wire Status_KX = 0;
wire Status_SX = 0;
wire Status_UX = 0;
reg Status_UM; // Base operating mode (0->Kernel, 1->User)
wire Status_R0 = 0;
reg Status_ERL; // Error Level (0->Normal, 1->Error (reset, NMI))
reg Status_EXL; // Exception level (0->Normal, 1->Exception)
reg Status_IE; // Interrupt Enable
wire [31:0] Status = {Status_CU_321, Status_CU_0, Status_RP, Status_FR, Status_RE, Status_MX,
Status_PX, Status_BEV, Status_TS, Status_SR, Status_NMI, Status_RES,
Status_Custom, Status_IM, Status_KX, Status_SX, Status_UX,
Status_UM, Status_R0, Status_ERL, Status_EXL, Status_IE};
// Cause Register (Register 13, Select 0)
reg Cause_BD; // Exception occured in Branch Delay
reg [1:0] Cause_CE; // CP number for CP Unusable exception
reg Cause_IV; // Indicator of general IV (0->0x180) or special IV (1->0x200)
wire Cause_WP = 0;
reg [7:0] Cause_IP; // Pending HW Interrupt indicator.
wire Cause_ExcCode4 = 0; // Can be made into a register when this bit is needed.
reg [3:0] Cause_ExcCode30; // Description of Exception (only lower 4 bits currently used; see above)
wire [31:0] Cause = {Cause_BD, 1'b0, Cause_CE, 4'b0000, Cause_IV, Cause_WP,
6'b000000, Cause_IP, 1'b0, Cause_ExcCode4, Cause_ExcCode30, 2'b00};
// Exception Program Counter (Register 14, Select 0)
reg [31:0] EPC;
// Processor Identification (Register 15, Select 0)
wire [7:0] ID_Options = 8'b0000_0000;
wire [7:0] ID_CID = 8'b0000_0000;
wire [7:0] ID_PID = 8'b0000_0000;
wire [7:0] ID_Rev = 8'b0000_0001;
wire [31:0] PRId = {ID_Options, ID_CID, ID_PID, ID_Rev};
// Configuration Register (Register 16, Select 0)
wire Config_M = 1;
wire [14:0] Config_Impl = 15'b000_0000_0000_0000;
wire Config_BE = Big_Endian; // From parameters file
wire [1:0] Config_AT = 2'b00;
wire [2:0] Config_AR = 3'b000;
wire [2:0] Config_MT = 3'b000;
wire [2:0] Config_K0 = 3'b000;
wire [31:0] Config = {Config_M, Config_Impl, Config_BE, Config_AT, Config_AR, Config_MT,
4'b0000, Config_K0};
// Configuration Register 1 (Register 16, Select 1)
wire Config1_M = 0;
wire [5:0] Config1_MMU = 6'b000000;
wire [2:0] Config1_IS = 3'b000;
wire [2:0] Config1_IL = 3'b000;
wire [2:0] Config1_IA = 3'b000;
wire [2:0] Config1_DS = 3'b000;
wire [2:0] Config1_DL = 3'b000;
wire [2:0] Config1_DA = 3'b000;
wire Config1_C2 = 0;
wire Config1_MD = 0;
wire Config1_PC = 0; // XXX Performance Counters
wire Config1_WR = 0; // XXX Watch Registers
wire Config1_CA = 0;
wire Config1_EP = 0;
wire Config1_FP = 0;
wire [31:0] Config1 = {Config1_M, Config1_MMU, Config1_IS, Config1_IL, Config1_IA,
Config1_DS, Config1_DL, Config1_DA, Config1_C2,
Config1_MD, Config1_PC, Config1_WR, Config1_CA,
Config1_EP, Config1_FP};
// Performance Counter Register (Register 25) XXX TODO
// ErrorEPC Register (Register 30, Select 0)
reg [31:0] ErrorEPC;
// Exception Detection and Processing
wire M_Exception_Detect, EX_Exception_Detect, ID_Exception_Detect, IF_Exception_Detect;
wire M_Exception_Mask, EX_Exception_Mask, ID_Exception_Mask, IF_Exception_Mask;
wire M_Exception_Ready, EX_Exception_Ready, ID_Exception_Ready, IF_Exception_Ready;
assign IP = Cause_IP;
/*** Coprocessor Unusable Exception ***/
assign EXC_CpU = COP1 | COP2 | COP3 | ((Mtc0 | Mfc0 | ERET) & ~(Status_CU_0 | KernelMode));
/*** Kernel Mode Signal ***/
assign KernelMode = ~Status_UM | Status_EXL | Status_ERL;
/*** Reverse Endian for User Mode ***/
assign ReverseEndian = Status_RE;
/*** Interrupts ***/
assign Int5 = (Count == Compare);
//assign EXC_Int = ((Cause_IP[7:0] & Status_IM[7:0]) != 8'h00) & Status_IE & ~Status_EXL & ~Status_ERL & ~ID_IsFlushed;
wire Enabled_Interrupt = EXC_NMI | (Status_IE & ((Cause_IP[7:0] & Status_IM[7:0]) != 8'h00));
assign EXC_Int = Enabled_Interrupt & ~Status_EXL & ~Status_ERL & ~ID_IsFlushed;
assign CP0_WriteCond = (Status_CU_0 | KernelMode) & Mtc0 & ~ID_Stall;
/***
Exception Hazard Flow Control Explanation:
- An exception at any time in any stage causes its own and any previous stages to
flush (clear own commits, NOPS to fwd stages).
- An exception in a stage can also stall that stage (and inherently all previous stages) if and only if:
1. A forward stage is capable of causing an exception AND
2. A forward stage is not currently causing an exception.
- An exception is ready to process when it is detected and not stalled in a stage.
Flush specifics per pipeline stage:
MEM: Mask 'MemWrite' and 'MemRead' (for performance) after EX/M and before data memory. NOPs to M/WB.
EX : Mask writes to HI/LO. NOPs to EX/M.
ID : Mask writes (reads?) to CP0. NOPs to ID/EX.
IF : NOP to IF/ID.
***/
/*** Exceptions grouped by pipeline stage ***/
assign M_Exception_Detect = EXC_AdEL | EXC_AdES | EXC_Tr;
assign EX_Exception_Detect = EXC_Ov;
assign ID_Exception_Detect = EXC_Sys | EXC_Bp | EXC_RI | EXC_CpU | EXC_Int;
assign IF_Exception_Detect = EXC_AdIF;
/*** Exception mask conditions ***/
// A potential bug would occur if e.g. EX stalls, MEM has data, but MEM is not stalled and finishes
// going through the pipeline so forwarding would fail. This is not a problem however because
// EX would not need data since it would flush on an exception.
assign M_Exception_Mask = IF_Stall;
assign EX_Exception_Mask = IF_Stall | M_CanErr;
assign ID_Exception_Mask = IF_Stall | M_CanErr | EX_CanErr;
assign IF_Exception_Mask = M_CanErr | EX_CanErr | ID_CanErr | EXC_Int;
/***
Exceptions which must wait for forward stages. A stage will not stall if a forward stage has an exception.
These stalls must be inserted as stall conditions in the hazard unit so that it will take care of chaining.
All writes to CP0 must also wait for forward hazard conditions to clear.
*/
assign M_Exception_Stall = M_Exception_Detect & M_Exception_Mask;
assign EX_Exception_Stall = EX_Exception_Detect & EX_Exception_Mask & ~M_Exception_Detect;
assign ID_Exception_Stall = (ID_Exception_Detect | ERET | Mtc0) & ID_Exception_Mask & ~(EX_Exception_Detect | M_Exception_Detect);
assign IF_Exception_Stall = IF_Exception_Detect & IF_Exception_Mask & ~(ID_Exception_Detect | EX_Exception_Detect | M_Exception_Detect);
/*** Exceptions which are ready to process (mutually exclusive) ***/
// XXX can remove ~ID_Stall since in mask now (?)
assign M_Exception_Ready = ~ID_Stall & M_Exception_Detect & ~M_Exception_Mask;
assign EX_Exception_Ready = ~ID_Stall & EX_Exception_Detect & ~EX_Exception_Mask;
assign ID_Exception_Ready = ~ID_Stall & ID_Exception_Detect & ~ID_Exception_Mask;
assign IF_Exception_Ready = ~ID_Stall & IF_Exception_Detect & ~IF_Exception_Mask;
/***
Flushes. A flush clears a pipeline stage's control signals and prevents the stage from committing any changes.
Data such as 'RestartPC' and the detected exception must remain.
*/
assign M_Exception_Flush = M_Exception_Detect;
assign EX_Exception_Flush = M_Exception_Detect | EX_Exception_Detect;
assign ID_Exception_Flush = M_Exception_Detect | EX_Exception_Detect | ID_Exception_Detect;
assign IF_Exception_Flush = M_Exception_Detect | EX_Exception_Detect | ID_Exception_Detect | IF_Exception_Detect | (ERET & ~ID_Stall) | reset_r;
/*** Software reads of CP0 Registers ***/
always @(*) begin
if (Mfc0 & (Status_CU_0 | KernelMode)) begin
case (Rd)
5'd8 : Reg_Out <= BadVAddr;
5'd9 : Reg_Out <= Count;
5'd11 : Reg_Out <= Compare;
5'd12 : Reg_Out <= Status;
5'd13 : Reg_Out <= Cause;
5'd14 : Reg_Out <= EPC;
5'd15 : Reg_Out <= PRId;
5'd16 : Reg_Out <= (Sel == 3'b000) ? Config : Config1;
5'd30 : Reg_Out <= ErrorEPC;
default : Reg_Out <= 32'h0000_0000;
endcase
end
else begin
Reg_Out <= 32'h0000_0000;
end
end
/*** Cp0 Register Assignments: Non-general exceptions (Reset, Soft Reset, NMI...) ***/
always @(posedge clock) begin
if (reset) begin
Status_BEV <= 1;
Status_NMI <= 0;
Status_ERL <= 1;
ErrorEPC <= 32'b0;
end
else if (ID_Exception_Ready & EXC_NMI) begin
Status_BEV <= 1;
Status_NMI <= 1;
Status_ERL <= 1;
ErrorEPC <= ID_RestartPC;
end
else begin
Status_BEV <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[22] : Status_BEV;
Status_NMI <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[19] : Status_NMI;
Status_ERL <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[2] : ((Status_ERL & ERET & ~ID_Stall) ? 0 : Status_ERL);
ErrorEPC <= (CP0_WriteCond & (Rd == 5'd30) & (Sel == 3'b000)) ? Reg_In : ErrorEPC;
end
end
/*** Cp0 Register Assignments: All other registers ***/
always @(posedge clock) begin
if (reset) begin
Count <= 32'b0;
Compare <= 32'b0;
Status_CU_0 <= 0;
Status_RE <= 0;
Status_IM <= 8'b0;
Status_UM <= 0;
Status_IE <= 0;
Cause_IV <= 0;
Cause_IP <= 8'b0;
end
else begin
Count <= (CP0_WriteCond & (Rd == 5'd9 ) & (Sel == 3'b000)) ? Reg_In : ((Count == Compare) ? 32'b0 : Count + 1);
Compare <= (CP0_WriteCond & (Rd == 5'd11) & (Sel == 3'b000)) ? Reg_In : Compare;
Status_CU_0 <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[28] : Status_CU_0;
Status_RE <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[25] : Status_RE;
Status_IM <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[15:8] : Status_IM;
Status_UM <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[4] : Status_UM;
Status_IE <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[0] : Status_IE;
Cause_IV <= (CP0_WriteCond & (Rd == 5'd13) & (Sel == 3'b000)) ? Reg_In[23] : Cause_IV;
/* Cause_IP indicates 8 interrupts:
[7] is set by the timer comparison, and cleared by reading 'Count'.
[6:2] are set and cleared by external hardware.
[1:0] are set and cleared by software.
*/
// If reading -> 0, Otherwise if 0 -> Int5.
Cause_IP[7] <= ((Status_CU_0 | KernelMode) & Mfc0 & (Rd == 5'd9) & (Sel == 3'b000)) ? 0 : ((Cause_IP[7] == 0) ? Int5 : Cause_IP[7]);
Cause_IP[6:2] <= Int[4:0];
Cause_IP[1:0] <= (CP0_WriteCond & (Rd == 5'd13) & (Sel == 3'b000)) ? Reg_In[9:8] : Cause_IP[1:0];
end
end
/*** Cp0 Register Assignments: General Exception and Interrupt Processing ***/
always @(posedge clock) begin
if (reset) begin
Cause_BD <= 0;
Cause_CE <= 2'b00;
Cause_ExcCode30 <= 4'b0000;
Status_EXL <= 0;
EPC <= 32'h0;
BadVAddr <= 32'h0;
end
else begin
// MEM stage
if (M_Exception_Ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : M_IsBD;
Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00));
Cause_ExcCode30 <= Cause_ExcCode_bits;
Status_EXL <= 1;
EPC <= (Status_EXL) ? EPC : M_RestartPC;
BadVAddr <= BadAddr_M;
end
// EX stage
else if (EX_Exception_Ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : EX_IsBD;
Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00));
Cause_ExcCode30 <= Cause_ExcCode_bits;
Status_EXL <= 1;
EPC <= (Status_EXL) ? EPC : EX_RestartPC;
BadVAddr <= BadVAddr;
end
// ID stage
else if (ID_Exception_Ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : ID_IsBD;
Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00));
Cause_ExcCode30 <= Cause_ExcCode_bits;
Status_EXL <= 1;
EPC <= (Status_EXL) ? EPC : ID_RestartPC;
BadVAddr <= BadVAddr;
end
// IF stage
else if (IF_Exception_Ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : IF_IsBD;
Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00));
Cause_ExcCode30 <= Cause_ExcCode_bits;
Status_EXL <= 1;
EPC <= (Status_EXL) ? EPC : BadAddr_IF;
BadVAddr <= BadAddr_IF;
end
// No exceptions this cycle
else begin
Cause_BD <= 1'b0;
Cause_CE <= Cause_CE;
Cause_ExcCode30 <= Cause_ExcCode30;
// Without new exceptions, 'Status_EXL' is set by software or cleared by ERET.
Status_EXL <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[1] : ((Status_EXL & ERET & ~ID_Stall) ? 0 : Status_EXL);
// The EPC is also writable by software
EPC <= (CP0_WriteCond & (Rd == 5'd14) & (Sel == 3'b000)) ? Reg_In : EPC;
BadVAddr <= BadVAddr;
end
end
end
/*** Program Counter for all Exceptions/Interrupts ***/
always @(*) begin
// Following is redundant since PC has initial value now.
if (reset) begin
Exc_PC_Out <= EXC_Vector_Base_Reset;
end
else if (ERET & ~ID_Stall) begin
Exc_PC_Out <= (Status_ERL) ? ErrorEPC : EPC;
end
else if (EXC_General) begin
Exc_PC_Out <= (Status_BEV) ? (EXC_Vector_Base_Other_Boot + EXC_Vector_Offset_General) :
(EXC_Vector_Base_Other_NoBoot + EXC_Vector_Offset_General);
end
else if (EXC_NMI) begin
Exc_PC_Out <= EXC_Vector_Base_Reset;
end
else if (EXC_Int & Cause_IV) begin
Exc_PC_Out <= (Status_BEV) ? (EXC_Vector_Base_Other_Boot + EXC_Vector_Offset_Special) :
(EXC_Vector_Base_Other_NoBoot + EXC_Vector_Offset_Special);
end
else begin
Exc_PC_Out <= (Status_BEV) ? (EXC_Vector_Base_Other_Boot + EXC_Vector_Offset_General) :
(EXC_Vector_Base_Other_NoBoot + EXC_Vector_Offset_General);
end
end
//assign Exc_PC_Sel = (reset | (ERET & ~ID_Stall) | EXC_General | EXC_Int);
assign Exc_PC_Sel = reset | (ERET & ~ID_Stall) | IF_Exception_Ready | ID_Exception_Ready | EX_Exception_Ready | M_Exception_Ready;
/*** Cause Register ExcCode Field ***/
always @(*) begin
// Ordered by Pipeline Stage with Interrupts last
if (EXC_AdEL) Cause_ExcCode_bits <= 4'h4; // 00100
else if (EXC_AdES) Cause_ExcCode_bits <= 4'h5; // 00101
else if (EXC_Tr) Cause_ExcCode_bits <= 4'hd; // 01101
else if (EXC_Ov) Cause_ExcCode_bits <= 4'hc; // 01100
else if (EXC_Sys) Cause_ExcCode_bits <= 4'h8; // 01000
else if (EXC_Bp) Cause_ExcCode_bits <= 4'h9; // 01001
else if (EXC_RI) Cause_ExcCode_bits <= 4'ha; // 01010
else if (EXC_CpU) Cause_ExcCode_bits <= 4'hb; // 01011
else if (EXC_AdIF) Cause_ExcCode_bits <= 4'h4; // 00100
else if (EXC_Int) Cause_ExcCode_bits <= 4'h0; // 00000 // OK that NMI writes this.
else Cause_ExcCode_bits <= 4'bxxxx;
end
endmodule

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`timescale 1ns / 1ps
/*
* File : Compare.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 15-Jun-2011 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* Compares two 32-bit values and outputs the following information about them:
* EQ : A and B are equal
* GZ : A is greater than zero
* LZ : A is less than zero
* GEZ : A is greater than or equal to zero
* LEZ : A is less than or equal to zero
*/
module Compare(
input [31:0] A,
input [31:0] B,
output EQ,
output GZ,
output LZ,
output GEZ,
output LEZ
);
wire ZeroA = (A == 32'b0);
assign EQ = ( A == B);
assign GZ = (~A[31] & ~ZeroA);
assign LZ = A[31];
assign GEZ = ~A[31];
assign LEZ = ( A[31] | ZeroA);
endmodule

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`timescale 1ns / 1ps
/*
* File : Control.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 7-Jun-2011 GEA Initial design.
* 2.0 26-May-2012 GEA Release version with CP0.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The Datapath Controller. This module sets the datapath control
* bits for an incoming instruction. These control bits follow the
* instruction through each pipeline stage as needed, and constitute
* the effective operation of the processor through each pipeline stage.
*/
module Control(
input ID_Stall,
input [5:0] OpCode,
input [5:0] Funct,
input [4:0] Rs, // used to differentiate mfc0 and mtc0
input [4:0] Rt, // used to differentiate bgez,bgezal,bltz,bltzal,teqi,tgei,tgeiu,tlti,tltiu,tnei
input Cmp_EQ,
input Cmp_GZ,
input Cmp_GEZ,
input Cmp_LZ,
input Cmp_LEZ,
//------------
output IF_Flush,
output reg [7:0] DP_Hazards,
output [1:0] PCSrc,
output SignExtend,
output Link,
output Movn,
output Movz,
output Mfc0,
output Mtc0,
output CP1,
output CP2,
output CP3,
output Eret,
output Trap,
output TrapCond,
output EXC_Sys,
output EXC_Bp,
output EXC_RI,
output ID_CanErr,
output EX_CanErr,
output M_CanErr,
output NextIsDelay,
output RegDst,
output ALUSrcImm,
output reg [4:0] ALUOp,
output LLSC,
output MemWrite,
output MemRead,
output MemByte,
output MemHalf,
output MemSignExtend,
output Left,
output Right,
output RegWrite,
output MemtoReg
);
`include "MIPS_Parameters.v"
wire Movc;
wire Branch, Branch_EQ, Branch_GTZ, Branch_LEZ, Branch_NEQ, Branch_GEZ, Branch_LTZ;
wire Unaligned_Mem;
reg [15:0] Datapath;
assign PCSrc[0] = Datapath[14];
assign Link = Datapath[13];
assign ALUSrcImm = Datapath[12];
assign Movc = Datapath[11];
assign Trap = Datapath[10];
assign TrapCond = Datapath[9];
assign RegDst = Datapath[8];
assign LLSC = Datapath[7];
assign MemRead = Datapath[6];
assign MemWrite = Datapath[5];
assign MemHalf = Datapath[4];
assign MemByte = Datapath[3];
assign MemSignExtend = Datapath[2];
assign RegWrite = Datapath[1];
assign MemtoReg = Datapath[0];
reg [2:0] DP_Exceptions;
assign ID_CanErr = DP_Exceptions[2];
assign EX_CanErr = DP_Exceptions[1];
assign M_CanErr = DP_Exceptions[0];
// Set the main datapath control signals based on the Op Code
always @(*) begin
if (ID_Stall)
Datapath <= DP_None;
else begin
case (OpCode)
// R-Type
Op_Type_R :
begin
case (Funct)
Funct_Add : Datapath <= DP_Add;
Funct_Addu : Datapath <= DP_Addu;
Funct_And : Datapath <= DP_And;
Funct_Break : Datapath <= DP_Break;
Funct_Div : Datapath <= DP_Div;
Funct_Divu : Datapath <= DP_Divu;
Funct_Jalr : Datapath <= DP_Jalr;
Funct_Jr : Datapath <= DP_Jr;
Funct_Mfhi : Datapath <= DP_Mfhi;
Funct_Mflo : Datapath <= DP_Mflo;
Funct_Movn : Datapath <= DP_Movn;
Funct_Movz : Datapath <= DP_Movz;
Funct_Mthi : Datapath <= DP_Mthi;
Funct_Mtlo : Datapath <= DP_Mtlo;
Funct_Mult : Datapath <= DP_Mult;
Funct_Multu : Datapath <= DP_Multu;
Funct_Nor : Datapath <= DP_Nor;
Funct_Or : Datapath <= DP_Or;
Funct_Sll : Datapath <= DP_Sll;
Funct_Sllv : Datapath <= DP_Sllv;
Funct_Slt : Datapath <= DP_Slt;
Funct_Sltu : Datapath <= DP_Sltu;
Funct_Sra : Datapath <= DP_Sra;
Funct_Srav : Datapath <= DP_Srav;
Funct_Srl : Datapath <= DP_Srl;
Funct_Srlv : Datapath <= DP_Srlv;
Funct_Sub : Datapath <= DP_Sub;
Funct_Subu : Datapath <= DP_Subu;
Funct_Syscall : Datapath <= DP_Syscall;
Funct_Teq : Datapath <= DP_Teq;
Funct_Tge : Datapath <= DP_Tge;
Funct_Tgeu : Datapath <= DP_Tgeu;
Funct_Tlt : Datapath <= DP_Tlt;
Funct_Tltu : Datapath <= DP_Tltu;
Funct_Tne : Datapath <= DP_Tne;
Funct_Xor : Datapath <= DP_Xor;
default : Datapath <= DP_None;
endcase
end
// R2-Type
Op_Type_R2 :
begin
case (Funct)
Funct_Clo : Datapath <= DP_Clo;
Funct_Clz : Datapath <= DP_Clz;
Funct_Madd : Datapath <= DP_Madd;
Funct_Maddu : Datapath <= DP_Maddu;
Funct_Msub : Datapath <= DP_Msub;
Funct_Msubu : Datapath <= DP_Msubu;
Funct_Mul : Datapath <= DP_Mul;
default : Datapath <= DP_None;
endcase
end
// I-Type
Op_Addi : Datapath <= DP_Addi;
Op_Addiu : Datapath <= DP_Addiu;
Op_Andi : Datapath <= DP_Andi;
Op_Ori : Datapath <= DP_Ori;
Op_Pref : Datapath <= DP_Pref;
Op_Slti : Datapath <= DP_Slti;
Op_Sltiu : Datapath <= DP_Sltiu;
Op_Xori : Datapath <= DP_Xori;
// Jumps (using immediates)
Op_J : Datapath <= DP_J;
Op_Jal : Datapath <= DP_Jal;
// Branches and Traps
Op_Type_BI :
begin
case (Rt)
OpRt_Bgez : Datapath <= DP_Bgez;
OpRt_Bgezal : Datapath <= DP_Bgezal;
OpRt_Bltz : Datapath <= DP_Bltz;
OpRt_Bltzal : Datapath <= DP_Bltzal;
OpRt_Teqi : Datapath <= DP_Teqi;
OpRt_Tgei : Datapath <= DP_Tgei;
OpRt_Tgeiu : Datapath <= DP_Tgeiu;
OpRt_Tlti : Datapath <= DP_Tlti;
OpRt_Tltiu : Datapath <= DP_Tltiu;
OpRt_Tnei : Datapath <= DP_Tnei;
default : Datapath <= DP_None;
endcase
end
Op_Beq : Datapath <= DP_Beq;
Op_Bgtz : Datapath <= DP_Bgtz;
Op_Blez : Datapath <= DP_Blez;
Op_Bne : Datapath <= DP_Bne;
// Coprocessor 0
Op_Type_CP0 :
begin
case (Rs)
OpRs_MF : Datapath <= DP_Mfc0;
OpRs_MT : Datapath <= DP_Mtc0;
OpRs_ERET : Datapath <= (Funct == Funct_ERET) ? DP_Eret : DP_None;
default : Datapath <= DP_None;
endcase
end
// Memory
Op_Lb : Datapath <= DP_Lb;
Op_Lbu : Datapath <= DP_Lbu;
Op_Lh : Datapath <= DP_Lh;
Op_Lhu : Datapath <= DP_Lhu;
Op_Ll : Datapath <= DP_Ll;
Op_Lui : Datapath <= DP_Lui;
Op_Lw : Datapath <= DP_Lw;
Op_Lwl : Datapath <= DP_Lwl;
Op_Lwr : Datapath <= DP_Lwr;
Op_Sb : Datapath <= DP_Sb;
Op_Sc : Datapath <= DP_Sc;
Op_Sh : Datapath <= DP_Sh;
Op_Sw : Datapath <= DP_Sw;
Op_Swl : Datapath <= DP_Swl;
Op_Swr : Datapath <= DP_Swr;
default : Datapath <= DP_None;
endcase
end
end
// Set the Hazard Control Signals and Exception Indicators based on the Op Code
always @(*) begin
case (OpCode)
// R-Type
Op_Type_R :
begin
case (Funct)
Funct_Add : begin DP_Hazards <= HAZ_Add; DP_Exceptions <= EXC_Add; end
Funct_Addu : begin DP_Hazards <= HAZ_Addu; DP_Exceptions <= EXC_Addu; end
Funct_And : begin DP_Hazards <= HAZ_And; DP_Exceptions <= EXC_And; end
Funct_Break : begin DP_Hazards <= HAZ_Break; DP_Exceptions <= EXC_Break; end
Funct_Div : begin DP_Hazards <= HAZ_Div; DP_Exceptions <= EXC_Div; end
Funct_Divu : begin DP_Hazards <= HAZ_Divu; DP_Exceptions <= EXC_Divu; end
Funct_Jalr : begin DP_Hazards <= HAZ_Jalr; DP_Exceptions <= EXC_Jalr; end
Funct_Jr : begin DP_Hazards <= HAZ_Jr; DP_Exceptions <= EXC_Jr; end
Funct_Mfhi : begin DP_Hazards <= HAZ_Mfhi; DP_Exceptions <= EXC_Mfhi; end
Funct_Mflo : begin DP_Hazards <= HAZ_Mflo; DP_Exceptions <= EXC_Mflo; end
Funct_Movn : begin DP_Hazards <= HAZ_Movn; DP_Exceptions <= EXC_Movn; end
Funct_Movz : begin DP_Hazards <= HAZ_Movz; DP_Exceptions <= EXC_Movz; end
Funct_Mthi : begin DP_Hazards <= HAZ_Mthi; DP_Exceptions <= EXC_Mthi; end
Funct_Mtlo : begin DP_Hazards <= HAZ_Mtlo; DP_Exceptions <= EXC_Mtlo; end
Funct_Mult : begin DP_Hazards <= HAZ_Mult; DP_Exceptions <= EXC_Mult; end
Funct_Multu : begin DP_Hazards <= HAZ_Multu; DP_Exceptions <= EXC_Multu; end
Funct_Nor : begin DP_Hazards <= HAZ_Nor; DP_Exceptions <= EXC_Nor; end
Funct_Or : begin DP_Hazards <= HAZ_Or; DP_Exceptions <= EXC_Or; end
Funct_Sll : begin DP_Hazards <= HAZ_Sll; DP_Exceptions <= EXC_Sll; end
Funct_Sllv : begin DP_Hazards <= HAZ_Sllv; DP_Exceptions <= EXC_Sllv; end
Funct_Slt : begin DP_Hazards <= HAZ_Slt; DP_Exceptions <= EXC_Slt; end
Funct_Sltu : begin DP_Hazards <= HAZ_Sltu; DP_Exceptions <= EXC_Sltu; end
Funct_Sra : begin DP_Hazards <= HAZ_Sra; DP_Exceptions <= EXC_Sra; end
Funct_Srav : begin DP_Hazards <= HAZ_Srav; DP_Exceptions <= EXC_Srav; end
Funct_Srl : begin DP_Hazards <= HAZ_Srl; DP_Exceptions <= EXC_Srl; end
Funct_Srlv : begin DP_Hazards <= HAZ_Srlv; DP_Exceptions <= EXC_Srlv; end
Funct_Sub : begin DP_Hazards <= HAZ_Sub; DP_Exceptions <= EXC_Sub; end
Funct_Subu : begin DP_Hazards <= HAZ_Subu; DP_Exceptions <= EXC_Subu; end
Funct_Syscall : begin DP_Hazards <= HAZ_Syscall; DP_Exceptions <= EXC_Syscall; end
Funct_Teq : begin DP_Hazards <= HAZ_Teq; DP_Exceptions <= EXC_Teq; end
Funct_Tge : begin DP_Hazards <= HAZ_Tge; DP_Exceptions <= EXC_Tge; end
Funct_Tgeu : begin DP_Hazards <= HAZ_Tgeu; DP_Exceptions <= EXC_Tgeu; end
Funct_Tlt : begin DP_Hazards <= HAZ_Tlt; DP_Exceptions <= EXC_Tlt; end
Funct_Tltu : begin DP_Hazards <= HAZ_Tltu; DP_Exceptions <= EXC_Tltu; end
Funct_Tne : begin DP_Hazards <= HAZ_Tne; DP_Exceptions <= EXC_Tne; end
Funct_Xor : begin DP_Hazards <= HAZ_Xor; DP_Exceptions <= EXC_Xor; end
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
endcase
end
// R2-Type
Op_Type_R2 :
begin
case (Funct)
Funct_Clo : begin DP_Hazards <= HAZ_Clo; DP_Exceptions <= EXC_Clo; end
Funct_Clz : begin DP_Hazards <= HAZ_Clz; DP_Exceptions <= EXC_Clz; end
Funct_Madd : begin DP_Hazards <= HAZ_Madd; DP_Exceptions <= EXC_Madd; end
Funct_Maddu : begin DP_Hazards <= HAZ_Maddu; DP_Exceptions <= EXC_Maddu; end
Funct_Msub : begin DP_Hazards <= HAZ_Msub; DP_Exceptions <= EXC_Msub; end
Funct_Msubu : begin DP_Hazards <= HAZ_Msubu; DP_Exceptions <= EXC_Msubu; end
Funct_Mul : begin DP_Hazards <= HAZ_Mul; DP_Exceptions <= EXC_Mul; end
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
endcase
end
// I-Type
Op_Addi : begin DP_Hazards <= HAZ_Addi; DP_Exceptions <= EXC_Addi; end
Op_Addiu : begin DP_Hazards <= HAZ_Addiu; DP_Exceptions <= EXC_Addiu; end
Op_Andi : begin DP_Hazards <= HAZ_Andi; DP_Exceptions <= EXC_Andi; end
Op_Ori : begin DP_Hazards <= HAZ_Ori; DP_Exceptions <= EXC_Ori; end
Op_Pref : begin DP_Hazards <= HAZ_Pref; DP_Exceptions <= EXC_Pref; end
Op_Slti : begin DP_Hazards <= HAZ_Slti; DP_Exceptions <= EXC_Slti; end
Op_Sltiu : begin DP_Hazards <= HAZ_Sltiu; DP_Exceptions <= EXC_Sltiu; end
Op_Xori : begin DP_Hazards <= HAZ_Xori; DP_Exceptions <= EXC_Xori; end
// Jumps
Op_J : begin DP_Hazards <= HAZ_J; DP_Exceptions <= EXC_J; end
Op_Jal : begin DP_Hazards <= HAZ_Jal; DP_Exceptions <= EXC_Jal; end
// Branches and Traps
Op_Type_BI :
begin
case (Rt)
OpRt_Bgez : begin DP_Hazards <= HAZ_Bgez; DP_Exceptions <= EXC_Bgez; end
OpRt_Bgezal : begin DP_Hazards <= HAZ_Bgezal; DP_Exceptions <= EXC_Bgezal; end
OpRt_Bltz : begin DP_Hazards <= HAZ_Bltz; DP_Exceptions <= EXC_Bltz; end
OpRt_Bltzal : begin DP_Hazards <= HAZ_Bltzal; DP_Exceptions <= EXC_Bltzal; end
OpRt_Teqi : begin DP_Hazards <= HAZ_Teqi; DP_Exceptions <= EXC_Teqi; end
OpRt_Tgei : begin DP_Hazards <= HAZ_Tgei; DP_Exceptions <= EXC_Tgei; end
OpRt_Tgeiu : begin DP_Hazards <= HAZ_Tgeiu; DP_Exceptions <= EXC_Tgeiu; end
OpRt_Tlti : begin DP_Hazards <= HAZ_Tlti; DP_Exceptions <= EXC_Tlti; end
OpRt_Tltiu : begin DP_Hazards <= HAZ_Tltiu; DP_Exceptions <= EXC_Tltiu; end
OpRt_Tnei : begin DP_Hazards <= HAZ_Tnei; DP_Exceptions <= EXC_Tnei; end
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
endcase
end
Op_Beq : begin DP_Hazards <= HAZ_Beq; DP_Exceptions <= EXC_Beq; end
Op_Bgtz : begin DP_Hazards <= HAZ_Bgtz; DP_Exceptions <= EXC_Bgtz; end
Op_Blez : begin DP_Hazards <= HAZ_Blez; DP_Exceptions <= EXC_Blez; end
Op_Bne : begin DP_Hazards <= HAZ_Bne; DP_Exceptions <= EXC_Bne; end
// Coprocessor 0
Op_Type_CP0 :
begin
case (Rs)
OpRs_MF : begin DP_Hazards <= HAZ_Mfc0; DP_Exceptions <= EXC_Mfc0; end
OpRs_MT : begin DP_Hazards <= HAZ_Mtc0; DP_Exceptions <= EXC_Mtc0; end
OpRs_ERET : begin DP_Hazards <= (Funct == Funct_ERET) ? DP_Eret : 8'hxx; DP_Exceptions <= EXC_Eret; end
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
endcase
end
// Memory
Op_Lb : begin DP_Hazards <= HAZ_Lb; DP_Exceptions <= EXC_Lb; end
Op_Lbu : begin DP_Hazards <= HAZ_Lbu; DP_Exceptions <= EXC_Lbu; end
Op_Lh : begin DP_Hazards <= HAZ_Lh; DP_Exceptions <= EXC_Lh; end
Op_Lhu : begin DP_Hazards <= HAZ_Lhu; DP_Exceptions <= EXC_Lhu; end
Op_Ll : begin DP_Hazards <= HAZ_Ll; DP_Exceptions <= EXC_Ll; end
Op_Lui : begin DP_Hazards <= HAZ_Lui; DP_Exceptions <= EXC_Lui; end
Op_Lw : begin DP_Hazards <= HAZ_Lw; DP_Exceptions <= EXC_Lw; end
Op_Lwl : begin DP_Hazards <= HAZ_Lwl; DP_Exceptions <= EXC_Lwl; end
Op_Lwr : begin DP_Hazards <= HAZ_Lwr; DP_Exceptions <= EXC_Lwr; end
Op_Sb : begin DP_Hazards <= HAZ_Sb; DP_Exceptions <= EXC_Sb; end
Op_Sc : begin DP_Hazards <= HAZ_Sc; DP_Exceptions <= EXC_Sc; end
Op_Sh : begin DP_Hazards <= HAZ_Sh; DP_Exceptions <= EXC_Sh; end
Op_Sw : begin DP_Hazards <= HAZ_Sw; DP_Exceptions <= EXC_Sw; end
Op_Swl : begin DP_Hazards <= HAZ_Swl; DP_Exceptions <= EXC_Swl; end
Op_Swr : begin DP_Hazards <= HAZ_Swr; DP_Exceptions <= EXC_Swr; end
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
endcase
end
// ALU Assignment
always @(*) begin
if (ID_Stall)
ALUOp <= AluOp_Addu; // Any Op that doesn't write HILO or cause exceptions
else begin
case (OpCode)
Op_Type_R :
begin
case (Funct)
Funct_Add : ALUOp <= AluOp_Add;
Funct_Addu : ALUOp <= AluOp_Addu;
Funct_And : ALUOp <= AluOp_And;
Funct_Div : ALUOp <= AluOp_Div;
Funct_Divu : ALUOp <= AluOp_Divu;
Funct_Jalr : ALUOp <= AluOp_Addu;
Funct_Mfhi : ALUOp <= AluOp_Mfhi;
Funct_Mflo : ALUOp <= AluOp_Mflo;
Funct_Movn : ALUOp <= AluOp_Addu;
Funct_Movz : ALUOp <= AluOp_Addu;
Funct_Mthi : ALUOp <= AluOp_Mthi;
Funct_Mtlo : ALUOp <= AluOp_Mtlo;
Funct_Mult : ALUOp <= AluOp_Mult;
Funct_Multu : ALUOp <= AluOp_Multu;
Funct_Nor : ALUOp <= AluOp_Nor;
Funct_Or : ALUOp <= AluOp_Or;
Funct_Sll : ALUOp <= AluOp_Sll;
Funct_Sllv : ALUOp <= AluOp_Sllv;
Funct_Slt : ALUOp <= AluOp_Slt;
Funct_Sltu : ALUOp <= AluOp_Sltu;
Funct_Sra : ALUOp <= AluOp_Sra;
Funct_Srav : ALUOp <= AluOp_Srav;
Funct_Srl : ALUOp <= AluOp_Srl;
Funct_Srlv : ALUOp <= AluOp_Srlv;
Funct_Sub : ALUOp <= AluOp_Sub;
Funct_Subu : ALUOp <= AluOp_Subu;
Funct_Syscall : ALUOp <= AluOp_Addu;
Funct_Teq : ALUOp <= AluOp_Subu;
Funct_Tge : ALUOp <= AluOp_Slt;
Funct_Tgeu : ALUOp <= AluOp_Sltu;
Funct_Tlt : ALUOp <= AluOp_Slt;
Funct_Tltu : ALUOp <= AluOp_Sltu;
Funct_Tne : ALUOp <= AluOp_Subu;
Funct_Xor : ALUOp <= AluOp_Xor;
default : ALUOp <= AluOp_Addu;
endcase
end
Op_Type_R2 :
begin
case (Funct)
Funct_Clo : ALUOp <= AluOp_Clo;
Funct_Clz : ALUOp <= AluOp_Clz;
Funct_Madd : ALUOp <= AluOp_Madd;
Funct_Maddu : ALUOp <= AluOp_Maddu;
Funct_Msub : ALUOp <= AluOp_Msub;
Funct_Msubu : ALUOp <= AluOp_Msubu;
Funct_Mul : ALUOp <= AluOp_Mul;
default : ALUOp <= AluOp_Addu;
endcase
end
Op_Type_BI :
begin
case (Rt)
OpRt_Teqi : ALUOp <= AluOp_Subu;
OpRt_Tgei : ALUOp <= AluOp_Slt;
OpRt_Tgeiu : ALUOp <= AluOp_Sltu;
OpRt_Tlti : ALUOp <= AluOp_Slt;
OpRt_Tltiu : ALUOp <= AluOp_Sltu;
OpRt_Tnei : ALUOp <= AluOp_Subu;
default : ALUOp <= AluOp_Addu; // Branches don't matter.
endcase
end
Op_Type_CP0 : ALUOp <= AluOp_Addu;
Op_Addi : ALUOp <= AluOp_Add;
Op_Addiu : ALUOp <= AluOp_Addu;
Op_Andi : ALUOp <= AluOp_And;
Op_Jal : ALUOp <= AluOp_Addu;
Op_Lb : ALUOp <= AluOp_Addu;
Op_Lbu : ALUOp <= AluOp_Addu;
Op_Lh : ALUOp <= AluOp_Addu;
Op_Lhu : ALUOp <= AluOp_Addu;
Op_Ll : ALUOp <= AluOp_Addu;
Op_Lui : ALUOp <= AluOp_Sllc;
Op_Lw : ALUOp <= AluOp_Addu;
Op_Lwl : ALUOp <= AluOp_Addu;
Op_Lwr : ALUOp <= AluOp_Addu;
Op_Ori : ALUOp <= AluOp_Or;
Op_Sb : ALUOp <= AluOp_Addu;
Op_Sc : ALUOp <= AluOp_Addu; // XXX Needs HW implement
Op_Sh : ALUOp <= AluOp_Addu;
Op_Slti : ALUOp <= AluOp_Slt;
Op_Sltiu : ALUOp <= AluOp_Sltu;
Op_Sw : ALUOp <= AluOp_Addu;
Op_Swl : ALUOp <= AluOp_Addu;
Op_Swr : ALUOp <= AluOp_Addu;
Op_Xori : ALUOp <= AluOp_Xor;
default : ALUOp <= AluOp_Addu;
endcase
end
end
/***
These remaining options cover portions of the datapath that are not
controlled directly by the datapath bits. Note that some refer to bits of
the opcode or other fields, which breaks the otherwise fully-abstracted view
of instruction encodings. Make sure when adding custom instructions that
no false positives/negatives are generated here.
***/
// Branch Detection: Options are mutually exclusive.
assign Branch_EQ = OpCode[2] & ~OpCode[1] & ~OpCode[0] & Cmp_EQ;
assign Branch_GTZ = OpCode[2] & OpCode[1] & OpCode[0] & Cmp_GZ;
assign Branch_LEZ = OpCode[2] & OpCode[1] & ~OpCode[0] & Cmp_LEZ;
assign Branch_NEQ = OpCode[2] & ~OpCode[1] & OpCode[0] & ~Cmp_EQ;
assign Branch_GEZ = ~OpCode[2] & Rt[0] & Cmp_GEZ;
assign Branch_LTZ = ~OpCode[2] & ~Rt[0] & Cmp_LZ;
assign Branch = Branch_EQ | Branch_GTZ | Branch_LEZ | Branch_NEQ | Branch_GEZ | Branch_LTZ;
assign PCSrc[1] = (Datapath[15] & ~Datapath[14]) ? Branch : Datapath[15];
/* In MIPS32, all Branch and Jump operations execute the Branch Delay Slot,
* or next instruction, regardless if the branch is taken or not. The exception
* is the "Branch Likely" instruction group. These are deprecated, however, and not
* implemented here. "IF_Flush" is defined to allow for the cancelation of a
* Branch Delay Slot should these be implemented later.
*/
assign IF_Flush = 0;
// Indicator that next instruction is a Branch Delay Slot.
assign NextIsDelay = Datapath[15] | Datapath[14];
// Sign- or Zero-Extension Control. The only ops that require zero-extension are
// Andi, Ori, and Xori. The following also zero-extends 'lui', however it does not alter the effect of lui.
assign SignExtend = (OpCode[5:2] != 4'b0011);
// Move Conditional
assign Movn = Movc & Funct[0];
assign Movz = Movc & ~Funct[0];
// Coprocessor 0 (Mfc0, Mtc0) control signals.
assign Mfc0 = ((OpCode == Op_Type_CP0) && (Rs == OpRs_MF));
assign Mtc0 = ((OpCode == Op_Type_CP0) && (Rs == OpRs_MT));
assign Eret = ((OpCode == Op_Type_CP0) && (Rs == OpRs_ERET) && (Funct == Funct_ERET));
// Coprocessor 1,2,3 accesses (not implemented)
assign CP1 = (OpCode == Op_Type_CP1);
assign CP2 = (OpCode == Op_Type_CP2);
assign CP3 = (OpCode == Op_Type_CP3);
// Exceptions found in ID
assign EXC_Sys = ((OpCode == Op_Type_R) && (Funct == Funct_Syscall));
assign EXC_Bp = ((OpCode == Op_Type_R) && (Funct == Funct_Break));
// Unaligned Memory Accesses (lwl, lwr, swl, swr)
assign Unaligned_Mem = OpCode[5] & ~OpCode[4] & OpCode[1] & ~OpCode[0];
assign Left = Unaligned_Mem & ~OpCode[2];
assign Right = Unaligned_Mem & OpCode[2];
// TODO: Reserved Instruction Exception must still be implemented
assign EXC_RI = 0;
endmodule

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`timescale 1ns / 1ns
/*
* File : Divide.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Neil Russell
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 6-Nov-2012 NJR Initial design.
*
* Description:
* A multi-cycle 32-bit divider.
*
* On any cycle that one of OP_div or OP_divu are true, the Dividend and
* Divisor will be captured and a multi-cycle divide operation initiated.
* Stall will go true on the next cycle and the first cycle of the divide
* operation completed. After some time (about 32 cycles), Stall will go
* false on the same cycle that the result becomes valid. OP_div or OP_divu
* will abort any currently running divide operation and initiate a new one.
*/
module Divide(
input clock,
input reset,
input OP_div, // True to initiate a signed divide
input OP_divu, // True to initiate an unsigned divide
input [31:0] Dividend,
input [31:0] Divisor,
output [31:0] Quotient,
output [31:0] Remainder,
output Stall // True while calculating
);
reg active; // True if the divider is running
reg neg; // True if the result will be negative
reg [4:0] cycle; // Number of cycles to go
reg [31:0] result; // Begin with dividend, end with quotient
reg [31:0] denom; // Divisor
reg [31:0] work; // Running remainder
// Calculate the current digit
wire [32:0] sub = { work[30:0], result[31] } - denom;
// Send the results to our master
assign Quotient = !neg ? result : -result;
assign Remainder = work;
assign Stall = active;
// The state machine
always @(posedge clock) begin
if (reset) begin
active <= 0;
neg <= 0;
cycle <= 0;
result <= 0;
denom <= 0;
work <= 0;
end
else begin
if (OP_div) begin
// Set up for a signed divide. Remember the resulting sign,
// and make the operands positive.
cycle <= 5'd31;
result <= (Dividend[31] == 0) ? Dividend : -Dividend;
denom <= (Divisor[31] == 0) ? Divisor : -Divisor;
work <= 32'b0;
neg <= Dividend[31] ^ Divisor[31];
active <= 1;
end
else if (OP_divu) begin
// Set up for an unsigned divide.
cycle <= 5'd31;
result <= Dividend;
denom <= Divisor;
work <= 32'b0;
neg <= 0;
active <= 1;
end
else if (active) begin
// Run an iteration of the divide.
if (sub[32] == 0) begin
work <= sub[31:0];
result <= {result[30:0], 1'b1};
end
else begin
work <= {work[30:0], result[31]};
result <= {result[30:0], 1'b0};
end
if (cycle == 0) begin
active <= 0;
end
cycle <= cycle - 5'd1;
end
end
end
endmodule

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`timescale 1ns / 1ps
/*
* File : EXMEM_Stage.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 9-Jun-2011 GEA Initial design.
* 2.0 26-Jul-2012 GEA Many updates have been made.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The Pipeline Register to bridge the Execute and Memory stages.
*/
module EXMEM_Stage(
input clock,
input reset,
input EX_Flush,
input EX_Stall,
input M_Stall,
// Control Signals
input EX_Movn,
input EX_Movz,
input EX_BZero,
input EX_RegWrite, // Future Control to WB
input EX_MemtoReg, // Future Control to WB
input EX_ReverseEndian,
input EX_LLSC,
input EX_MemRead,
input EX_MemWrite,
input EX_MemByte,
input EX_MemHalf,
input EX_MemSignExtend,
input EX_Left,
input EX_Right,
// Exception Control/Info
input EX_KernelMode,
input [31:0] EX_RestartPC,
input EX_IsBDS,
input EX_Trap,
input EX_TrapCond,
input EX_M_CanErr,
// Data Signals
input [31:0] EX_ALU_Result,
input [31:0] EX_ReadData2,
input [4:0] EX_RtRd,
// ------------------
output reg M_RegWrite,
output reg M_MemtoReg,
output reg M_ReverseEndian,
output reg M_LLSC,
output reg M_MemRead,
output reg M_MemWrite,
output reg M_MemByte,
output reg M_MemHalf,
output reg M_MemSignExtend,
output reg M_Left,
output reg M_Right,
output reg M_KernelMode,
output reg [31:0] M_RestartPC,
output reg M_IsBDS,
output reg M_Trap,
output reg M_TrapCond,
output reg M_M_CanErr,
output reg [31:0] M_ALU_Result,
output reg [31:0] M_ReadData2,
output reg [4:0] M_RtRd
);
/***
The purpose of a pipeline register is to capture data from one pipeline stage
and provide it to the next pipeline stage. This creates at least one clock cycle
of delay, but reduces the combinatorial path length of signals which allows for
higher clock speeds.
All pipeline registers update unless the forward stage is stalled. When this occurs
or when the current stage is being flushed, the forward stage will receive data that
is effectively a NOP and causes nothing to happen throughout the remaining pipeline
traversal. In other words:
A stall masks all control signals to forward stages. A flush permanently clears
control signals to forward stages (but not certain data for exception purposes).
***/
// Mask of RegWrite if a Move Conditional failed.
wire MovcRegWrite = (EX_Movn & ~EX_BZero) | (EX_Movz & EX_BZero);
always @(posedge clock) begin
M_RegWrite <= (reset) ? 0 : ((M_Stall) ? M_RegWrite : ((EX_Stall | EX_Flush) ? 0 : EX_RegWrite));
M_RegWrite <= (reset) ? 0 : ((M_Stall) ? M_RegWrite : ((EX_Stall | EX_Flush) ? 0 : ((EX_Movn | EX_Movz) ? MovcRegWrite : EX_RegWrite)));
M_MemtoReg <= (reset) ? 0 : ((M_Stall) ? M_MemtoReg : EX_MemtoReg);
M_ReverseEndian <= (reset) ? 0 : ((M_Stall) ? M_ReverseEndian : EX_ReverseEndian);
M_LLSC <= (reset) ? 0 : ((M_Stall) ? M_LLSC : EX_LLSC);
M_MemRead <= (reset) ? 0 : ((M_Stall) ? M_MemRead : ((EX_Stall | EX_Flush) ? 0 : EX_MemRead));
M_MemWrite <= (reset) ? 0 : ((M_Stall) ? M_MemWrite : ((EX_Stall | EX_Flush) ? 0 : EX_MemWrite));
M_MemByte <= (reset) ? 0 : ((M_Stall) ? M_MemByte : EX_MemByte);
M_MemHalf <= (reset) ? 0 : ((M_Stall) ? M_MemHalf : EX_MemHalf);
M_MemSignExtend <= (reset) ? 0 : ((M_Stall) ? M_MemSignExtend : EX_MemSignExtend);
M_Left <= (reset) ? 0 : ((M_Stall) ? M_Left : EX_Left);
M_Right <= (reset) ? 0 : ((M_Stall) ? M_Right : EX_Right);
M_KernelMode <= (reset) ? 0 : ((M_Stall) ? M_KernelMode : EX_KernelMode);
M_RestartPC <= (reset) ? 32'b0 : ((M_Stall) ? M_RestartPC : EX_RestartPC);
M_IsBDS <= (reset) ? 0 : ((M_Stall) ? M_IsBDS : EX_IsBDS);
M_Trap <= (reset) ? 0 : ((M_Stall) ? M_Trap : ((EX_Stall | EX_Flush) ? 0 : EX_Trap));
M_TrapCond <= (reset) ? 0 : ((M_Stall) ? M_TrapCond : EX_TrapCond);
M_M_CanErr <= (reset) ? 0 : ((M_Stall) ? M_M_CanErr : ((EX_Stall | EX_Flush) ? 0 : EX_M_CanErr));
M_ALU_Result <= (reset) ? 32'b0 : ((M_Stall) ? M_ALU_Result : EX_ALU_Result);
M_ReadData2 <= (reset) ? 32'b0 : ((M_Stall) ? M_ReadData2 : EX_ReadData2);
M_RtRd <= (reset) ? 5'b0 : ((M_Stall) ? M_RtRd : EX_RtRd);
end
endmodule

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`timescale 1ns / 1ps
/*
* File : Hazard_Detection.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 23-Jul-2011 GEA Initial design.
* 2.0 26-May-2012 GEA Release version with CP0.
* 2.01 1-Nov-2012 GEA Fixed issue with Jal.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* Hazard Detection and Forward Control. This is the glue that allows a
* pipelined processor to operate efficiently and correctly in the presence
* of data, structural, and control hazards. For each pipeline stage, it
* detects whether that stage requires data that is still in the pipeline,
* and whether that data may be forwarded or if the pipeline must be stalled.
*
* This module is heavily commented. Read below for more information.
*/
module Hazard_Detection(
input [7:0] DP_Hazards,
input [4:0] ID_Rs,
input [4:0] ID_Rt,
input [4:0] EX_Rs,
input [4:0] EX_Rt,
input [4:0] EX_RtRd,
input [4:0] MEM_RtRd,
input [4:0] WB_RtRd,
input EX_Link,
input EX_RegWrite,
input MEM_RegWrite,
input WB_RegWrite,
input MEM_MemRead,
input MEM_MemWrite, // Needed for Store Conditional which writes to a register
input InstMem_Read,
input InstMem_Ready,
input Mfc0, // Using fwd mux; not part of haz/fwd.
input IF_Exception_Stall,
input ID_Exception_Stall,
input EX_Exception_Stall,
input EX_ALU_Stall,
input M_Stall_Controller, // Determined by data memory controller
output IF_Stall,
output ID_Stall,
output EX_Stall,
output M_Stall,
output WB_Stall,
output [1:0] ID_RsFwdSel,
output [1:0] ID_RtFwdSel,
output [1:0] EX_RsFwdSel,
output [1:0] EX_RtFwdSel,
output M_WriteDataFwdSel
);
/* Hazard and Forward Detection
*
* Most instructions read from one or more registers. Normally this occurs in
* the ID stage. However, frequently the register file in the ID stage is stale
* when one or more forward stages in the pipeline (EX, MEM, or WB) contains
* an instruction which will eventually update it but has not yet done so.
*
* A hazard condition is created when a forward pipeline stage is set to write
* the same register that a current pipeline stage (e.g. in ID) needs to read.
* The solution is to stall the current stage (and effectively all stages behind
* it) or bypass (forward) the data from forward stages. Fortunately forwarding
* works for most combinations of instructions.
*
* Hazard and Forward conditions are handled based on two simple rules:
* "Wants" and "Needs." If an instruction "wants" data in a certain pipeline
* stage, and that data is available further along in the pipeline, it will
* be forwarded. If it "needs" data and the data is not yet available for forwarding,
* the pipeline stage stalls. If it does not want or need data in a certain
* stage, forwarding is disabled and a stall will not occur. This is important
* for instructions which insert custom data, such as jal or movz.
*
* Currently, "Want" and "Need" conditions are defined for both Rs data and Rt
* data (the two read registers in MIPS), and these conditions exist in the
* ID and EX pipeline stages. This is a total of eight condition bits.
*
* A unique exception exists with Store instructions, which don't need the
* "Rt" data until the MEM stage. Because data doesn't change in WB, and WB
* is the only stage following MEM, forwarding is *always* possible from
* WB to Mem. This unit handles this situation, and a condition bit is not
* needed.
*
* When data is needed from the MEM stage by a previous stage (ID or EX), the
* decision to forward or stall is based on whether MEM is accessing memory
* (stall) or not (forward). Normally store instructions don't write to registers
* and thus are never needed for a data dependence, so the signal 'MEM_MemRead'
* is sufficient to determine. Because of the Store Conditional instruction,
* however, 'MEM_MemWrite' must also be considered because it writes to a register.
*
*/
wire WantRsByID, NeedRsByID, WantRtByID, NeedRtByID, WantRsByEX, NeedRsByEX, WantRtByEX, NeedRtByEX;
assign WantRsByID = DP_Hazards[7];
assign NeedRsByID = DP_Hazards[6];
assign WantRtByID = DP_Hazards[5];
assign NeedRtByID = DP_Hazards[4];
assign WantRsByEX = DP_Hazards[3];
assign NeedRsByEX = DP_Hazards[2];
assign WantRtByEX = DP_Hazards[1];
assign NeedRtByEX = DP_Hazards[0];
// Trick allowed by RegDst = 0 which gives Rt. MEM_Rt is only used on
// Data Memory write operations (stores), and RegWrite is always 0 in this case.
wire [4:0] MEM_Rt = MEM_RtRd;
// Forwarding should not happen when the src/dst register is $zero
wire EX_RtRd_NZ = (EX_RtRd != 5'b00000);
wire MEM_RtRd_NZ = (MEM_RtRd != 5'b00000);
wire WB_RtRd_NZ = (WB_RtRd != 5'b00000);
// ID Dependencies
wire Rs_IDEX_Match = (ID_Rs == EX_RtRd) & EX_RtRd_NZ & (WantRsByID | NeedRsByID) & EX_RegWrite;
wire Rt_IDEX_Match = (ID_Rt == EX_RtRd) & EX_RtRd_NZ & (WantRtByID | NeedRtByID) & EX_RegWrite;
wire Rs_IDMEM_Match = (ID_Rs == MEM_RtRd) & MEM_RtRd_NZ & (WantRsByID | NeedRsByID) & MEM_RegWrite;
wire Rt_IDMEM_Match = (ID_Rt == MEM_RtRd) & MEM_RtRd_NZ & (WantRtByID | NeedRtByID) & MEM_RegWrite;
wire Rs_IDWB_Match = (ID_Rs == WB_RtRd) & WB_RtRd_NZ & (WantRsByID | NeedRsByID) & WB_RegWrite;
wire Rt_IDWB_Match = (ID_Rt == WB_RtRd) & WB_RtRd_NZ & (WantRtByID | NeedRtByID) & WB_RegWrite;
// EX Dependencies
wire Rs_EXMEM_Match = (EX_Rs == MEM_RtRd) & MEM_RtRd_NZ & (WantRsByEX | NeedRsByEX) & MEM_RegWrite;
wire Rt_EXMEM_Match = (EX_Rt == MEM_RtRd) & MEM_RtRd_NZ & (WantRtByEX | NeedRtByEX) & MEM_RegWrite;
wire Rs_EXWB_Match = (EX_Rs == WB_RtRd) & WB_RtRd_NZ & (WantRsByEX | NeedRsByEX) & WB_RegWrite;
wire Rt_EXWB_Match = (EX_Rt == WB_RtRd) & WB_RtRd_NZ & (WantRtByEX | NeedRtByEX) & WB_RegWrite;
// MEM Dependencies
wire Rt_MEMWB_Match = (MEM_Rt == WB_RtRd) & WB_RtRd_NZ & WB_RegWrite;
// ID needs data from EX : Stall
wire ID_Stall_1 = (Rs_IDEX_Match & NeedRsByID);
wire ID_Stall_2 = (Rt_IDEX_Match & NeedRtByID);
// ID needs data from MEM : Stall if mem access
wire ID_Stall_3 = (Rs_IDMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRsByID);
wire ID_Stall_4 = (Rt_IDMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRtByID);
// ID wants data from MEM : Forward if not mem access
wire ID_Fwd_1 = (Rs_IDMEM_Match & ~(MEM_MemRead | MEM_MemWrite));
wire ID_Fwd_2 = (Rt_IDMEM_Match & ~(MEM_MemRead | MEM_MemWrite));
// ID wants/needs data from WB : Forward
wire ID_Fwd_3 = (Rs_IDWB_Match);
wire ID_Fwd_4 = (Rt_IDWB_Match);
// EX needs data from MEM : Stall if mem access
wire EX_Stall_1 = (Rs_EXMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRsByEX);
wire EX_Stall_2 = (Rt_EXMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRtByEX);
// EX wants data from MEM : Forward if not mem access
wire EX_Fwd_1 = (Rs_EXMEM_Match & ~(MEM_MemRead | MEM_MemWrite));
wire EX_Fwd_2 = (Rt_EXMEM_Match & ~(MEM_MemRead | MEM_MemWrite));
// EX wants/needs data from WB : Forward
wire EX_Fwd_3 = (Rs_EXWB_Match);
wire EX_Fwd_4 = (Rt_EXWB_Match);
// MEM needs data from WB : Forward
wire MEM_Fwd_1 = (Rt_MEMWB_Match);
// Stalls and Control Flow Final Assignments
assign WB_Stall = M_Stall;
assign M_Stall = IF_Stall | M_Stall_Controller;
assign EX_Stall = (EX_Stall_1 | EX_Stall_2 | EX_Exception_Stall) | EX_ALU_Stall | M_Stall;
assign ID_Stall = (ID_Stall_1 | ID_Stall_2 | ID_Stall_3 | ID_Stall_4 | ID_Exception_Stall) | EX_Stall;
assign IF_Stall = InstMem_Read | InstMem_Ready | IF_Exception_Stall;
// Forwarding Control Final Assignments
assign ID_RsFwdSel = (ID_Fwd_1) ? 2'b01 : ((ID_Fwd_3) ? 2'b10 : 2'b00);
assign ID_RtFwdSel = (Mfc0) ? 2'b11 : ((ID_Fwd_2) ? 2'b01 : ((ID_Fwd_4) ? 2'b10 : 2'b00));
assign EX_RsFwdSel = (EX_Link) ? 2'b11 : ((EX_Fwd_1) ? 2'b01 : ((EX_Fwd_3) ? 2'b10 : 2'b00));
assign EX_RtFwdSel = (EX_Link) ? 2'b11 : ((EX_Fwd_2) ? 2'b01 : ((EX_Fwd_4) ? 2'b10 : 2'b00));
assign M_WriteDataFwdSel = MEM_Fwd_1;
endmodule

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`timescale 1ns / 1ps
/*
* File : IDEX_Stage.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 9-Jun-2011 GEA Initial design.
* 2.0 26-Jul-2012 GEA Many updates have been made.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The Pipeline Register to bridge the Instruction Decode
* and Execute stages.
*/
module IDEX_Stage(
input clock,
input reset,
input ID_Flush,
input ID_Stall,
input EX_Stall,
// Control Signals
input ID_Link,
input ID_RegDst,
input ID_ALUSrcImm,
input [4:0] ID_ALUOp,
input ID_Movn,
input ID_Movz,
input ID_LLSC,
input ID_MemRead,
input ID_MemWrite,
input ID_MemByte,
input ID_MemHalf,
input ID_MemSignExtend,
input ID_Left,
input ID_Right,
input ID_RegWrite,
input ID_MemtoReg,
input ID_ReverseEndian,
// Hazard & Forwarding
input [4:0] ID_Rs,
input [4:0] ID_Rt,
input ID_WantRsByEX,
input ID_NeedRsByEX,
input ID_WantRtByEX,
input ID_NeedRtByEX,
// Exception Control/Info
input ID_KernelMode,
input [31:0] ID_RestartPC,
input ID_IsBDS,
input ID_Trap,
input ID_TrapCond,
input ID_EX_CanErr,
input ID_M_CanErr,
// Data Signals
input [31:0] ID_ReadData1,
input [31:0] ID_ReadData2,
input [16:0] ID_SignExtImm, // ID_Rd, ID_Shamt included here
// ----------------
output reg EX_Link,
output [1:0] EX_LinkRegDst,
output reg EX_ALUSrcImm,
output reg [4:0] EX_ALUOp,
output reg EX_Movn,
output reg EX_Movz,
output reg EX_LLSC,
output reg EX_MemRead,
output reg EX_MemWrite,
output reg EX_MemByte,
output reg EX_MemHalf,
output reg EX_MemSignExtend,
output reg EX_Left,
output reg EX_Right,
output reg EX_RegWrite,
output reg EX_MemtoReg,
output reg EX_ReverseEndian,
output reg [4:0] EX_Rs,
output reg [4:0] EX_Rt,
output reg EX_WantRsByEX,
output reg EX_NeedRsByEX,
output reg EX_WantRtByEX,
output reg EX_NeedRtByEX,
output reg EX_KernelMode,
output reg [31:0] EX_RestartPC,
output reg EX_IsBDS,
output reg EX_Trap,
output reg EX_TrapCond,
output reg EX_EX_CanErr,
output reg EX_M_CanErr,
output reg [31:0] EX_ReadData1,
output reg [31:0] EX_ReadData2,
output [31:0] EX_SignExtImm,
output [4:0] EX_Rd,
output [4:0] EX_Shamt
);
/***
The purpose of a pipeline register is to capture data from one pipeline stage
and provide it to the next pipeline stage. This creates at least one clock cycle
of delay, but reduces the combinatorial path length of signals which allows for
higher clock speeds.
All pipeline registers update unless the forward stage is stalled. When this occurs
or when the current stage is being flushed, the forward stage will receive data that
is effectively a NOP and causes nothing to happen throughout the remaining pipeline
traversal. In other words:
A stall masks all control signals to forward stages. A flush permanently clears
control signals to forward stages (but not certain data for exception purposes).
***/
reg [16:0] EX_SignExtImm_pre;
reg EX_RegDst;
assign EX_LinkRegDst = (EX_Link) ? 2'b10 : ((EX_RegDst) ? 2'b01 : 2'b00);
assign EX_Rd = EX_SignExtImm[15:11];
assign EX_Shamt = EX_SignExtImm[10:6];
assign EX_SignExtImm = (EX_SignExtImm_pre[16]) ? {15'h7fff, EX_SignExtImm_pre[16:0]} : {15'h0000, EX_SignExtImm_pre[16:0]};
always @(posedge clock) begin
EX_Link <= (reset) ? 0 : ((EX_Stall) ? EX_Link : ID_Link);
EX_RegDst <= (reset) ? 0 : ((EX_Stall) ? EX_RegDst : ID_RegDst);
EX_ALUSrcImm <= (reset) ? 0 : ((EX_Stall) ? EX_ALUSrcImm : ID_ALUSrcImm);
EX_ALUOp <= (reset) ? 5'b0 : ((EX_Stall) ? EX_ALUOp : ((ID_Stall | ID_Flush) ? 5'b0 : ID_ALUOp));
EX_Movn <= (reset) ? 0 : ((EX_Stall) ? EX_Movn : ID_Movn);
EX_Movz <= (reset) ? 0 : ((EX_Stall) ? EX_Movz : ID_Movz);
EX_LLSC <= (reset) ? 0 : ((EX_Stall) ? EX_LLSC : ID_LLSC);
EX_MemRead <= (reset) ? 0 : ((EX_Stall) ? EX_MemRead : ((ID_Stall | ID_Flush) ? 0 : ID_MemRead));
EX_MemWrite <= (reset) ? 0 : ((EX_Stall) ? EX_MemWrite : ((ID_Stall | ID_Flush) ? 0 : ID_MemWrite));
EX_MemByte <= (reset) ? 0 : ((EX_Stall) ? EX_MemByte : ID_MemByte);
EX_MemHalf <= (reset) ? 0 : ((EX_Stall) ? EX_MemHalf : ID_MemHalf);
EX_MemSignExtend <= (reset) ? 0 : ((EX_Stall) ? EX_MemSignExtend : ID_MemSignExtend);
EX_Left <= (reset) ? 0 : ((EX_Stall) ? EX_Left : ID_Left);
EX_Right <= (reset) ? 0 : ((EX_Stall) ? EX_Right : ID_Right);
EX_RegWrite <= (reset) ? 0 : ((EX_Stall) ? EX_RegWrite : ((ID_Stall | ID_Flush) ? 0 : ID_RegWrite));
EX_MemtoReg <= (reset) ? 0 : ((EX_Stall) ? EX_MemtoReg : ID_MemtoReg);
EX_ReverseEndian <= (reset) ? 0 : ((EX_Stall) ? EX_ReverseEndian : ID_ReverseEndian);
EX_RestartPC <= (reset) ? 32'b0 : ((EX_Stall) ? EX_RestartPC : ID_RestartPC);
EX_IsBDS <= (reset) ? 0 : ((EX_Stall) ? EX_IsBDS : ID_IsBDS);
EX_Trap <= (reset) ? 0 : ((EX_Stall) ? EX_Trap : ((ID_Stall | ID_Flush) ? 0 : ID_Trap));
EX_TrapCond <= (reset) ? 0 : ((EX_Stall) ? EX_TrapCond : ID_TrapCond);
EX_EX_CanErr <= (reset) ? 0 : ((EX_Stall) ? EX_EX_CanErr : ((ID_Stall | ID_Flush) ? 0 : ID_EX_CanErr));
EX_M_CanErr <= (reset) ? 0 : ((EX_Stall) ? EX_M_CanErr : ((ID_Stall | ID_Flush) ? 0 : ID_M_CanErr));
EX_ReadData1 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData1 : ID_ReadData1);
EX_ReadData2 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData2 : ID_ReadData2);
EX_SignExtImm_pre <= (reset) ? 17'b0 : ((EX_Stall) ? EX_SignExtImm_pre : ID_SignExtImm);
EX_Rs <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rs : ID_Rs);
EX_Rt <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rt : ID_Rt);
EX_WantRsByEX <= (reset) ? 0 : ((EX_Stall) ? EX_WantRsByEX : ((ID_Stall | ID_Flush) ? 0 : ID_WantRsByEX));
EX_NeedRsByEX <= (reset) ? 0 : ((EX_Stall) ? EX_NeedRsByEX : ((ID_Stall | ID_Flush) ? 0 : ID_NeedRsByEX));
EX_WantRtByEX <= (reset) ? 0 : ((EX_Stall) ? EX_WantRtByEX : ((ID_Stall | ID_Flush) ? 0 : ID_WantRtByEX));
EX_NeedRtByEX <= (reset) ? 0 : ((EX_Stall) ? EX_NeedRtByEX : ((ID_Stall | ID_Flush) ? 0 : ID_NeedRtByEX));
EX_KernelMode <= (reset) ? 0 : ((EX_Stall) ? EX_KernelMode : ID_KernelMode);
end
endmodule

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`timescale 1ns / 1ps
/*
* File : IFID_Stage.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 9-Jun-2011 GEA Initial design.
* 2.0 26-Jul-2012 GEA Many updates have been made.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The Pipeline Register to bridge the Instruction Fetch
* and Instruction Decode stages.
*/
module IFID_Stage(
input clock,
input reset,
input IF_Flush,
input IF_Stall,
input ID_Stall,
// Control Signals
input [31:0] IF_Instruction,
// Data Signals
input [31:0] IF_PCAdd4,
input [31:0] IF_PC,
input IF_IsBDS,
// ------------------
output reg [31:0] ID_Instruction,
output reg [31:0] ID_PCAdd4,
output reg [31:0] ID_RestartPC,
output reg ID_IsBDS,
output reg ID_IsFlushed
);
/***
The purpose of a pipeline register is to capture data from one pipeline stage
and provide it to the next pipeline stage. This creates at least one clock cycle
of delay, but reduces the combinatorial path length of signals which allows for
higher clock speeds.
All pipeline registers update unless the forward stage is stalled. When this occurs
or when the current stage is being flushed, the forward stage will receive data that
is effectively a NOP and causes nothing to happen throughout the remaining pipeline
traversal. In other words:
A stall masks all control signals to forward stages. A flush permanently clears
control signals to forward stages (but not certain data for exception purposes).
***/
/***
The signal 'ID_IsFlushed' is needed because of interrupts. Normally, a flushed instruction
is a NOP which will never cause an exception and thus its restart PC will never be needed
or used. However, interrupts are detected in ID and may occur when any instruction, flushed
or not, is in the ID stage. It is an error to save the restart PC of a flushed instruction
since it was never supposed to execute (such as the "delay slot" after ERET or the branch
delay slot after a canceled Branch Likely instruction). A simple way to prevent this is to
pass a signal to ID indicating that its instruction was flushed. Interrupt detection is then
masked when this signal is high, and the interrupt will trigger on the next instruction load to ID.
***/
always @(posedge clock) begin
ID_Instruction <= (reset) ? 32'b0 : ((ID_Stall) ? ID_Instruction : ((IF_Stall | IF_Flush) ? 32'b0 : IF_Instruction));
ID_PCAdd4 <= (reset) ? 32'b0 : ((ID_Stall) ? ID_PCAdd4 : IF_PCAdd4);
ID_IsBDS <= (reset) ? 0 : ((ID_Stall) ? ID_IsBDS : IF_IsBDS);
ID_RestartPC <= (reset) ? 32'b0 : ((ID_Stall | IF_IsBDS) ? ID_RestartPC : IF_PC);
ID_IsFlushed <= (reset) ? 0 : ((ID_Stall) ? ID_IsFlushed : IF_Flush);
end
endmodule

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`timescale 1ns / 1ps
/*
* File : MEMWB_Stage.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 9-Jun-2011 GEA Initial design.
* 2.0 26-Jul-2012 GEA Many updates have been made.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The Pipeline Register to bridge the Memory and Writeback stages.
*/
module MEMWB_Stage(
input clock,
input reset,
input M_Flush,
input M_Stall,
input WB_Stall,
// Control Signals
input M_RegWrite,
input M_MemtoReg,
// Data Signals
input [31:0] M_ReadData,
input [31:0] M_ALU_Result,
input [4:0] M_RtRd,
// ----------------
output reg WB_RegWrite,
output reg WB_MemtoReg,
output reg [31:0] WB_ReadData,
output reg [31:0] WB_ALU_Result,
output reg [4:0] WB_RtRd
);
/***
The purpose of a pipeline register is to capture data from one pipeline stage
and provide it to the next pipeline stage. This creates at least one clock cycle
of delay, but reduces the combinatorial path length of signals which allows for
higher clock speeds.
All pipeline registers update unless the forward stage is stalled. When this occurs
or when the current stage is being flushed, the forward stage will receive data that
is effectively a NOP and causes nothing to happen throughout the remaining pipeline
traversal. In other words:
A stall masks all control signals to forward stages. A flush permanently clears
control signals to forward stages (but not certain data for exception purposes).
Since WB is the final stage in the pipeline, it would normally never stall.
However, because the MEM stage may be using data forwarded from WB, WB must stall
when MEM is stalled. If it didn't, the forward data would not be preserved. If
the processor didn't forward any data, a stall would not be needed.
In practice, the only time WB stalls is when forwarding for a Lw->Sw sequence, since
MEM doesn't need the data until its stage, but it does not latch the forwarded data.
This means WB_Stall is probably identical to M_Stall. There is no speed difference by
allowing WB to stall.
***/
always @(posedge clock) begin
WB_RegWrite <= (reset) ? 0 : ((WB_Stall) ? WB_RegWrite : ((M_Stall | M_Flush) ? 0 : M_RegWrite));
WB_MemtoReg <= (reset) ? 0 : ((WB_Stall) ? WB_MemtoReg : M_MemtoReg);
WB_ReadData <= (reset) ? 32'b0 : ((WB_Stall) ? WB_ReadData : M_ReadData);
WB_ALU_Result <= (reset) ? 32'b0 : ((WB_Stall) ? WB_ALU_Result : M_ALU_Result);
WB_RtRd <= (reset) ? 5'b0 : ((WB_Stall) ? WB_RtRd : M_RtRd);
end
endmodule

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/*
* File : MIPS_Parameters.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 26-May-2012 GEA Release version.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* Provides a language abstraction for the MIPS32-specific op-codes and
* the processor-specific datapath, hazard, and exception bits which
* control the processor. These parameter names are used extensively
* throughout the processor HDL modules.
*/
/*** Exception Vector Locations ***
When the CPU powers up or is reset, it will begin execution at 'EXC_Vector_Base_Reset'.
All other exceptions are the sum of a base address and offset:
- The base address is either a bootstrap or normal value. It is controlled by
the 'BEV' bit in the CP0 'Status' register. Both base addresses can be mapped to
the same location.
- The offset address is either a standard offset (which is always used for
non-interrupt general exceptions in this processor because it lacks TLB Refill
and Cache errors), or a special interrupt-only offset for interrupts, which is
enabled with the 'IV' bit in the CP0 'Cause' register.
Current Setup:
General exceptions go to 0x0. Interrupts go to 0x8. Booting starts at 0x10.
*/
parameter [31:0] EXC_Vector_Base_Reset = 32'h0000_0010; // MIPS Standard is 0xBFC0_0000
parameter [31:0] EXC_Vector_Base_Other_NoBoot = 32'h0000_0000; // MIPS Standard is 0x8000_0000
parameter [31:0] EXC_Vector_Base_Other_Boot = 32'h0000_0000; // MIPS Standard is 0xBFC0_0200
parameter [31:0] EXC_Vector_Offset_General = 32'h0000_0000; // MIPS Standard is 0x0000_0180
parameter [31:0] EXC_Vector_Offset_Special = 32'h0000_0008; // MIPS Standard is 0x0000_0200
/*** Kernel/User Memory Areas ***
Kernel memory starts at address 0x0. User memory starts at 'UMem_Lower' and extends to
the end of the address space.
A distinction is made to protect against accesses to kernel memory while the processor
is in user mode. Lacking MMU hardware, these addresses are physical, not virtual.
This simple two-part division of the address space can be extended almost arbitrarily
in the Data Memory Controller. Note that there is currently no user/kernel space check
for the Instruction Memory, because it is assumed that instructions are in the kernel space.
*/
parameter [31:0] UMem_Lower = 32'h08000000;
/*** Processor Endianness ***
The MIPS Configuration Register (CP0 Register 16 Select 0) specifies the processor's
endianness. A processor in user mode may switch to reverse endianness, which will be
the opposite of this parameter.
*/
parameter Big_Endian = 1;
/*** Encodings for MIPS32 Release 1 Architecture ***/
/* Op Code Categories */
parameter [5:0] Op_Type_R = 6'b00_0000; // Standard R-Type instructions
parameter [5:0] Op_Type_R2 = 6'b01_1100; // Extended R-Like instructions
parameter [5:0] Op_Type_BI = 6'b00_0001; // Branch/Trap extended instructions
parameter [5:0] Op_Type_CP0 = 6'b01_0000; // Coprocessor 0 instructions
parameter [5:0] Op_Type_CP1 = 6'b01_0001; // Coprocessor 1 instructions (not implemented)
parameter [5:0] Op_Type_CP2 = 6'b01_0010; // Coprocessor 2 instructions (not implemented)
parameter [5:0] Op_Type_CP3 = 6'b01_0011; // Coprocessor 3 instructions (not implemented)
// --------------------------------------
parameter [5:0] Op_Add = Op_Type_R;
parameter [5:0] Op_Addi = 6'b00_1000;
parameter [5:0] Op_Addiu = 6'b00_1001;
parameter [5:0] Op_Addu = Op_Type_R;
parameter [5:0] Op_And = Op_Type_R;
parameter [5:0] Op_Andi = 6'b00_1100;
parameter [5:0] Op_Beq = 6'b00_0100;
parameter [5:0] Op_Bgez = Op_Type_BI;
parameter [5:0] Op_Bgezal = Op_Type_BI;
parameter [5:0] Op_Bgtz = 6'b00_0111;
parameter [5:0] Op_Blez = 6'b00_0110;
parameter [5:0] Op_Bltz = Op_Type_BI;
parameter [5:0] Op_Bltzal = Op_Type_BI;
parameter [5:0] Op_Bne = 6'b00_0101;
parameter [5:0] Op_Break = Op_Type_R;
parameter [5:0] Op_Clo = Op_Type_R2;
parameter [5:0] Op_Clz = Op_Type_R2;
parameter [5:0] Op_Div = Op_Type_R;
parameter [5:0] Op_Divu = Op_Type_R;
parameter [5:0] Op_Eret = Op_Type_CP0;
parameter [5:0] Op_J = 6'b00_0010;
parameter [5:0] Op_Jal = 6'b00_0011;
parameter [5:0] Op_Jalr = Op_Type_R;
parameter [5:0] Op_Jr = Op_Type_R;
parameter [5:0] Op_Lb = 6'b10_0000;
parameter [5:0] Op_Lbu = 6'b10_0100;
parameter [5:0] Op_Lh = 6'b10_0001;
parameter [5:0] Op_Lhu = 6'b10_0101;
parameter [5:0] Op_Ll = 6'b11_0000;
parameter [5:0] Op_Lui = 6'b00_1111;
parameter [5:0] Op_Lw = 6'b10_0011;
parameter [5:0] Op_Lwl = 6'b10_0010;
parameter [5:0] Op_Lwr = 6'b10_0110;
parameter [5:0] Op_Madd = Op_Type_R2;
parameter [5:0] Op_Maddu = Op_Type_R2;
parameter [5:0] Op_Mfc0 = Op_Type_CP0;
parameter [5:0] Op_Mfhi = Op_Type_R;
parameter [5:0] Op_Mflo = Op_Type_R;
parameter [5:0] Op_Movn = Op_Type_R;
parameter [5:0] Op_Movz = Op_Type_R;
parameter [5:0] Op_Msub = Op_Type_R2;
parameter [5:0] Op_Msubu = Op_Type_R2;
parameter [5:0] Op_Mtc0 = Op_Type_CP0;
parameter [5:0] Op_Mthi = Op_Type_R;
parameter [5:0] Op_Mtlo = Op_Type_R;
parameter [5:0] Op_Mul = Op_Type_R2;
parameter [5:0] Op_Mult = Op_Type_R;
parameter [5:0] Op_Multu = Op_Type_R;
parameter [5:0] Op_Nor = Op_Type_R;
parameter [5:0] Op_Or = Op_Type_R;
parameter [5:0] Op_Ori = 6'b00_1101;
parameter [5:0] Op_Pref = 6'b11_0011; // Prefetch does nothing in this implementation.
parameter [5:0] Op_Sb = 6'b10_1000;
parameter [5:0] Op_Sc = 6'b11_1000;
parameter [5:0] Op_Sh = 6'b10_1001;
parameter [5:0] Op_Sll = Op_Type_R;
parameter [5:0] Op_Sllv = Op_Type_R;
parameter [5:0] Op_Slt = Op_Type_R;
parameter [5:0] Op_Slti = 6'b00_1010;
parameter [5:0] Op_Sltiu = 6'b00_1011;
parameter [5:0] Op_Sltu = Op_Type_R;
parameter [5:0] Op_Sra = Op_Type_R;
parameter [5:0] Op_Srav = Op_Type_R;
parameter [5:0] Op_Srl = Op_Type_R;
parameter [5:0] Op_Srlv = Op_Type_R;
parameter [5:0] Op_Sub = Op_Type_R;
parameter [5:0] Op_Subu = Op_Type_R;
parameter [5:0] Op_Sw = 6'b10_1011;
parameter [5:0] Op_Swl = 6'b10_1010;
parameter [5:0] Op_Swr = 6'b10_1110;
parameter [5:0] Op_Syscall = Op_Type_R;
parameter [5:0] Op_Teq = Op_Type_R;
parameter [5:0] Op_Teqi = Op_Type_BI;
parameter [5:0] Op_Tge = Op_Type_R;
parameter [5:0] Op_Tgei = Op_Type_BI;
parameter [5:0] Op_Tgeiu = Op_Type_BI;
parameter [5:0] Op_Tgeu = Op_Type_R;
parameter [5:0] Op_Tlt = Op_Type_R;
parameter [5:0] Op_Tlti = Op_Type_BI;
parameter [5:0] Op_Tltiu = Op_Type_BI;
parameter [5:0] Op_Tltu = Op_Type_R;
parameter [5:0] Op_Tne = Op_Type_R;
parameter [5:0] Op_Tnei = Op_Type_BI;
parameter [5:0] Op_Xor = Op_Type_R;
parameter [5:0] Op_Xori = 6'b00_1110;
/* Op Code Rt fields for Branches & Traps */
parameter [4:0] OpRt_Bgez = 5'b00001;
parameter [4:0] OpRt_Bgezal = 5'b10001;
parameter [4:0] OpRt_Bltz = 5'b00000;
parameter [4:0] OpRt_Bltzal = 5'b10000;
parameter [4:0] OpRt_Teqi = 5'b01100;
parameter [4:0] OpRt_Tgei = 5'b01000;
parameter [4:0] OpRt_Tgeiu = 5'b01001;
parameter [4:0] OpRt_Tlti = 5'b01010;
parameter [4:0] OpRt_Tltiu = 5'b01011;
parameter [4:0] OpRt_Tnei = 5'b01110;
/* Op Code Rs fields for Coprocessors */
parameter [4:0] OpRs_MF = 5'b00000;
parameter [4:0] OpRs_MT = 5'b00100;
/* Special handling for ERET */
parameter [4:0] OpRs_ERET = 5'b10000;
parameter [5:0] Funct_ERET = 6'b011000;
/* Function Codes for R-Type Op Codes */
parameter [5:0] Funct_Add = 6'b10_0000;
parameter [5:0] Funct_Addu = 6'b10_0001;
parameter [5:0] Funct_And = 6'b10_0100;
parameter [5:0] Funct_Break = 6'b00_1101;
parameter [5:0] Funct_Clo = 6'b10_0001; // same as Addu
parameter [5:0] Funct_Clz = 6'b10_0000; // same as Add
parameter [5:0] Funct_Div = 6'b01_1010;
parameter [5:0] Funct_Divu = 6'b01_1011;
parameter [5:0] Funct_Jr = 6'b00_1000;
parameter [5:0] Funct_Jalr = 6'b00_1001;
parameter [5:0] Funct_Madd = 6'b00_0000;
parameter [5:0] Funct_Maddu = 6'b00_0001;
parameter [5:0] Funct_Mfhi = 6'b01_0000;
parameter [5:0] Funct_Mflo = 6'b01_0010;
parameter [5:0] Funct_Movn = 6'b00_1011;
parameter [5:0] Funct_Movz = 6'b00_1010;
parameter [5:0] Funct_Msub = 6'b00_0100; // same as Sllv
parameter [5:0] Funct_Msubu = 6'b00_0101;
parameter [5:0] Funct_Mthi = 6'b01_0001;
parameter [5:0] Funct_Mtlo = 6'b01_0011;
parameter [5:0] Funct_Mul = 6'b00_0010; // same as Srl
parameter [5:0] Funct_Mult = 6'b01_1000;
parameter [5:0] Funct_Multu = 6'b01_1001;
parameter [5:0] Funct_Nor = 6'b10_0111;
parameter [5:0] Funct_Or = 6'b10_0101;
parameter [5:0] Funct_Sll = 6'b00_0000;
parameter [5:0] Funct_Sllv = 6'b00_0100;
parameter [5:0] Funct_Slt = 6'b10_1010;
parameter [5:0] Funct_Sltu = 6'b10_1011;
parameter [5:0] Funct_Sra = 6'b00_0011;
parameter [5:0] Funct_Srav = 6'b00_0111;
parameter [5:0] Funct_Srl = 6'b00_0010;
parameter [5:0] Funct_Srlv = 6'b00_0110;
parameter [5:0] Funct_Sub = 6'b10_0010;
parameter [5:0] Funct_Subu = 6'b10_0011;
parameter [5:0] Funct_Syscall = 6'b00_1100;
parameter [5:0] Funct_Teq = 6'b11_0100;
parameter [5:0] Funct_Tge = 6'b11_0000;
parameter [5:0] Funct_Tgeu = 6'b11_0001;
parameter [5:0] Funct_Tlt = 6'b11_0010;
parameter [5:0] Funct_Tltu = 6'b11_0011;
parameter [5:0] Funct_Tne = 6'b11_0110;
parameter [5:0] Funct_Xor = 6'b10_0110;
/* ALU Operations (Implementation) */
parameter [4:0] AluOp_Add = 5'd1;
parameter [4:0] AluOp_Addu = 5'd0;
parameter [4:0] AluOp_And = 5'd2;
parameter [4:0] AluOp_Clo = 5'd3;
parameter [4:0] AluOp_Clz = 5'd4;
parameter [4:0] AluOp_Div = 5'd5;
parameter [4:0] AluOp_Divu = 5'd6;
parameter [4:0] AluOp_Madd = 5'd7;
parameter [4:0] AluOp_Maddu = 5'd8;
parameter [4:0] AluOp_Mfhi = 5'd9;
parameter [4:0] AluOp_Mflo = 5'd10;
parameter [4:0] AluOp_Msub = 5'd13;
parameter [4:0] AluOp_Msubu = 5'd14;
parameter [4:0] AluOp_Mthi = 5'd11;
parameter [4:0] AluOp_Mtlo = 5'd12;
parameter [4:0] AluOp_Mul = 5'd15;
parameter [4:0] AluOp_Mult = 5'd16;
parameter [4:0] AluOp_Multu = 5'd17;
parameter [4:0] AluOp_Nor = 5'd18;
parameter [4:0] AluOp_Or = 5'd19;
parameter [4:0] AluOp_Sll = 5'd20;
parameter [4:0] AluOp_Sllc = 5'd21; // Move this if another AluOp is needed
parameter [4:0] AluOp_Sllv = 5'd22;
parameter [4:0] AluOp_Slt = 5'd23;
parameter [4:0] AluOp_Sltu = 5'd24;
parameter [4:0] AluOp_Sra = 5'd25;
parameter [4:0] AluOp_Srav = 5'd26;
parameter [4:0] AluOp_Srl = 5'd27;
parameter [4:0] AluOp_Srlv = 5'd28;
parameter [4:0] AluOp_Sub = 5'd29;
parameter [4:0] AluOp_Subu = 5'd30;
parameter [4:0] AluOp_Xor = 5'd31;
// Movc:10->11, Trap:9->10, TrapCond:8->9, RegDst:7->8
/*** Datapath ***
All Signals are Active High. Branching and Jump signals (determined by "PCSrc"),
as well as ALU operation signals ("ALUOp") are handled by the controller and are not found here.
Bit Name Description
------------------------------
15: PCSrc (Instruction Type)
14: 11: Instruction is Jump to Register
10: Instruction is Branch
01: Instruction is Jump to Immediate
00: Instruction does not branch nor jump
13: Link (Link on Branch/Jump)
------------------------------
12: ALUSrc (ALU Source) [0=ALU input B is 2nd register file output; 1=Immediate value]
11: Movc (Conditional Move)
10: Trap (Trap Instruction)
9 : TrapCond (Trap Condition) [0=ALU result is 0; 1=ALU result is not 0]
8 : RegDst (Register File Target) [0=Rt field; 1=Rd field]
------------------------------
7 : LLSC (Load Linked or Store Conditional)
6 : MemRead (Data Memory Read)
5 : MemWrite (Data Memory Write)
4 : MemHalf (Half Word Memory Access)
3 : MemByte (Byte size Memory Access)
2 : MemSignExtend (Sign Extend Read Memory) [0=Zero Extend; 1=Sign Extend]
------------------------------
1 : RegWrite (Register File Write)
0 : MemtoReg (Memory to Register) [0=Register File write data is ALU output; 1=Is Data Memory]
------------------------------
*/
parameter [15:0] DP_None = 16'b000_00000_000000_00; // Instructions which require nothing of the main datapath.
parameter [15:0] DP_RType = 16'b000_00001_000000_10; // Standard R-Type
parameter [15:0] DP_IType = 16'b000_10000_000000_10; // Standard I-Type
parameter [15:0] DP_Branch = 16'b100_00000_000000_00; // Standard Branch
parameter [15:0] DP_BranchLink = 16'b101_00000_000000_10; // Branch and Link
parameter [15:0] DP_HiLoWr = 16'b000_00000_000000_00; // Write to Hi/Lo ALU register (Div,Divu,Mult,Multu,Mthi,Mtlo). Currently 'DP_None'.
parameter [15:0] DP_Jump = 16'b010_00000_000000_00; // Standard Jump
parameter [15:0] DP_JumpLink = 16'b011_00000_000000_10; // Jump and Link
parameter [15:0] DP_JumpLinkReg = 16'b111_00000_000000_10; // Jump and Link Register
parameter [15:0] DP_JumpReg = 16'b110_00000_000000_00; // Jump Register
parameter [15:0] DP_LoadByteS = 16'b000_10000_010011_11; // Load Byte Signed
parameter [15:0] DP_LoadByteU = 16'b000_10000_010010_11; // Load Byte Unsigned
parameter [15:0] DP_LoadHalfS = 16'b000_10000_010101_11; // Load Half Signed
parameter [15:0] DP_LoadHalfU = 16'b000_10000_010100_11; // Load Half Unsigned
parameter [15:0] DP_LoadWord = 16'b000_10000_010000_11; // Load Word
parameter [15:0] DP_ExtWrRt = 16'b000_00000_000000_10; // A DP-external write to Rt
parameter [15:0] DP_ExtWrRd = 16'b000_00001_000000_10; // A DP-external write to Rd
parameter [15:0] DP_Movc = 16'b000_01001_000000_10; // Conditional Move
parameter [15:0] DP_LoadLinked = 16'b000_10000_110000_11; // Load Linked
parameter [15:0] DP_StoreCond = 16'b000_10000_101000_11; // Store Conditional
parameter [15:0] DP_StoreByte = 16'b000_10000_001010_00; // Store Byte
parameter [15:0] DP_StoreHalf = 16'b000_10000_001100_00; // Store Half
parameter [15:0] DP_StoreWord = 16'b000_10000_001000_00; // Store Word
parameter [15:0] DP_TrapRegCNZ = 16'b000_00110_000000_00; // Trap using Rs and Rt, non-zero ALU (Tlt, Tltu, Tne)
parameter [15:0] DP_TrapRegCZ = 16'b000_00100_000000_00; // Trap using RS and Rt, zero ALU (Teq, Tge, Tgeu)
parameter [15:0] DP_TrapImmCNZ = 16'b000_10110_000000_00; // Trap using Rs and Imm, non-zero ALU (Tlti, Tltiu, Tnei)
parameter [15:0] DP_TrapImmCZ = 16'b000_10100_000000_00; // Trap using Rs and Imm, zero ALU (Teqi, Tgei, Tgeiu)
//--------------------------------------------------------
parameter [15:0] DP_Add = DP_RType;
parameter [15:0] DP_Addi = DP_IType;
parameter [15:0] DP_Addiu = DP_IType;
parameter [15:0] DP_Addu = DP_RType;
parameter [15:0] DP_And = DP_RType;
parameter [15:0] DP_Andi = DP_IType;
parameter [15:0] DP_Beq = DP_Branch;
parameter [15:0] DP_Bgez = DP_Branch;
parameter [15:0] DP_Bgezal = DP_BranchLink;
parameter [15:0] DP_Bgtz = DP_Branch;
parameter [15:0] DP_Blez = DP_Branch;
parameter [15:0] DP_Bltz = DP_Branch;
parameter [15:0] DP_Bltzal = DP_BranchLink;
parameter [15:0] DP_Bne = DP_Branch;
parameter [15:0] DP_Break = DP_None;
parameter [15:0] DP_Clo = DP_RType;
parameter [15:0] DP_Clz = DP_RType;
parameter [15:0] DP_Div = DP_HiLoWr;
parameter [15:0] DP_Divu = DP_HiLoWr;
parameter [15:0] DP_Eret = DP_None;
parameter [15:0] DP_J = DP_Jump;
parameter [15:0] DP_Jal = DP_JumpLink;
parameter [15:0] DP_Jalr = DP_JumpLinkReg;
parameter [15:0] DP_Jr = DP_JumpReg;
parameter [15:0] DP_Lb = DP_LoadByteS;
parameter [15:0] DP_Lbu = DP_LoadByteU;
parameter [15:0] DP_Lh = DP_LoadHalfS;
parameter [15:0] DP_Lhu = DP_LoadHalfU;
parameter [15:0] DP_Ll = DP_LoadLinked;
parameter [15:0] DP_Lui = DP_IType;
parameter [15:0] DP_Lw = DP_LoadWord;
parameter [15:0] DP_Lwl = DP_LoadWord;
parameter [15:0] DP_Lwr = DP_LoadWord;
parameter [15:0] DP_Madd = DP_HiLoWr;
parameter [15:0] DP_Maddu = DP_HiLoWr;
parameter [15:0] DP_Mfc0 = DP_ExtWrRt;
parameter [15:0] DP_Mfhi = DP_ExtWrRd;
parameter [15:0] DP_Mflo = DP_ExtWrRd;
parameter [15:0] DP_Movn = DP_Movc;
parameter [15:0] DP_Movz = DP_Movc;
parameter [15:0] DP_Msub = DP_HiLoWr;
parameter [15:0] DP_Msubu = DP_HiLoWr;
parameter [15:0] DP_Mtc0 = DP_None;
parameter [15:0] DP_Mthi = DP_HiLoWr;
parameter [15:0] DP_Mtlo = DP_HiLoWr;
parameter [15:0] DP_Mul = DP_RType;
parameter [15:0] DP_Mult = DP_HiLoWr;
parameter [15:0] DP_Multu = DP_HiLoWr;
parameter [15:0] DP_Nor = DP_RType;
parameter [15:0] DP_Or = DP_RType;
parameter [15:0] DP_Ori = DP_IType;
parameter [15:0] DP_Pref = DP_None; // Not Implemented
parameter [15:0] DP_Sb = DP_StoreByte;
parameter [15:0] DP_Sc = DP_StoreCond;
parameter [15:0] DP_Sh = DP_StoreHalf;
parameter [15:0] DP_Sll = DP_RType;
parameter [15:0] DP_Sllv = DP_RType;
parameter [15:0] DP_Slt = DP_RType;
parameter [15:0] DP_Slti = DP_IType;
parameter [15:0] DP_Sltiu = DP_IType;
parameter [15:0] DP_Sltu = DP_RType;
parameter [15:0] DP_Sra = DP_RType;
parameter [15:0] DP_Srav = DP_RType;
parameter [15:0] DP_Srl = DP_RType;
parameter [15:0] DP_Srlv = DP_RType;
parameter [15:0] DP_Sub = DP_RType;
parameter [15:0] DP_Subu = DP_RType;
parameter [15:0] DP_Sw = DP_StoreWord;
parameter [15:0] DP_Swl = DP_StoreWord;
parameter [15:0] DP_Swr = DP_StoreWord;
parameter [15:0] DP_Syscall = DP_None;
parameter [15:0] DP_Teq = DP_TrapRegCZ;
parameter [15:0] DP_Teqi = DP_TrapImmCZ;
parameter [15:0] DP_Tge = DP_TrapRegCZ;
parameter [15:0] DP_Tgei = DP_TrapImmCZ;
parameter [15:0] DP_Tgeiu = DP_TrapImmCZ;
parameter [15:0] DP_Tgeu = DP_TrapRegCZ;
parameter [15:0] DP_Tlt = DP_TrapRegCNZ;
parameter [15:0] DP_Tlti = DP_TrapImmCNZ;
parameter [15:0] DP_Tltiu = DP_TrapImmCNZ;
parameter [15:0] DP_Tltu = DP_TrapRegCNZ;
parameter [15:0] DP_Tne = DP_TrapRegCNZ;
parameter [15:0] DP_Tnei = DP_TrapImmCNZ;
parameter [15:0] DP_Xor = DP_RType;
parameter [15:0] DP_Xori = DP_IType;
/*** Exception Information ***
All signals are Active High.
Bit Meaning
------------
2: Instruction can cause exceptions in ID
1: Instruction can cause exceptions in EX
0: Instruction can cause exceptions in MEM
*/
parameter [2:0] EXC_None = 3'b000;
parameter [2:0] EXC_ID = 3'b100;
parameter [2:0] EXC_EX = 3'b010;
parameter [2:0] EXC_MEM = 3'b001;
//--------------------------------
parameter [2:0] EXC_Add = EXC_EX;
parameter [2:0] EXC_Addi = EXC_EX;
parameter [2:0] EXC_Addiu = EXC_None;
parameter [2:0] EXC_Addu = EXC_None;
parameter [2:0] EXC_And = EXC_None;
parameter [2:0] EXC_Andi = EXC_None;
parameter [2:0] EXC_Beq = EXC_None;
parameter [2:0] EXC_Bgez = EXC_None;
parameter [2:0] EXC_Bgezal = EXC_None;
parameter [2:0] EXC_Bgtz = EXC_None;
parameter [2:0] EXC_Blez = EXC_None;
parameter [2:0] EXC_Bltz = EXC_None;
parameter [2:0] EXC_Bltzal = EXC_None;
parameter [2:0] EXC_Bne = EXC_None;
parameter [2:0] EXC_Break = EXC_ID;
parameter [2:0] EXC_Clo = EXC_None;
parameter [2:0] EXC_Clz = EXC_None;
parameter [2:0] EXC_Div = EXC_None;
parameter [2:0] EXC_Divu = EXC_None;
parameter [2:0] EXC_Eret = EXC_ID;
parameter [2:0] EXC_J = EXC_None;
parameter [2:0] EXC_Jal = EXC_None;
parameter [2:0] EXC_Jalr = EXC_None;
parameter [2:0] EXC_Jr = EXC_None;
parameter [2:0] EXC_Lb = EXC_MEM;
parameter [2:0] EXC_Lbu = EXC_MEM;
parameter [2:0] EXC_Lh = EXC_MEM;
parameter [2:0] EXC_Lhu = EXC_MEM;
parameter [2:0] EXC_Ll = EXC_MEM;
parameter [2:0] EXC_Lui = EXC_None;
parameter [2:0] EXC_Lw = EXC_MEM;
parameter [2:0] EXC_Lwl = EXC_MEM;
parameter [2:0] EXC_Lwr = EXC_MEM;
parameter [2:0] EXC_Madd = EXC_None;
parameter [2:0] EXC_Maddu = EXC_None;
parameter [2:0] EXC_Mfc0 = EXC_ID;
parameter [2:0] EXC_Mfhi = EXC_None;
parameter [2:0] EXC_Mflo = EXC_None;
parameter [2:0] EXC_Movn = EXC_None;
parameter [2:0] EXC_Movz = EXC_None;
parameter [2:0] EXC_Msub = EXC_None;
parameter [2:0] EXC_Msubu = EXC_None;
parameter [2:0] EXC_Mtc0 = EXC_ID;
parameter [2:0] EXC_Mthi = EXC_None;
parameter [2:0] EXC_Mtlo = EXC_None;
parameter [2:0] EXC_Mul = EXC_None;
parameter [2:0] EXC_Mult = EXC_None;
parameter [2:0] EXC_Multu = EXC_None;
parameter [2:0] EXC_Nor = EXC_None;
parameter [2:0] EXC_Or = EXC_None;
parameter [2:0] EXC_Ori = EXC_None;
parameter [2:0] EXC_Pref = EXC_None; // XXX
parameter [2:0] EXC_Sb = EXC_MEM;
parameter [2:0] EXC_Sc = EXC_MEM;
parameter [2:0] EXC_Sh = EXC_MEM;
parameter [2:0] EXC_Sll = EXC_None;
parameter [2:0] EXC_Sllv = EXC_None;
parameter [2:0] EXC_Slt = EXC_None;
parameter [2:0] EXC_Slti = EXC_None;
parameter [2:0] EXC_Sltiu = EXC_None;
parameter [2:0] EXC_Sltu = EXC_None;
parameter [2:0] EXC_Sra = EXC_None;
parameter [2:0] EXC_Srav = EXC_None;
parameter [2:0] EXC_Srl = EXC_None;
parameter [2:0] EXC_Srlv = EXC_None;
parameter [2:0] EXC_Sub = EXC_EX;
parameter [2:0] EXC_Subu = EXC_None;
parameter [2:0] EXC_Sw = EXC_MEM;
parameter [2:0] EXC_Swl = EXC_MEM;
parameter [2:0] EXC_Swr = EXC_MEM;
parameter [2:0] EXC_Syscall = EXC_ID;
parameter [2:0] EXC_Teq = EXC_MEM;
parameter [2:0] EXC_Teqi = EXC_MEM;
parameter [2:0] EXC_Tge = EXC_MEM;
parameter [2:0] EXC_Tgei = EXC_MEM;
parameter [2:0] EXC_Tgeiu = EXC_MEM;
parameter [2:0] EXC_Tgeu = EXC_MEM;
parameter [2:0] EXC_Tlt = EXC_MEM;
parameter [2:0] EXC_Tlti = EXC_MEM;
parameter [2:0] EXC_Tltiu = EXC_MEM;
parameter [2:0] EXC_Tltu = EXC_MEM;
parameter [2:0] EXC_Tne = EXC_MEM;
parameter [2:0] EXC_Tnei = EXC_MEM;
parameter [2:0] EXC_Xor = EXC_None;
parameter [2:0] EXC_Xori = EXC_None;
/*** Hazard & Forwarding Datapath ***
All signals are Active High.
Bit Meaning
------------
7: Wants Rs by ID
6: Needs Rs by ID
5: Wants Rt by ID
4: Needs Rt by ID
3: Wants Rs by EX
2: Needs Rs by EX
1: Wants Rt by EX
0: Needs Rt by EX
*/
parameter [7:0] HAZ_Nothing = 8'b00000000; // Jumps, Lui, Mfhi/lo, special, etc.
parameter [7:0] HAZ_IDRsIDRt = 8'b11110000; // Beq, Bne, Traps
parameter [7:0] HAZ_IDRs = 8'b11000000; // Most branches, Jumps to registers
parameter [7:0] HAZ_IDRt = 8'b00110000; // Mtc0
parameter [7:0] HAZ_IDRtEXRs = 8'b10111100; // Movn, Movz
parameter [7:0] HAZ_EXRsEXRt = 8'b10101111; // Many R-Type ops
parameter [7:0] HAZ_EXRs = 8'b10001100; // Immediates: Loads, Clo/z, Mthi/lo, etc.
parameter [7:0] HAZ_EXRsWRt = 8'b10101110; // Stores
parameter [7:0] HAZ_EXRt = 8'b00100011; // Shifts using Shamt field
//-----------------------------------------
parameter [7:0] HAZ_Add = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Addi = HAZ_EXRs;
parameter [7:0] HAZ_Addiu = HAZ_EXRs;
parameter [7:0] HAZ_Addu = HAZ_EXRsEXRt;
parameter [7:0] HAZ_And = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Andi = HAZ_EXRs;
parameter [7:0] HAZ_Beq = HAZ_IDRsIDRt;
parameter [7:0] HAZ_Bgez = HAZ_IDRs;
parameter [7:0] HAZ_Bgezal = HAZ_IDRs;
parameter [7:0] HAZ_Bgtz = HAZ_IDRs;
parameter [7:0] HAZ_Blez = HAZ_IDRs;
parameter [7:0] HAZ_Bltz = HAZ_IDRs;
parameter [7:0] HAZ_Bltzal = HAZ_IDRs;
parameter [7:0] HAZ_Bne = HAZ_IDRsIDRt;
parameter [7:0] HAZ_Break = HAZ_Nothing;
parameter [7:0] HAZ_Clo = HAZ_EXRs;
parameter [7:0] HAZ_Clz = HAZ_EXRs;
parameter [7:0] HAZ_Div = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Divu = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Eret = HAZ_Nothing;
parameter [7:0] HAZ_J = HAZ_Nothing;
parameter [7:0] HAZ_Jal = HAZ_Nothing;
parameter [7:0] HAZ_Jalr = HAZ_IDRs;
parameter [7:0] HAZ_Jr = HAZ_IDRs;
parameter [7:0] HAZ_Lb = HAZ_EXRs;
parameter [7:0] HAZ_Lbu = HAZ_EXRs;
parameter [7:0] HAZ_Lh = HAZ_EXRs;
parameter [7:0] HAZ_Lhu = HAZ_EXRs;
parameter [7:0] HAZ_Ll = HAZ_EXRs;
parameter [7:0] HAZ_Lui = HAZ_Nothing;
parameter [7:0] HAZ_Lw = HAZ_EXRs;
parameter [7:0] HAZ_Lwl = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Lwr = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Madd = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Maddu = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Mfc0 = HAZ_Nothing;
parameter [7:0] HAZ_Mfhi = HAZ_Nothing;
parameter [7:0] HAZ_Mflo = HAZ_Nothing;
parameter [7:0] HAZ_Movn = HAZ_IDRtEXRs;
parameter [7:0] HAZ_Movz = HAZ_IDRtEXRs;
parameter [7:0] HAZ_Msub = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Msubu = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Mtc0 = HAZ_IDRt;
parameter [7:0] HAZ_Mthi = HAZ_EXRs;
parameter [7:0] HAZ_Mtlo = HAZ_EXRs;
parameter [7:0] HAZ_Mul = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Mult = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Multu = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Nor = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Or = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Ori = HAZ_EXRs;
parameter [7:0] HAZ_Pref = HAZ_Nothing; // XXX
parameter [7:0] HAZ_Sb = HAZ_EXRsWRt;
parameter [7:0] HAZ_Sc = HAZ_EXRsWRt;
parameter [7:0] HAZ_Sh = HAZ_EXRsWRt;
parameter [7:0] HAZ_Sll = HAZ_EXRt;
parameter [7:0] HAZ_Sllv = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Slt = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Slti = HAZ_EXRs;
parameter [7:0] HAZ_Sltiu = HAZ_EXRs;
parameter [7:0] HAZ_Sltu = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Sra = HAZ_EXRt;
parameter [7:0] HAZ_Srav = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Srl = HAZ_EXRt;
parameter [7:0] HAZ_Srlv = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Sub = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Subu = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Sw = HAZ_EXRsWRt;
parameter [7:0] HAZ_Swl = HAZ_EXRsWRt;
parameter [7:0] HAZ_Swr = HAZ_EXRsWRt;
parameter [7:0] HAZ_Syscall = HAZ_Nothing;
parameter [7:0] HAZ_Teq = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Teqi = HAZ_EXRs;
parameter [7:0] HAZ_Tge = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Tgei = HAZ_EXRs;
parameter [7:0] HAZ_Tgeiu = HAZ_EXRs;
parameter [7:0] HAZ_Tgeu = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Tlt = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Tlti = HAZ_EXRs;
parameter [7:0] HAZ_Tltiu = HAZ_EXRs;
parameter [7:0] HAZ_Tltu = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Tne = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Tnei = HAZ_EXRs;
parameter [7:0] HAZ_Xor = HAZ_EXRsEXRt;
parameter [7:0] HAZ_Xori = HAZ_EXRs;

233
demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/MemControl.v Executable file
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`timescale 1ns / 1ps
/*
* File : MemControl.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 24-Jun-2011 GEA Initial design.
* 2.0 28-Jun-2012 GEA Expanded from a simple byte/half/word unit to
* An advanced data memory controller capable of
* handling big/little endian, atomic and unaligned
* memory accesses.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* A Data Memory Controller which handles all read and write requests from the
* processor to data memory. All data accesses--whether big endian, little endian,
* byte, half, word, or unaligned transfers--are transformed into a simple read
* and write command to data memory over a 32-bit data bus, where the read command
* is one bit and the write command is 4 bits, one for each byte in the 32-bit word.
*/
module MemControl(
input clock,
input reset,
input [31:0] DataIn, // Data from CPU
input [31:0] Address, // From CPU
input [31:0] MReadData, // Data from Memory
input MemRead, // Memory Read command from CPU
input MemWrite, // Memory Write command from CPU
input DataMem_Ready, // Ready signal from Memory
input Byte, // Load/Store is Byte (8-bit)
input Half, // Load/Store is Half (16-bit)
input SignExtend, // Sub-word load should be sign extended
input KernelMode, // (Exception logic)
input ReverseEndian, // Reverse Endian Memory for User Mode
input LLSC, // (LLSC logic)
input ERET, // (LLSC logic)
input Left, // Unaligned Load/Store Word Left
input Right, // Unaligned Load/Store Word Right
input M_Exception_Stall,
input IF_Stall, // XXX Clean this up between this module and HAZ/FWD
output reg [31:0] DataOut, // Data to CPU
output [31:0] MWriteData, // Data to Memory
output reg [3:0] WriteEnable, // Write Enable to Memory for each of 4 bytes of Memory
output ReadEnable, // Read Enable to Memory
output M_Stall,
output EXC_AdEL, // Load Exception
output EXC_AdES // Store Exception
);
`include "MIPS_Parameters.v"
/*** Reverse Endian Mode
Normal memory accesses in the processor are Big Endian. The endianness can be reversed
to Little Endian in User Mode only.
*/
wire BE = KernelMode | ~ReverseEndian;
/*** Indicator that the current memory reference must be word-aligned ***/
wire Word = ~(Half | Byte | Left | Right);
// Exception Detection
wire EXC_KernelMem = ~KernelMode & (Address < UMem_Lower);
wire EXC_Word = Word & (Address[1] | Address[0]);
wire EXC_Half = Half & Address[0];
assign EXC_AdEL = MemRead & (EXC_KernelMem | EXC_Word | EXC_Half);
assign EXC_AdES = MemWrite & (EXC_KernelMem | EXC_Word | EXC_Half);
/*** Load Linked and Store Conditional logic ***
A 32-bit register keeps track of the address for atomic Load Linked / Store Conditional
operations. This register can be updated during stalls since it is not visible to
forward stages. It does not need to be flushed during exceptions, since ERET destroys
the atomicity condition and there are no detrimental effects in an exception handler.
The atomic condition is set with a Load Linked instruction, and cleared on an ERET
instruction or when any store instruction writes to one or more bytes covered by
the word address register. It does not update on a stall condition.
The MIPS32 spec states that an ERET instruction between LL and SC will cause the
atomicity condition to fail. This implementation uses the ERET signal from the ID
stage, which means instruction sequences such as "LL SC" could appear to have an
ERET instruction between them even though they don't. One way to fix this is to pass
the ERET signal through the pipeline to the MEM stage. However, because of the nature
of LL/SC operations (they occur in a loop which checks the result at each iteration),
an ERET will normally never be inserted into the pipeline programmatically until the
LL/SC sequence has completed (exceptions such as interrupts can still cause ERET, but
they can still cause them in the LL SC sequence as well). In other words, by not passing
ERET through the pipeline, the only possible effect is a performance penalty. Also this
may be irrelevant since currently ERET stalls for forward stages which can cause exceptions,
which includes LL and SC.
*/
reg [29:0] LLSC_Address;
reg LLSC_Atomic;
wire LLSC_MemWrite_Mask;
always @(posedge clock) begin
LLSC_Address <= (reset) ? 30'b0 : (MemRead & LLSC) ? Address[31:2] : LLSC_Address;
end
always @(posedge clock) begin
if (reset) begin
LLSC_Atomic <= 0;
end
else if (MemRead) begin
LLSC_Atomic <= (LLSC) ? 1 : LLSC_Atomic;
end
// XXX GEA Bug for Ganesh: remove "& ~IF_Stall" from below, then SC will always fail:
else if (ERET | (~M_Stall & ~IF_Stall & MemWrite & (Address[31:2] == LLSC_Address))) begin
LLSC_Atomic <= 0;
end
else begin
LLSC_Atomic <= LLSC_Atomic;
end
end
assign LLSC_MemWrite_Mask = (LLSC & MemWrite & (~LLSC_Atomic | (Address[31:2] != LLSC_Address)));
wire WriteCondition = MemWrite & ~(EXC_KernelMem | EXC_Word | EXC_Half) & ~LLSC_MemWrite_Mask;
wire ReadCondition = MemRead & ~(EXC_KernelMem | EXC_Word | EXC_Half);
reg RW_Mask;
always @(posedge clock) begin
RW_Mask <= (reset) ? 0 : (((MemWrite | MemRead) & DataMem_Ready) ? 1 : ((~M_Stall & ~IF_Stall) ? 0 : RW_Mask));
end
assign M_Stall = ReadEnable | (WriteEnable != 4'b0000) | DataMem_Ready | M_Exception_Stall;
assign ReadEnable = ReadCondition & ~RW_Mask;
wire Half_Access_L = (Address[1] ^ BE);
wire Half_Access_R = (Address[1] ~^ BE);
wire Byte_Access_LL = Half_Access_L & (Address[1] ~^ Address[0]);
wire Byte_Access_LM = Half_Access_L & (Address[0] ~^ BE);
wire Byte_Access_RM = Half_Access_R & (Address[0] ^ BE);
wire Byte_Access_RR = Half_Access_R & (Address[1] ~^ Address[0]);
// Write-Enable Signals to Memory
always @(*) begin
if (WriteCondition & ~RW_Mask) begin
if (Byte) begin
WriteEnable[3] <= Byte_Access_LL;
WriteEnable[2] <= Byte_Access_LM;
WriteEnable[1] <= Byte_Access_RM;
WriteEnable[0] <= Byte_Access_RR;
end
else if (Half) begin
WriteEnable[3] <= Half_Access_L;
WriteEnable[2] <= Half_Access_L;
WriteEnable[1] <= Half_Access_R;
WriteEnable[0] <= Half_Access_R;
end
else if (Left) begin
case (Address[1:0])
2'b00 : WriteEnable <= (BE) ? 4'b1111 : 4'b0001;
2'b01 : WriteEnable <= (BE) ? 4'b0111 : 4'b0011;
2'b10 : WriteEnable <= (BE) ? 4'b0011 : 4'b0111;
2'b11 : WriteEnable <= (BE) ? 4'b0001 : 4'b1111;
endcase
end
else if (Right) begin
case (Address[1:0])
2'b00 : WriteEnable <= (BE) ? 4'b1000 : 4'b1111;
2'b01 : WriteEnable <= (BE) ? 4'b1100 : 4'b1110;
2'b10 : WriteEnable <= (BE) ? 4'b1110 : 4'b1100;
2'b11 : WriteEnable <= (BE) ? 4'b1111 : 4'b1000;
endcase
end
else begin
WriteEnable <= 4'b1111;
end
end
else begin
WriteEnable <= 4'b0000;
end
end
// Data Going to Memory
assign MWriteData[31:24] = (Byte) ? DataIn[7:0] : ((Half) ? DataIn[15:8] : DataIn[31:24]);
assign MWriteData[23:16] = (Byte | Half) ? DataIn[7:0] : DataIn[23:16];
assign MWriteData[15:8] = (Byte) ? DataIn[7:0] : DataIn[15:8];
assign MWriteData[7:0] = DataIn[7:0];
// Data Read from Memory
always @(*) begin
if (Byte) begin
if (Byte_Access_LL) begin
DataOut <= (SignExtend & MReadData[31]) ? {24'hFFFFFF, MReadData[31:24]} : {24'h000000, MReadData[31:24]};
end
else if (Byte_Access_LM) begin
DataOut <= (SignExtend & MReadData[23]) ? {24'hFFFFFF, MReadData[23:16]} : {24'h000000, MReadData[23:16]};
end
else if (Byte_Access_RM) begin
DataOut <= (SignExtend & MReadData[15]) ? {24'hFFFFFF, MReadData[15:8]} : {24'h000000, MReadData[15:8]};
end
else begin
DataOut <= (SignExtend & MReadData[7]) ? {24'hFFFFFF, MReadData[7:0]} : {24'h000000, MReadData[7:0]};
end
end
else if (Half) begin
if (Half_Access_L) begin
DataOut <= (SignExtend & MReadData[31]) ? {16'hFFFF, MReadData[31:16]} : {16'h0000, MReadData[31:16]};
end
else begin
DataOut <= (SignExtend & MReadData[15]) ? {16'hFFFF, MReadData[15:0]} : {16'h0000, MReadData[15:0]};
end
end
else if (LLSC & MemWrite) begin
DataOut <= (LLSC_Atomic & (Address[31:2] == LLSC_Address)) ? 32'h0000_0001 : 32'h0000_0000;
end
else if (Left) begin
case (Address[1:0])
2'b00 : DataOut <= (BE) ? MReadData : {MReadData[7:0], DataIn[23:0]};
2'b01 : DataOut <= (BE) ? {MReadData[23:0], DataIn[7:0]} : {MReadData[15:0], DataIn[15:0]};
2'b10 : DataOut <= (BE) ? {MReadData[15:0], DataIn[15:0]} : {MReadData[23:0], DataIn[7:0]};
2'b11 : DataOut <= (BE) ? {MReadData[7:0], DataIn[23:0]} : MReadData;
endcase
end
else if (Right) begin
case (Address[1:0])
2'b00 : DataOut <= (BE) ? {DataIn[31:8], MReadData[31:24]} : MReadData;
2'b01 : DataOut <= (BE) ? {DataIn[31:16], MReadData[31:16]} : {DataIn[31:24], MReadData[31:8]};
2'b10 : DataOut <= (BE) ? {DataIn[31:24], MReadData[31:8]} : {DataIn[31:16], MReadData[31:16]};
2'b11 : DataOut <= (BE) ? MReadData : {DataIn[31:8], MReadData[31:24]};
endcase
end
else begin
DataOut <= MReadData;
end
end
endmodule

26
demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Mux2.v Executable file
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`timescale 1ns / 1ps
/*
* File : Mux2.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 7-Jun-2011 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* A 2-input Mux of variable width, defaulting to 32-bit width.
*/
module Mux2 #(parameter WIDTH = 32)(
input sel,
input [(WIDTH-1):0] in0, in1,
output [(WIDTH-1):0] out
);
assign out = (sel) ? in1 : in0;
endmodule

33
demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Mux4.v Executable file
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`timescale 1ns / 1ps
/*
* File : Mux4.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 7-Jun-2011 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* A 4-input Mux of variable width, defaulting to 32-bit width.
*/
module Mux4 #(parameter WIDTH = 32)(
input [1:0] sel,
input [(WIDTH-1):0] in0, in1, in2, in3,
output reg [(WIDTH-1):0] out
);
always @(*) begin
case (sel)
2'b00 : out <= in0;
2'b01 : out <= in1;
2'b10 : out <= in2;
2'b11 : out <= in3;
endcase
end
endmodule

679
demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Processor.v Executable file
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`timescale 1ns / 1ps
/*
* File : Processor.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 23-Jul-2011 GEA Initial design.
* 2.0 26-May-2012 GEA Release version with CP0.
* 2.01 1-Nov-2012 GEA Fixed issue with Jal.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The top-level MIPS32 Processor. This file is mostly the instantiation
* and wiring of the building blocks of the processor according to the
* hardware design diagram. It contains very little logic itself.
*/
module Processor(
input clock,
input reset,
input [4:0] Interrupts, // 5 general-purpose hardware interrupts
input NMI, // Non-maskable interrupt
// Data Memory Interface
input [31:0] DataMem_In,
input DataMem_Ready,
output DataMem_Read,
output [3:0] DataMem_Write, // 4-bit Write, one for each byte in word.
output [29:0] DataMem_Address, // Addresses are words, not bytes.
output [31:0] DataMem_Out,
// Instruction Memory Interface
input [31:0] InstMem_In,
output [29:0] InstMem_Address, // Addresses are words, not bytes.
input InstMem_Ready,
output InstMem_Read,
output [7:0] IP // Pending interrupts (diagnostic)
);
`include "MIPS_Parameters.v"
/*** MIPS Instruction and Components (ID Stage) ***/
wire [31:0] Instruction;
wire [5:0] OpCode = Instruction[31:26];
wire [4:0] Rs = Instruction[25:21];
wire [4:0] Rt = Instruction[20:16];
wire [4:0] Rd = Instruction[15:11];
wire [5:0] Funct = Instruction[5:0];
wire [15:0] Immediate = Instruction[15:0];
wire [25:0] JumpAddress = Instruction[25:0];
wire [2:0] Cp0_Sel = Instruction[2:0];
/*** IF (Instruction Fetch) Signals ***/
wire IF_Stall, IF_Flush;
wire IF_EXC_AdIF;
wire IF_Exception_Stall;
wire IF_Exception_Flush;
wire IF_IsBDS;
wire [31:0] IF_PCAdd4, IF_PC_PreExc, IF_PCIn, IF_PCOut, IF_Instruction;
/*** ID (Instruction Decode) Signals ***/
wire ID_Stall;
wire [1:0] ID_PCSrc;
wire [1:0] ID_RsFwdSel, ID_RtFwdSel;
wire ID_Link, ID_Movn, ID_Movz;
wire ID_SignExtend;
wire ID_LLSC;
wire ID_RegDst, ID_ALUSrcImm, ID_MemWrite, ID_MemRead, ID_MemByte, ID_MemHalf, ID_MemSignExtend, ID_RegWrite, ID_MemtoReg;
wire [4:0] ID_ALUOp;
wire ID_Mfc0, ID_Mtc0, ID_Eret;
wire ID_NextIsDelay;
wire ID_CanErr, ID_ID_CanErr, ID_EX_CanErr, ID_M_CanErr;
wire ID_KernelMode;
wire ID_ReverseEndian;
wire ID_Trap, ID_TrapCond;
wire ID_EXC_Sys, ID_EXC_Bp, ID_EXC_RI;
wire ID_Exception_Stall;
wire ID_Exception_Flush;
wire ID_PCSrc_Exc;
wire [31:0] ID_ExceptionPC;
wire ID_CP1, ID_CP2, ID_CP3;
wire [31:0] ID_PCAdd4;
wire [31:0] ID_ReadData1_RF, ID_ReadData1_End;
wire [31:0] ID_ReadData2_RF, ID_ReadData2_End;
wire [31:0] CP0_RegOut;
wire ID_CmpEQ, ID_CmpGZ, ID_CmpLZ, ID_CmpGEZ, ID_CmpLEZ;
wire [29:0] ID_SignExtImm = (ID_SignExtend & Immediate[15]) ? {14'h3FFF, Immediate} : {14'h0000, Immediate};
wire [31:0] ID_ImmLeftShift2 = {ID_SignExtImm[29:0], 2'b00};
wire [31:0] ID_JumpAddress = {ID_PCAdd4[31:28], JumpAddress[25:0], 2'b00};
wire [31:0] ID_BranchAddress;
wire [31:0] ID_RestartPC;
wire ID_IsBDS;
wire ID_Left, ID_Right;
wire ID_IsFlushed;
/*** EX (Execute) Signals ***/
wire EX_ALU_Stall, EX_Stall;
wire [1:0] EX_RsFwdSel, EX_RtFwdSel;
wire EX_Link;
wire [1:0] EX_LinkRegDst;
wire EX_ALUSrcImm;
wire [4:0] EX_ALUOp;
wire EX_Movn, EX_Movz;
wire EX_LLSC;
wire EX_MemRead, EX_MemWrite, EX_MemByte, EX_MemHalf, EX_MemSignExtend, EX_RegWrite, EX_MemtoReg;
wire [4:0] EX_Rs, EX_Rt;
wire EX_WantRsByEX, EX_NeedRsByEX, EX_WantRtByEX, EX_NeedRtByEX;
wire EX_Trap, EX_TrapCond;
wire EX_CanErr, EX_EX_CanErr, EX_M_CanErr;
wire EX_KernelMode;
wire EX_ReverseEndian;
wire EX_Exception_Stall;
wire EX_Exception_Flush;
wire [31:0] EX_ReadData1_PR, EX_ReadData1_Fwd, EX_ReadData2_PR, EX_ReadData2_Fwd, EX_ReadData2_Imm;
wire [31:0] EX_SignExtImm;
wire [4:0] EX_Rd, EX_RtRd, EX_Shamt;
wire [31:0] EX_ALUResult;
wire EX_BZero;
wire EX_EXC_Ov;
wire [31:0] EX_RestartPC;
wire EX_IsBDS;
wire EX_Left, EX_Right;
/*** MEM (Memory) Signals ***/
wire M_Stall, M_Stall_Controller;
wire M_LLSC;
wire M_MemRead, M_MemWrite, M_MemByte, M_MemHalf, M_MemSignExtend;
wire M_RegWrite, M_MemtoReg;
wire M_WriteDataFwdSel;
wire M_EXC_AdEL, M_EXC_AdES;
wire M_M_CanErr;
wire M_KernelMode;
wire M_ReverseEndian;
wire M_Trap, M_TrapCond;
wire M_EXC_Tr;
wire M_Exception_Flush;
wire [31:0] M_ALUResult, M_ReadData2_PR;
wire [4:0] M_RtRd;
wire [31:0] M_MemReadData;
wire [31:0] M_RestartPC;
wire M_IsBDS;
wire [31:0] M_WriteData_Pre;
wire M_Left, M_Right;
wire M_Exception_Stall;
/*** WB (Writeback) Signals ***/
wire WB_Stall, WB_RegWrite;
wire [31:0] WB_ReadData, WB_ALUResult;
wire [4:0] WB_RtRd;
wire [31:0] WB_WriteData;
/*** Other Signals ***/
wire [7:0] ID_DP_Hazards, HAZ_DP_Hazards;
/*** Assignments ***/
assign IF_Instruction = (IF_Stall) ? 32'h00000000 : InstMem_In;
assign IF_IsBDS = ID_NextIsDelay;
assign HAZ_DP_Hazards = {ID_DP_Hazards[7:4], EX_WantRsByEX, EX_NeedRsByEX, EX_WantRtByEX, EX_NeedRtByEX};
assign IF_EXC_AdIF = IF_PCOut[1] | IF_PCOut[0];
assign ID_CanErr = ID_ID_CanErr | ID_EX_CanErr | ID_M_CanErr;
assign EX_CanErr = EX_EX_CanErr | EX_M_CanErr;
assign M_CanErr = M_M_CanErr;
// External Memory Interface
reg IRead, IReadMask;
assign InstMem_Address = IF_PCOut[31:2];
assign DataMem_Address = M_ALUResult[31:2];
always @(posedge clock) begin
IRead <= (reset) ? 1 : ~InstMem_Ready;
IReadMask <= (reset) ? 0 : ((IRead & InstMem_Ready) ? 1 : ((~IF_Stall) ? 0 : IReadMask));
end
assign InstMem_Read = IRead & ~IReadMask;
/*** Datapath Controller ***/
Control Controller (
.ID_Stall (ID_Stall),
.OpCode (OpCode),
.Funct (Funct),
.Rs (Rs),
.Rt (Rt),
.Cmp_EQ (ID_CmpEQ),
.Cmp_GZ (ID_CmpGZ),
.Cmp_GEZ (ID_CmpGEZ),
.Cmp_LZ (ID_CmpLZ),
.Cmp_LEZ (ID_CmpLEZ),
.IF_Flush (IF_Flush),
.DP_Hazards (ID_DP_Hazards),
.PCSrc (ID_PCSrc),
.SignExtend (ID_SignExtend),
.Link (ID_Link),
.Movn (ID_Movn),
.Movz (ID_Movz),
.Mfc0 (ID_Mfc0),
.Mtc0 (ID_Mtc0),
.CP1 (ID_CP1),
.CP2 (ID_CP2),
.CP3 (ID_CP3),
.Eret (ID_Eret),
.Trap (ID_Trap),
.TrapCond (ID_TrapCond),
.EXC_Sys (ID_EXC_Sys),
.EXC_Bp (ID_EXC_Bp),
.EXC_RI (ID_EXC_RI),
.ID_CanErr (ID_ID_CanErr),
.EX_CanErr (ID_EX_CanErr),
.M_CanErr (ID_M_CanErr),
.NextIsDelay (ID_NextIsDelay),
.RegDst (ID_RegDst),
.ALUSrcImm (ID_ALUSrcImm),
.ALUOp (ID_ALUOp),
.LLSC (ID_LLSC),
.MemWrite (ID_MemWrite),
.MemRead (ID_MemRead),
.MemByte (ID_MemByte),
.MemHalf (ID_MemHalf),
.MemSignExtend (ID_MemSignExtend),
.Left (ID_Left),
.Right (ID_Right),
.RegWrite (ID_RegWrite),
.MemtoReg (ID_MemtoReg)
);
/*** Hazard and Forward Control Unit ***/
Hazard_Detection HazardControl (
.DP_Hazards (HAZ_DP_Hazards),
.ID_Rs (Rs),
.ID_Rt (Rt),
.EX_Rs (EX_Rs),
.EX_Rt (EX_Rt),
.EX_RtRd (EX_RtRd),
.MEM_RtRd (M_RtRd),
.WB_RtRd (WB_RtRd),
.EX_Link (EX_Link),
.EX_RegWrite (EX_RegWrite),
.MEM_RegWrite (M_RegWrite),
.WB_RegWrite (WB_RegWrite),
.MEM_MemRead (M_MemRead),
.MEM_MemWrite (M_MemWrite),
.InstMem_Read (InstMem_Read),
.InstMem_Ready (InstMem_Ready),
.Mfc0 (ID_Mfc0),
.IF_Exception_Stall (IF_Exception_Stall),
.ID_Exception_Stall (ID_Exception_Stall),
.EX_Exception_Stall (EX_Exception_Stall),
.EX_ALU_Stall (EX_ALU_Stall),
.M_Stall_Controller (M_Stall_Controller),
.IF_Stall (IF_Stall),
.ID_Stall (ID_Stall),
.EX_Stall (EX_Stall),
.M_Stall (M_Stall),
.WB_Stall (WB_Stall),
.ID_RsFwdSel (ID_RsFwdSel),
.ID_RtFwdSel (ID_RtFwdSel),
.EX_RsFwdSel (EX_RsFwdSel),
.EX_RtFwdSel (EX_RtFwdSel),
.M_WriteDataFwdSel (M_WriteDataFwdSel)
);
/*** Coprocessor 0: Exceptions and Interrupts ***/
CPZero CP0 (
.clock (clock),
.Mfc0 (ID_Mfc0),
.Mtc0 (ID_Mtc0),
.IF_Stall (IF_Stall),
.ID_Stall (ID_Stall),
.COP1 (ID_CP1),
.COP2 (ID_CP2),
.COP3 (ID_CP3),
.ERET (ID_Eret),
.Rd (Rd),
.Sel (Cp0_Sel),
.Reg_In (ID_ReadData2_End),
.Reg_Out (CP0_RegOut),
.KernelMode (ID_KernelMode),
.ReverseEndian (ID_ReverseEndian),
.Int (Interrupts),
.reset (reset),
.EXC_NMI (NMI),
.EXC_AdIF (IF_EXC_AdIF),
.EXC_AdEL (M_EXC_AdEL),
.EXC_AdES (M_EXC_AdES),
.EXC_Ov (EX_EXC_Ov),
.EXC_Tr (M_EXC_Tr),
.EXC_Sys (ID_EXC_Sys),
.EXC_Bp (ID_EXC_Bp),
.EXC_RI (ID_EXC_RI),
.ID_RestartPC (ID_RestartPC),
.EX_RestartPC (EX_RestartPC),
.M_RestartPC (M_RestartPC),
.ID_IsFlushed (ID_IsFlushed),
.IF_IsBD (IF_IsBDS),
.ID_IsBD (ID_IsBDS),
.EX_IsBD (EX_IsBDS),
.M_IsBD (M_IsBDS),
.BadAddr_M (M_ALUResult),
.BadAddr_IF (IF_PCOut),
.ID_CanErr (ID_CanErr),
.EX_CanErr (EX_CanErr),
.M_CanErr (M_CanErr),
.IF_Exception_Stall (IF_Exception_Stall),
.ID_Exception_Stall (ID_Exception_Stall),
.EX_Exception_Stall (EX_Exception_Stall),
.M_Exception_Stall (M_Exception_Stall),
.IF_Exception_Flush (IF_Exception_Flush),
.ID_Exception_Flush (ID_Exception_Flush),
.EX_Exception_Flush (EX_Exception_Flush),
.M_Exception_Flush (M_Exception_Flush),
.Exc_PC_Sel (ID_PCSrc_Exc),
.Exc_PC_Out (ID_ExceptionPC),
.IP (IP)
);
/*** PC Source Non-Exception Mux ***/
Mux4 #(.WIDTH(32)) PCSrcStd_Mux (
.sel (ID_PCSrc),
.in0 (IF_PCAdd4),
.in1 (ID_JumpAddress),
.in2 (ID_BranchAddress),
.in3 (ID_ReadData1_End),
.out (IF_PC_PreExc)
);
/*** PC Source Exception Mux ***/
Mux2 #(.WIDTH(32)) PCSrcExc_Mux (
.sel (ID_PCSrc_Exc),
.in0 (IF_PC_PreExc),
.in1 (ID_ExceptionPC),
.out (IF_PCIn)
);
/*** Program Counter (MIPS spec is 0xBFC00000 starting address) ***/
Register #(.WIDTH(32), .INIT(EXC_Vector_Base_Reset)) PC (
.clock (clock),
.reset (reset),
//.enable (~IF_Stall), // XXX verify. HERE. Was 1 but on stall latches PC+4, ad nauseum.
.enable (~(IF_Stall | ID_Stall)),
.D (IF_PCIn),
.Q (IF_PCOut)
);
/*** PC +4 Adder ***/
Add PC_Add4 (
.A (IF_PCOut),
.B (32'h00000004),
.C (IF_PCAdd4)
);
/*** Instruction Fetch -> Instruction Decode Stage Register ***/
IFID_Stage IFID (
.clock (clock),
.reset (reset),
.IF_Flush (IF_Exception_Flush | IF_Flush),
.IF_Stall (IF_Stall),
.ID_Stall (ID_Stall),
.IF_Instruction (IF_Instruction),
.IF_PCAdd4 (IF_PCAdd4),
.IF_PC (IF_PCOut),
.IF_IsBDS (IF_IsBDS),
.ID_Instruction (Instruction),
.ID_PCAdd4 (ID_PCAdd4),
.ID_RestartPC (ID_RestartPC),
.ID_IsBDS (ID_IsBDS),
.ID_IsFlushed (ID_IsFlushed)
);
/*** Register File ***/
RegisterFile RegisterFile (
.clock (clock),
.reset (reset),
.ReadReg1 (Rs),
.ReadReg2 (Rt),
.WriteReg (WB_RtRd),
.WriteData (WB_WriteData),
.RegWrite (WB_RegWrite),
.ReadData1 (ID_ReadData1_RF),
.ReadData2 (ID_ReadData2_RF)
);
/*** ID Rs Forwarding/Link Mux ***/
Mux4 #(.WIDTH(32)) IDRsFwd_Mux (
.sel (ID_RsFwdSel),
.in0 (ID_ReadData1_RF),
.in1 (M_ALUResult),
.in2 (WB_WriteData),
.in3 (32'hxxxxxxxx),
.out (ID_ReadData1_End)
);
/*** ID Rt Forwarding/CP0 Mfc0 Mux ***/
Mux4 #(.WIDTH(32)) IDRtFwd_Mux (
.sel (ID_RtFwdSel),
.in0 (ID_ReadData2_RF),
.in1 (M_ALUResult),
.in2 (WB_WriteData),
.in3 (CP0_RegOut),
.out (ID_ReadData2_End)
);
/*** Condition Compare Unit ***/
Compare Compare (
.A (ID_ReadData1_End),
.B (ID_ReadData2_End),
.EQ (ID_CmpEQ),
.GZ (ID_CmpGZ),
.LZ (ID_CmpLZ),
.GEZ (ID_CmpGEZ),
.LEZ (ID_CmpLEZ)
);
/*** Branch Address Adder ***/
Add BranchAddress_Add (
.A (ID_PCAdd4),
.B (ID_ImmLeftShift2),
.C (ID_BranchAddress)
);
/*** Instruction Decode -> Execute Pipeline Stage ***/
IDEX_Stage IDEX (
.clock (clock),
.reset (reset),
.ID_Flush (ID_Exception_Flush),
.ID_Stall (ID_Stall),
.EX_Stall (EX_Stall),
.ID_Link (ID_Link),
.ID_RegDst (ID_RegDst),
.ID_ALUSrcImm (ID_ALUSrcImm),
.ID_ALUOp (ID_ALUOp),
.ID_Movn (ID_Movn),
.ID_Movz (ID_Movz),
.ID_LLSC (ID_LLSC),
.ID_MemRead (ID_MemRead),
.ID_MemWrite (ID_MemWrite),
.ID_MemByte (ID_MemByte),
.ID_MemHalf (ID_MemHalf),
.ID_MemSignExtend (ID_MemSignExtend),
.ID_Left (ID_Left),
.ID_Right (ID_Right),
.ID_RegWrite (ID_RegWrite),
.ID_MemtoReg (ID_MemtoReg),
.ID_ReverseEndian (ID_ReverseEndian),
.ID_Rs (Rs),
.ID_Rt (Rt),
.ID_WantRsByEX (ID_DP_Hazards[3]),
.ID_NeedRsByEX (ID_DP_Hazards[2]),
.ID_WantRtByEX (ID_DP_Hazards[1]),
.ID_NeedRtByEX (ID_DP_Hazards[0]),
.ID_KernelMode (ID_KernelMode),
.ID_RestartPC (ID_RestartPC),
.ID_IsBDS (ID_IsBDS),
.ID_Trap (ID_Trap),
.ID_TrapCond (ID_TrapCond),
.ID_EX_CanErr (ID_EX_CanErr),
.ID_M_CanErr (ID_M_CanErr),
.ID_ReadData1 (ID_ReadData1_End),
.ID_ReadData2 (ID_ReadData2_End),
.ID_SignExtImm (ID_SignExtImm[16:0]),
.EX_Link (EX_Link),
.EX_LinkRegDst (EX_LinkRegDst),
.EX_ALUSrcImm (EX_ALUSrcImm),
.EX_ALUOp (EX_ALUOp),
.EX_Movn (EX_Movn),
.EX_Movz (EX_Movz),
.EX_LLSC (EX_LLSC),
.EX_MemRead (EX_MemRead),
.EX_MemWrite (EX_MemWrite),
.EX_MemByte (EX_MemByte),
.EX_MemHalf (EX_MemHalf),
.EX_MemSignExtend (EX_MemSignExtend),
.EX_Left (EX_Left),
.EX_Right (EX_Right),
.EX_RegWrite (EX_RegWrite),
.EX_MemtoReg (EX_MemtoReg),
.EX_ReverseEndian (EX_ReverseEndian),
.EX_Rs (EX_Rs),
.EX_Rt (EX_Rt),
.EX_WantRsByEX (EX_WantRsByEX),
.EX_NeedRsByEX (EX_NeedRsByEX),
.EX_WantRtByEX (EX_WantRtByEX),
.EX_NeedRtByEX (EX_NeedRtByEX),
.EX_KernelMode (EX_KernelMode),
.EX_RestartPC (EX_RestartPC),
.EX_IsBDS (EX_IsBDS),
.EX_Trap (EX_Trap),
.EX_TrapCond (EX_TrapCond),
.EX_EX_CanErr (EX_EX_CanErr),
.EX_M_CanErr (EX_M_CanErr),
.EX_ReadData1 (EX_ReadData1_PR),
.EX_ReadData2 (EX_ReadData2_PR),
.EX_SignExtImm (EX_SignExtImm),
.EX_Rd (EX_Rd),
.EX_Shamt (EX_Shamt)
);
/*** EX Rs Forwarding Mux ***/
Mux4 #(.WIDTH(32)) EXRsFwd_Mux (
.sel (EX_RsFwdSel),
.in0 (EX_ReadData1_PR),
.in1 (M_ALUResult),
.in2 (WB_WriteData),
.in3 (EX_RestartPC),
.out (EX_ReadData1_Fwd)
);
/*** EX Rt Forwarding / Link Mux ***/
Mux4 #(.WIDTH(32)) EXRtFwdLnk_Mux (
.sel (EX_RtFwdSel),
.in0 (EX_ReadData2_PR),
.in1 (M_ALUResult),
.in2 (WB_WriteData),
.in3 (32'h00000008),
.out (EX_ReadData2_Fwd)
);
/*** EX ALU Immediate Mux ***/
Mux2 #(.WIDTH(32)) EXALUImm_Mux (
.sel (EX_ALUSrcImm),
.in0 (EX_ReadData2_Fwd),
.in1 (EX_SignExtImm),
.out (EX_ReadData2_Imm)
);
/*** EX RtRd / Link Mux ***/
Mux4 #(.WIDTH(5)) EXRtRdLnk_Mux (
.sel (EX_LinkRegDst),
.in0 (EX_Rt),
.in1 (EX_Rd),
.in2 (5'b11111),
.in3 (5'bxxxxx),
.out (EX_RtRd)
);
/*** Arithmetic Logic Unit ***/
ALU ALU (
.clock (clock),
.reset (reset),
.EX_Stall (EX_Stall),
.EX_Flush (EX_Exception_Flush),
.A (EX_ReadData1_Fwd),
.B (EX_ReadData2_Imm),
.Operation (EX_ALUOp),
.Shamt (EX_Shamt),
.Result (EX_ALUResult),
.BZero (EX_BZero),
.EXC_Ov (EX_EXC_Ov),
.ALU_Stall (EX_ALU_Stall)
);
/*** Execute -> Memory Pipeline Stage ***/
EXMEM_Stage EXMEM (
.clock (clock),
.reset (reset),
.EX_Flush (EX_Exception_Flush),
.EX_Stall (EX_Stall),
.M_Stall (M_Stall),
.EX_Movn (EX_Movn),
.EX_Movz (EX_Movz),
.EX_BZero (EX_BZero),
.EX_RegWrite (EX_RegWrite),
.EX_MemtoReg (EX_MemtoReg),
.EX_ReverseEndian (EX_ReverseEndian),
.EX_LLSC (EX_LLSC),
.EX_MemRead (EX_MemRead),
.EX_MemWrite (EX_MemWrite),
.EX_MemByte (EX_MemByte),
.EX_MemHalf (EX_MemHalf),
.EX_MemSignExtend (EX_MemSignExtend),
.EX_Left (EX_Left),
.EX_Right (EX_Right),
.EX_KernelMode (EX_KernelMode),
.EX_RestartPC (EX_RestartPC),
.EX_IsBDS (EX_IsBDS),
.EX_Trap (EX_Trap),
.EX_TrapCond (EX_TrapCond),
.EX_M_CanErr (EX_M_CanErr),
.EX_ALU_Result (EX_ALUResult),
.EX_ReadData2 (EX_ReadData2_Fwd),
.EX_RtRd (EX_RtRd),
.M_RegWrite (M_RegWrite),
.M_MemtoReg (M_MemtoReg),
.M_ReverseEndian (M_ReverseEndian),
.M_LLSC (M_LLSC),
.M_MemRead (M_MemRead),
.M_MemWrite (M_MemWrite),
.M_MemByte (M_MemByte),
.M_MemHalf (M_MemHalf),
.M_MemSignExtend (M_MemSignExtend),
.M_Left (M_Left),
.M_Right (M_Right),
.M_KernelMode (M_KernelMode),
.M_RestartPC (M_RestartPC),
.M_IsBDS (M_IsBDS),
.M_Trap (M_Trap),
.M_TrapCond (M_TrapCond),
.M_M_CanErr (M_M_CanErr),
.M_ALU_Result (M_ALUResult),
.M_ReadData2 (M_ReadData2_PR),
.M_RtRd (M_RtRd)
);
/*** Trap Detection Unit ***/
TrapDetect TrapDetect (
.Trap (M_Trap),
.TrapCond (M_TrapCond),
.ALUResult (M_ALUResult),
.EXC_Tr (M_EXC_Tr)
);
/*** MEM Write Data Mux ***/
Mux2 #(.WIDTH(32)) MWriteData_Mux (
.sel (M_WriteDataFwdSel),
.in0 (M_ReadData2_PR),
.in1 (WB_WriteData),
.out (M_WriteData_Pre)
);
/*** Data Memory Controller ***/
MemControl DataMem_Controller (
.clock (clock),
.reset (reset),
.DataIn (M_WriteData_Pre),
.Address (M_ALUResult),
.MReadData (DataMem_In),
.MemRead (M_MemRead),
.MemWrite (M_MemWrite),
.DataMem_Ready (DataMem_Ready),
.Byte (M_MemByte),
.Half (M_MemHalf),
.SignExtend (M_MemSignExtend),
.KernelMode (M_KernelMode),
.ReverseEndian (M_ReverseEndian),
.LLSC (M_LLSC),
.ERET (ID_Eret),
.Left (M_Left),
.Right (M_Right),
.M_Exception_Stall (M_Exception_Stall),
.IF_Stall (IF_Stall),
.DataOut (M_MemReadData),
.MWriteData (DataMem_Out),
.WriteEnable (DataMem_Write),
.ReadEnable (DataMem_Read),
.M_Stall (M_Stall_Controller),
.EXC_AdEL (M_EXC_AdEL),
.EXC_AdES (M_EXC_AdES)
);
/*** Memory -> Writeback Pipeline Stage ***/
MEMWB_Stage MEMWB (
.clock (clock),
.reset (reset),
.M_Flush (M_Exception_Flush),
.M_Stall (M_Stall),
.WB_Stall (WB_Stall),
.M_RegWrite (M_RegWrite),
.M_MemtoReg (M_MemtoReg),
.M_ReadData (M_MemReadData),
.M_ALU_Result (M_ALUResult),
.M_RtRd (M_RtRd),
.WB_RegWrite (WB_RegWrite),
.WB_MemtoReg (WB_MemtoReg),
.WB_ReadData (WB_ReadData),
.WB_ALU_Result (WB_ALUResult),
.WB_RtRd (WB_RtRd)
);
/*** WB MemtoReg Mux ***/
Mux2 #(.WIDTH(32)) WBMemtoReg_Mux (
.sel (WB_MemtoReg),
.in0 (WB_ALUResult),
.in1 (WB_ReadData),
.out (WB_WriteData)
);
endmodule

28
demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/README Normal file
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@ -0,0 +1,28 @@
MIPS32-R1 Standalone
--------------------
The files in this directory create a complete MIPS32 processor. The top-level
module is "Processor.v". The interface includes 5 general-purpose hardware
interrupts, a non-maskable hardware interrupt, the 8 pending ISA interrupts
(for diagnostics--this can be removed), and a memory interface for both
instructions and data.
The memory interface is implemented as a four-way handshake:
1. Read/Write request goes high.
2. Ack goes high when data is available.
3. Read/Write request goes low.
4. Ack signal goes low.
____
R/W: __| |____
____
Ack: _____| |____
This interface is simple and robust but can limit the performance of the
system. In the SoC design this is currently the case, since the instruction
memory fetches only once per handshake. This greatly increases the maximum
theoretical IPC from 1 to between 3 and 4.
If your application requires maximum performance out of this processor,
you should modify the memory handshake accordingly.

34
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`timescale 1ns / 1ps
/*
* File : Register.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 7-Jun-2011 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* A variable-width register (d flip-flop) with configurable initial
* value. Default is 32-bit width and 0s for initial value.
*/
module Register #(parameter WIDTH = 32, INIT = 0)(
input clock,
input reset,
input enable,
input [(WIDTH-1):0] D,
output reg [(WIDTH-1):0] Q
);
initial
Q = INIT;
always @(posedge clock) begin
Q <= (reset) ? INIT : ((enable) ? D : Q);
end
endmodule

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`timescale 1ns / 1ps
/*
* File : RegisterFile.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 7-Jun-2011 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* A Register File for a MIPS processor. Contains 32 general-purpose
* 32-bit wide registers and two read ports. Register 0 always reads
* as zero.
*/
module RegisterFile(
input clock,
input reset,
input [4:0] ReadReg1, ReadReg2, WriteReg,
input [31:0] WriteData,
input RegWrite,
output [31:0] ReadData1, ReadData2
);
// Register file of 32 32-bit registers. Register 0 is hardwired to 0s
reg [31:0] registers [1:31];
// Initialize all to zero
integer i;
initial begin
for (i=1; i<32; i=i+1) begin
registers[i] <= 0;
end
end
// Sequential (clocked) write.
// 'WriteReg' is the register index to write. 'RegWrite' is the command.
always @(posedge clock) begin
if (reset) begin
for (i=1; i<32; i=i+1) begin
registers[i] <= 0;
end
end
else begin
if (WriteReg != 0)
registers[WriteReg] <= (RegWrite) ? WriteData : registers[WriteReg];
end
end
// Combinatorial Read. Register 0 is all 0s.
assign ReadData1 = (ReadReg1 == 0) ? 32'h00000000 : registers[ReadReg1];
assign ReadData2 = (ReadReg2 == 0) ? 32'h00000000 : registers[ReadReg2];
endmodule

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`timescale 1ns / 1ps
/*
* File : TrapDetect.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 15-May-2012 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* Detects a Trap Exception in the pipeline.
*/
module TrapDetect(
input Trap,
input TrapCond,
input [31:0] ALUResult,
output EXC_Tr
);
wire ALUZero = (ALUResult == 32'h00000000);
assign EXC_Tr = Trap & (TrapCond ^ ALUZero);
endmodule

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MIPS32-R1 SoC HOWTO
-------------------
This document is a step-by-step procedure for building the MIPS32 hardware
and software and running it on the XUPV5-LX110T FPGA development board. With
minimal changes, other hardware platforms may be used as well (see FAQ).
Procedure
---------
1. Build the software toolchain. Instructions for doing this are located
in the "Software/toolchain" directory.
2. Open the project file "MIPS32-Pipelined-Hw.xise" located in the
"Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw" directory. This is
a Xilinx ISE 14.1 project file.
3. Build the Block RAM core by using the Block Memory Generator in
the Core Generator. See details below.
4. Build the hardware project and generate the programming .bit file.
Send the programming file to the board through Impact (you may need
to create a new Impact project file for your system, but no options
are needed other than the configuration .bit file targeted for the
Virtex-5 device). A default program built into the BRAM will print
a hello message to the LCD screen.
Alternatively, a pre-built .bit file is located in the
"Hardware/XUPV5-LX110T_SoC" directory. It is timed conservatively
at 33 MHz (66 MHz bus).
5. Compile any of the software demos located in "Software/demos" using
the Makefile included with the demo. One of the output files from
the compilation will have a .xum extension. This is a binary file that
contains the code and data for the program. Use the XUM Bootloader
software (Windows) to send the .xum file over a serial port to the
FPGA. When the program is sent, the CPU will reset and run it.
Rebuilding the Block RAM
------------------------
The following settings will allow you to build the Block RAM module
and add a default program to it assuming Xilinx Block Memory Generator
version 7.1): True Dual Port RAM, Common Clock, Byte Write Enable of 8
bits, Write/Read width of 32 bits, Write depth of 151552 (for full
592 KB), Always Enabled, same options for port B, Register Port A Output
of Memory Primitives AND Memory Core (for 2R version, this can be
customized), same settings for Port B, fill remaining locations with
0x00000000, optionally load a .coe file with initial memory contents,
use RSTA and RSTB. The file 'Boot.coe' provides the simple hello message
program.
FAQ
---
Q: What if I don't have the XUPV5-LX110T board?
A: If you have the same Virtex 5 FPGA but a different board, all you need
to do is update the pin locations in the User Constraints File (.ucf)
and either make sure your clock input is 100 MHz or adjust the PLL
in the clocking module of the design accordingly. Note that some
hardware such as the LCD screen or piezo speaker may not be present
on your board, in which case you should remove them from the design.
Q: What if I don't have a Virtex 5 FPGA?
A: Any FPGA can implement this design if it has enough logic resources.
There are only two Xilinx-specific modules in the MIPS32 SoC design;
the clocking module and BRAM module. Replace these with whatever suits
your hardware. Note however that the MIPS32 memory interface uses
byte-width write enables to memory (4 bits per 32-bit word), so if you
use Block Memory or equivalents they must either support this or
you must fake it somehow. You must also update the UCF.
Q: What if I don't have or use the Xilinx development tools?
A: If you only care about the MIPS32 processor and not the full SoC, start
with the "Hardware/MIPS32_Standalone" directory which contains only
Verilog files. The top-most module is "Processor.v". For the full SoC,
copy the "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src" directory
to whatever development environment you use. This directory contains
all of the Verilog files with "Top.v" as the head. The "Clocks" and
"BRAM" directories will need to be customized for your environment,
as well as the pin constraints.
Q: Is there a non-Windows version of the bootloader?
A: No, but the boot protocol is simple and can be implemented for any OS.
See "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/
uart_bootloader_v2.v" for a description of the protocol. If you
implement another version of the bootloader, please contribute it back
to the project.

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<!-- -->
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<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
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<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="src/Simulation/waveform.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc5vlx110t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Virtex5" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
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<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Top_Tester" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events) virtex5" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|Top_Tester" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="MIPS32-Pipelined-Hw" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex5" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-09-08T00:00:44" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AE9A2C604201437980E6BE5F7A73A833" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="src/MIPS32/MIPS_Parameters.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
</project>

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