PWD=$(shell pwd) | PWD=$(shell pwd) | ||||
ifeq ($(TOPLEVEL_LANG),verilog) | ifeq ($(TOPLEVEL_LANG),verilog) | ||||
VERILOG_SOURCES = $(PWD)/../hdl/counter.sv | |||||
VERILOG_SOURCES = $(PWD)/../hdl/counter.v | |||||
else ifeq ($(TOPLEVEL_LANG),vhdl) | else ifeq ($(TOPLEVEL_LANG),vhdl) | ||||
VHDL_SOURCES = $(PWD)/../hdl/counter.vhdl | VHDL_SOURCES = $(PWD)/../hdl/counter.vhdl | ||||
else | else |