ESY1A_B_Seminararbeiten/4-bit-counter-myhdl/main.py

import counter_4bit_conv, counter_4bit_tb
import os

# print("Konvertiere MyHDL Design in Verilog")
# counter_4bit_conv.convert()

print("Simuliere Verilog Design mit MyHDL")
counter_4bit_tb.simulate()

os.system("gtkwave.exe -S run.tcl *.lxt")