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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/4-bit-counter-myhdl/run.tcl

run.tcl 612B
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  1. ### --------------------------------------------------------------------

  2. ### gtkwave.tcl

  3. ### Author: Simon Schmidt

  4. ### --------------------------------------------------------------------

  5. 

  6. # Resources:

  7. # Manual: http://gtkwave.sourceforge.net/gtkwave.pdf#Appendix-E-Tcl-Command-Syntax

  8. 

  9. # Add all signals

  10. set nfacs [ gtkwave::getNumFacs ]

  11. 

  12. set all_facs [list]

  13. for {set i 0} {$i < $nfacs } {incr i} {

  14.     set facname [ gtkwave::getFacName $i ]

  15.     lappend all_facs "$facname"

  16. }

  17. 

  18. set num_added [ gtkwave::addSignalsFromList $all_facs ]

  19. puts "num signals added: $num_added"

  20. 

  21. # zoom full

  22. gtkwave::/Time/Zoom/Zoom_Full