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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/i2c_slave_opencores/README.md

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i2c_slave_opencores

I2C Verilog Testbench für einen CO2 Sensor

Beispiel ist von OpenCores

https://git.efi.th-nuernberg.de/gitea/schmidtsi76327/i2c_slave_opencores