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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/i2c_slave_opencores/bench
Simon Schmidt b3637d6d76 added i2c example from VL 2 years ago
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i2cSlaveTB_defines.v added i2c example from VL 2 years ago
multiByteReadWrite.v added i2c example from VL 2 years ago
testCase0.v added i2c example from VL 2 years ago
testHarness.v added i2c example from VL 2 years ago