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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/i2c_slave_opencores/model
Simon Schmidt b3637d6d76 added i2c example from VL 2 years ago
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i2c_master_bit_ctrl.v added i2c example from VL 2 years ago
i2c_master_byte_ctrl.v added i2c example from VL 2 years ago
i2c_master_defines.v added i2c example from VL 2 years ago
i2c_master_top.v added i2c example from VL 2 years ago
wb_master_model.v added i2c example from VL 2 years ago