schmidtsi76327
/
ESY1A_B_Seminararbeiten
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
11 Commits
1 Branch
Tree: 28af588549
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '28af588549'
${ noResults }
ESY1A_B_Seminararbeiten/LCD_EPD_Simulation_VerilogA/epaper/4_2_rdot_pixel/commands.txt

commands.txt 136B
Raw Blame History

1234 
  1. # Ausführen des Simulators

  2. vasim -c -cmd <Name_CMD>.cmd -do run.do <Name_Testbench>

  3. # Kompilieren der Testbench

  4. valog <quellcode-name>