BlinkProjekt
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## This file is a general .xdc for the Arty A7-100 Rev. D
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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## Clock signal
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#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
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#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
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## Switches
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#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
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#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
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#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
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#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
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## RGB LEDs
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#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
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#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
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#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
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#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
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#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
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#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
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#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
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#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
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#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
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#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
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#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
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#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
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## LEDs
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#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
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#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
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#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
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#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
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## Buttons
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#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
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#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
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#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
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#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
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## Pmod Header JA
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#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
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#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
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#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
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#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
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#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
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#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
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#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
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#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
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## Pmod Header JB
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#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
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#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
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#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
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#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
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#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
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#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
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#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
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#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
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## Pmod Header JC
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#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
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#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
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#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
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#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
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#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
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#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
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#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
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#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
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## Pmod Header JD
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#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
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#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
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#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
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#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
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#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
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#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
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#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
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#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
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## USB-UART Interface
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#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
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#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
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## ChipKit Outer Digital Header
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#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
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#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
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#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
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#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
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#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
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#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
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#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
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#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
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#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
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#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
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#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
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#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
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#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
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#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
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## ChipKit Inner Digital Header
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#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
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#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
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#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
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#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
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#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
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#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
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#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
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#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
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#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
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#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
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#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
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#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
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#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
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#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
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#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
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#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
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## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
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## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
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## WARNING: Do not use both sets of constraints at the same time!
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## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
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#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] ChipKit pin=A0
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#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ChipKit pin=A0
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#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
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#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
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#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] ChipKit pin=A2
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#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] ChipKit pin=A2
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#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_n }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
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#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_p }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
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#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] ChipKit pin=A4
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#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] ChipKit pin=A4
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#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] ChipKit pin=A5
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#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] ChipKit pin=A5
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## ChipKit Outer Analog Header - as Digital I/O
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## NOTE: The following constraints should be used when using these ports as digital I/O.
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#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0]
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#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1]
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#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2]
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#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3]
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#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
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#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
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## ChipKit Inner Analog Header - as Differential Analog Inputs
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## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
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## WARNING: Do not use both sets of constraints at the same time!
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## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
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#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
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#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
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#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
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#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
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#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
|
||||
|
||||
## SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
|
||||
|
||||
## Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Power Measurements
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
|
||||
@@ -0,0 +1,216 @@
|
||||
## This file is a general .xdc for the Arty A7-35 Rev. D
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
|
||||
|
||||
## Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
|
||||
|
||||
## Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
|
||||
|
||||
## USB-UART Interface
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_n }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_p }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: the following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5] ChipKit pin=A5
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit Analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: the following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_io20 }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_io21 }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_io22 }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_io23 }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_io24 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_io25 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
|
||||
|
||||
## SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
|
||||
|
||||
## Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Power Measurements
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
|
||||
@@ -0,0 +1,216 @@
|
||||
## This file is a general .xdc for the ARTY Rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
|
||||
|
||||
## Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
|
||||
|
||||
## Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
|
||||
|
||||
## USB-UART Interface
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_n }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_p }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
|
||||
|
||||
## SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
|
||||
|
||||
## Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Power Measurements
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
|
||||
@@ -0,0 +1,195 @@
|
||||
## This file is a general .xdc for the Arty S7-25 Rev. E
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signals
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { CLK12MHZ }]; #IO_L13P_T2_MRCC_15 Sch=uclk
|
||||
#create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { CLK12MHZ }];
|
||||
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200]
|
||||
#create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000} [get_ports { CLK100MHZ }];
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN M5 IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L23N_T3_FWE_B_15 Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L14N_T2_SRCC_15 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L13N_T2_MRCC_15 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led1_r
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L16P_T2_A28_15 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L15P_T2_DQS_15 Sch=led1_b
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L16N_T2_A27_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L17P_T2_A26_15 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L18P_T2_A24_15 Sch=led[5]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L4P_T0_D04_14 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L5P_T0_D06_14 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L5N_T0_D07_14 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L7P_T1_D09_14 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L7N_T1_D10_14 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja_n[4]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L9P_T1_DQS_14 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L9N_T1_DQS_D13_14 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L10P_T1_D14_14 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L10N_T1_D15_14 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11P_T1_SRCC_14 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L11N_T1_SRCC_14 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L12P_T1_MRCC_14 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L12N_T1_MRCC_14 Sch=jb_n[4]
|
||||
|
||||
## Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN P13 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]
|
||||
|
||||
## Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]
|
||||
|
||||
## USB-UART Interface
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_0_14 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[9]
|
||||
|
||||
## ChipKit SPI Header
|
||||
## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time.
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L22P_T3_A17_15 Sch=ck_io10_ss
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_mosi
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L14P_T2_SRCC_15 Sch=ck_io13_sck
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
## NOTE: these pins are shared with PMOD Headers JC and JD and cannot be used at the same time as the applicable PMOD interface(s)
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN P13 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
|
||||
|
||||
## Dedicated Analog Inputs
|
||||
#set_property -dict { PACKAGE_PIN J10 } [get_ports { vp_in }]; #IO_L1P_T0_AD4P_35 Sch=v_p
|
||||
#set_property -dict { PACKAGE_PIN K9 } [get_ports { vn_in }]; #IO_L1N_T0_AD4N_35 Sch=v_n
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS33 } [get_ports { vaux2_p }]; #IO_L5P_T0_AD9P_15 Sch=ck_an_p[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { vaux2_n }]; #IO_L5N_T0_AD9N_15 Sch=ck_an_n[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vaux10_p }]; #IO_L7P_T1_AD2P_15 Sch=ck_an_p[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { vaux10_n }]; #IO_L7N_T1_AD2N_15 Sch=ck_an_n[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { vaux3_p }]; #IO_L8P_T1_AD10P_15 Sch=ck_an_p[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { vaux3_n }]; #IO_L8N_T1_AD10N_15 Sch=ck_an_n[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L10P_T1_AD11P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L10N_T1_AD11N_15 Sch=ck_an_n[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_15 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_15 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_15 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_15 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_15 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_15 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_15 Sch=ad_p[8] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_15 Sch=ad_n[8] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { vaux11_p }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { vaux11_n }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3] ChipKit pin=A9
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L2P_T0_AD8P_15 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L2N_T0_AD8N_15 Sch=ad_n[8]
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L12P_T1_MRCC_15 Sch=ck_a10_r (Cannot be used as an analog input)
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L12N_T1_MRCC_15 Sch=ck_a11_r (Cannot be used as an analog input)
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_RS0_15 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_RS1_15 Sch=ck_sda
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_25_15 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L11N_T1_SRCC_15
|
||||
|
||||
## Quad SPI Flash
|
||||
## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
|
||||
## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
|
||||
## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
|
||||
## and to be able to use this pin as an ordinary I/O the following property must
|
||||
## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
|
||||
## used the internal reference is set to half that value (i.e. 0.675v). Note that
|
||||
## this property must be set even if SW3 is not used in the design.
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
@@ -0,0 +1,195 @@
|
||||
## This file is a general .xdc for the Arty S7-50 Rev. E
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signals
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { CLK12MHZ }]; #IO_L13P_T2_MRCC_15 Sch=uclk
|
||||
#create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { CLK12MHZ }];
|
||||
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200]
|
||||
#create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000} [get_ports { CLK100MHZ }];
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN M5 IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L23N_T3_FWE_B_15 Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L14N_T2_SRCC_15 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L13N_T2_MRCC_15 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led1_r
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L16P_T2_A28_15 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L15P_T2_DQS_15 Sch=led1_b
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L16N_T2_A27_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L17P_T2_A26_15 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L18P_T2_A24_15 Sch=led[5]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L4P_T0_D04_14 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L5P_T0_D06_14 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L5N_T0_D07_14 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L7P_T1_D09_14 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L7N_T1_D10_14 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja_n[4]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L9P_T1_DQS_14 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L9N_T1_DQS_D13_14 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L10P_T1_D14_14 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L10N_T1_D15_14 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11P_T1_SRCC_14 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L11N_T1_SRCC_14 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L12P_T1_MRCC_14 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L12N_T1_MRCC_14 Sch=jb_n[4]
|
||||
|
||||
## Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN P13 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]
|
||||
|
||||
## Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]
|
||||
|
||||
## USB-UART Interface
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_0_14 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[9]
|
||||
|
||||
## ChipKit SPI Header
|
||||
## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time.
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L22P_T3_A17_15 Sch=ck_io10_ss
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_mosi
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L14P_T2_SRCC_15 Sch=ck_io13_sck
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
## Note: these pins are shared with PMOD Headers JC and JD and cannot be used at the same time as the applicable PMOD interface(s)
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN P13 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
|
||||
|
||||
## Dedicated Analog Inputs
|
||||
#set_property -dict { PACKAGE_PIN J10 } [get_ports { vp_in }]; #IO_L1P_T0_AD4P_35 Sch=v_p
|
||||
#set_property -dict { PACKAGE_PIN K9 } [get_ports { vn_in }]; #IO_L1N_T0_AD4N_35 Sch=v_n
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_15 Sch=ck_an_p[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_15 Sch=ck_an_n[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vaux2_p }]; #IO_L7P_T1_AD2P_15 Sch=ck_an_p[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { vaux2_n }]; #IO_L7N_T1_AD2N_15 Sch=ck_an_n[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { vaux10_p }]; #IO_L8P_T1_AD10P_15 Sch=ck_an_p[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { vaux10_n }]; #IO_L8N_T1_AD10N_15 Sch=ck_an_n[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { vaux11_p }]; #IO_L10P_T1_AD11P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux11_n }]; #IO_L10N_T1_AD11N_15 Sch=ck_an_n[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_15 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_15 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_15 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_15 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_15 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_15 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_15 Sch=ad_p[8] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_15 Sch=ad_n[8] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { vaux3_p }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { vaux3_n }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3] ChipKit pin=A9
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L2P_T0_AD8P_15 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L2N_T0_AD8N_15 Sch=ad_n[8]
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L12P_T1_MRCC_15 Sch=ck_a10_r (Cannot be used as an analog input)
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L12N_T1_MRCC_15 Sch=ck_a11_r (Cannot be used as an analog input)
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_RS0_15 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_RS1_15 Sch=ck_sda
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_25_15 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L11N_T1_SRCC_15
|
||||
|
||||
## Quad SPI Flash
|
||||
## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
|
||||
## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
|
||||
## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
|
||||
## and to be able to use this pin as an ordinary I/O the following property must
|
||||
## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
|
||||
## used the internal reference is set to half that value (i.e. 0.675v). Note that
|
||||
## this property must be set even if SW3 is not used in the design.
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
@@ -0,0 +1,154 @@
|
||||
## This file is a general .xdc for the ARTY Z7-10 Rev.B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=SW0
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=SW1
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7P_35 Sch=LED4_B
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=LED4_G
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=LED4_R
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=LED5_B
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=LED5_G
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=LED5_R
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L6N_T0_VREF_34 Sch=LED0
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L6P_T0_34 Sch=LED1
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=LED2
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L23P_T3_35 Sch=LED3
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4P_T0_35 Sch=BTN0
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_35 Sch=BTN1
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=BTN2
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=BTN3
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P (Pin 1)
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N (Pin 2)
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P (Pin 3)
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N (Pin 4)
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P (Pin 7)
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N (Pin 8)
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P (Pin 9)
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N (Pin 10)
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L8P_T1_34 Sch=JB1_P (Pin 1)
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L8N_T1_34 Sch=JB1_N (Pin 2)
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L1P_T0_34 Sch=JB2_P (Pin 3)
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L1N_T0_34 Sch=JB2_N (Pin 4)
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L18P_T2_34 Sch=JB3_P (Pin 7)
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L18N_T2_34 Sch=JB3_N (Pin 8)
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb_p[4] }]; #IO_L4P_T0_34 Sch=JB4_P (Pin 9)
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb_n[4] }]; #IO_L4N_T0_34 Sch=JB4_N (Pin 10)
|
||||
|
||||
## Audio Out
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L20N_T3_34 Sch=AUD_PWM
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L20P_T3_34 Sch=AUD_SD
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=CRYPTO_SDA
|
||||
|
||||
## HDMI RX Signals
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=HDMI_RX_CEC
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=HDMI_RX_HPD
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA
|
||||
|
||||
## HDMI TX Signals
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=HDMI_TX_CEC
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]; #IO_0_34 Sch=HDMI_TX_HDPN
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L8P_T1_AD10P_35 Sch=HDMI_TX_SCL
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L8N_T1_AD10N_35 Sch=HDMI_TX_SDA
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L5P_T0_34 Sch=CK_IO0
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L2N_T0_34 Sch=CK_IO1
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=CK_IO2
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L3N_T0_DQS_34 Sch=CK_IO3
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L10P_T1_34 Sch=CK_IO4
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L5N_T0_34 Sch=CK_IO5
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19P_T3_34 Sch=CK_IO6
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L9N_T1_DQS_34 Sch=CK_IO7
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L21P_T3_DQS_34 Sch=CK_IO8
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L21N_T3_DQS_34 Sch=CK_IO9
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L9P_T1_DQS_34 Sch=CK_IO10
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L19N_T3_VREF_34 Sch=CK_IO11
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L23N_T3_34 Sch=CK_IO12
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L23P_T3_34 Sch=CK_IO13
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
## Not Connected on Z7-10 Variant
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports should be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) with the XADC IP core.
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=CK_AN0_N ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=CK_AN0_P ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=CK_AN1_N ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=CK_AN1_P ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=CK_AN2_N ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=CK_AN2_P ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=CK_AN3_N ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=CK_AN3_P ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=CK_AN4_N ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=CK_AN4_P ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=CK_AN5_N ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=CK_AN5_P ChipKit pin=A5
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=AD0_P ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=AD0_N ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=AD8_N ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L1P_T0_AD0P_35 Sch=AD0_P
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L1N_T0_AD0N_35 Sch=AD0_N
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=AD8_N
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=CK_MISO
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=CK_MISO
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=CK_SCK
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=CK_SS
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=CK_SCL
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=CK_SDA
|
||||
|
||||
## Not Connected Pins
|
||||
#set_property PACKAGE_PIN F17 [get_ports {netic20_f17}]; #IO_L6N_T0_VREF_35
|
||||
#set_property PACKAGE_PIN G18 [get_ports {netic20_g18}]; #IO_L16N_T2_35
|
||||
@@ -0,0 +1,185 @@
|
||||
## This file is a general .xdc for the ARTY Z7-20 Rev.B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=SW0
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=SW1
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7P_35 Sch=LED4_B
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=LED4_G
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=LED4_R
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=LED5_B
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=LED5_G
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=LED5_R
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L6N_T0_VREF_34 Sch=LED0
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L6P_T0_34 Sch=LED1
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=LED2
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L23P_T3_35 Sch=LED3
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4P_T0_35 Sch=BTN0
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_35 Sch=BTN1
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=BTN2
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=BTN3
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P (Pin 1)
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N (Pin 2)
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P (Pin 3)
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N (Pin 4)
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P (Pin 7)
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N (Pin 8)
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P (Pin 9)
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N (Pin 10)
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L8P_T1_34 Sch=JB1_P (Pin 1)
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L8N_T1_34 Sch=JB1_N (Pin 2)
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L1P_T0_34 Sch=JB2_P (Pin 3)
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L1N_T0_34 Sch=JB2_N (Pin 4)
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L18P_T2_34 Sch=JB3_P (Pin 7)
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L18N_T2_34 Sch=JB3_N (Pin 8)
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb_p[4] }]; #IO_L4P_T0_34 Sch=JB4_P (Pin 9)
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb_n[4] }]; #IO_L4N_T0_34 Sch=JB4_N (Pin 10)
|
||||
|
||||
## Audio Out
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L20N_T3_34 Sch=AUD_PWM
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L20P_T3_34 Sch=AUD_SD
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=CRYPTO_SDA
|
||||
|
||||
## HDMI RX Signals
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=HDMI_RX_CEC
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=HDMI_RX_HPD
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA
|
||||
|
||||
## HDMI TX Signals
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=HDMI_TX_CEC
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]; #IO_0_34 Sch=HDMI_TX_HDPN
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L8P_T1_AD10P_35 Sch=HDMI_TX_SCL
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L8N_T1_AD10N_35 Sch=HDMI_TX_SDA
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L5P_T0_34 Sch=CK_IO0
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L2N_T0_34 Sch=CK_IO1
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=CK_IO2
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L3N_T0_DQS_34 Sch=CK_IO3
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L10P_T1_34 Sch=CK_IO4
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L5N_T0_34 Sch=CK_IO5
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19P_T3_34 Sch=CK_IO6
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L9N_T1_DQS_34 Sch=CK_IO7
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L21P_T3_DQS_34 Sch=CK_IO8
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L21N_T3_DQS_34 Sch=CK_IO9
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L9P_T1_DQS_34 Sch=CK_IO10
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L19N_T3_VREF_34 Sch=CK_IO11
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L23N_T3_34 Sch=CK_IO12
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L23P_T3_34 Sch=CK_IO13
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_VREF_13 Sch=CK_IO26
|
||||
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L6N_T0_VREF_13 Sch=CK_IO27
|
||||
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L22P_T3_13 Sch=CK_IO28
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L11P_T1_SRCC_13 Sch=CK_IO29
|
||||
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L11N_T1_SRCC_13 Sch=CK_IO30
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L17N_T2_13 Sch=CK_IO31
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L15P_T2_DQS_13 Sch=CK_IO32
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L21N_T3_DQS_13 Sch=CK_IO33
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L16P_T2_13 Sch=CK_IO34
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L22N_T3_13 Sch=CK_IO35
|
||||
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L13N_T2_MRCC_13 Sch=CK_IO36
|
||||
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L13P_T2_MRCC_13 Sch=cCK_IO37
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_13 Sch=CK_IO38
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_SRCC_13 Sch=CK_IO39
|
||||
#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_13 Sch=CK_IO40
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L14P_T2_SRCC_13 Sch=CK_IO41
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=CK_AN0_N ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=CK_AN0_P ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=CK_AN1_N ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=CK_AN1_P ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=CK_AN2_N ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=CK_AN2_P ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=CK_AN3_N ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=CK_AN3_P ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=CK_AN4_N ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=CK_AN4_P ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=CK_AN5_N ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=CK_AN5_P ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L18N_T2_13 Sch=CK_A0
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L20P_T3_13 Sch=CK_A1
|
||||
#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L18P_T2_13 Sch=CK_A2
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L21P_T3_DQS_13 Sch=CK_A3
|
||||
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L19P_T3_13 Sch=CK_A4
|
||||
#set_property -dict { PACKAGE_PIN U10 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L12N_T1_MRCC_13 Sch=CK_A5
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=AD0_P ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=AD0_N ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=AD8_N ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L1P_T0_AD0P_35 Sch=AD0_P
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L1N_T0_AD0N_35 Sch=AD0_N
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=AD8_N
|
||||
|
||||
## ChipKit SPI
|
||||
## NOTE: The ChipKit SPI header ports can also be used as digital I/O
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=CK_MISO
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=CK_MISO
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=CK_SCK
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=CK_SS
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=CK_SCL
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=CK_SDA
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L20N_T3_13 Sch=CK_IOA
|
||||
|
||||
## Not Connected Pins
|
||||
#set_property PACKAGE_PIN F17 [get_ports {netic20_f17}]; #IO_L6N_T0_VREF_35
|
||||
#set_property PACKAGE_PIN G18 [get_ports {netic20_g18}]; #IO_L16N_T2_35
|
||||
#set_property PACKAGE_PIN T9 [get_ports {netic20_t9}]; #IO_L12P_T1_MRCC_13
|
||||
#set_property PACKAGE_PIN U9 [get_ports {netic20_u9}]; #IO_L17P_T2_13
|
||||
@@ -0,0 +1,154 @@
|
||||
## This file is a general .xdc for the Basys3 rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {sw[0]}]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {sw[1]}]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
|
||||
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
|
||||
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
|
||||
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
|
||||
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
|
||||
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
|
||||
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
|
||||
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
|
||||
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
|
||||
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]
|
||||
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
|
||||
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}]
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}]
|
||||
#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}]
|
||||
#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}]
|
||||
#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}]
|
||||
#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}]
|
||||
#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}]
|
||||
#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}]
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}]
|
||||
|
||||
|
||||
##7 Segment Display
|
||||
#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {seg[0]}]
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {seg[1]}]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {seg[2]}]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {seg[3]}]
|
||||
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {seg[4]}]
|
||||
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {seg[5]}]
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {seg[6]}]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports dp]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {an[0]}]
|
||||
#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {an[1]}]
|
||||
#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {an[2]}]
|
||||
#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {an[3]}]
|
||||
|
||||
|
||||
##Buttons
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU]
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD]
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1
|
||||
#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10
|
||||
|
||||
##Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10
|
||||
|
||||
##Pmod Header JXADC
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P
|
||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P
|
||||
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P
|
||||
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P
|
||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N
|
||||
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N
|
||||
#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N
|
||||
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N
|
||||
|
||||
|
||||
##VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync]
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx]
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data]
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
||||
##STARTUPE2 primitive.
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn]
|
||||
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
@@ -0,0 +1,132 @@
|
||||
## This file is a general .xdc for the CmodA7 rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## 12 MHz Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
|
||||
#create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}];
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2]
|
||||
|
||||
## RGB LED
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L14N_T2_SRCC_16 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L13N_T2_MRCC_16 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L14P_T2_SRCC_16 Sch=led0_r
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L5N_T0_D07_14 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L9P_T1_DQS_14 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L8P_T1_D11_14 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L4P_T0_D04_14 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L6N_T0_D08_VREF_14 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja[10]
|
||||
|
||||
## Analog XADC Pins
|
||||
## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]
|
||||
|
||||
## GPIO Pins
|
||||
## Pins 15 and 16 should remain commented if using them as analog inputs
|
||||
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { pio1 }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
|
||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports { pio2 }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { pio3 }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
|
||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports { pio4 }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { pio5 }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { pio6 }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { pio7 }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { pio8 }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { pio9 }]; #IO_L6P_T0_16 Sch=pio[09]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { pio10 }]; #IO_L7P_T1_AD6P_35 Sch=pio[10]
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports { pio11 }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { pio12 }]; #IO_L5P_T0_AD13P_35 Sch=pio[12]
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports { pio13 }]; #IO_L6N_T0_VREF_35 Sch=pio[13]
|
||||
#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports { pio14 }]; #IO_L5N_T0_AD13N_35 Sch=pio[14]
|
||||
#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports { pio17 }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17]
|
||||
#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports { pio18 }]; #IO_L12P_T1_MRCC_35 Sch=pio[18]
|
||||
#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { pio19 }]; #IO_L12N_T1_MRCC_35 Sch=pio[19]
|
||||
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports { pio20 }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20]
|
||||
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports { pio21 }]; #IO_L10N_T1_AD15N_35 Sch=pio[21]
|
||||
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports { pio22 }]; #IO_L10P_T1_AD15P_35 Sch=pio[22]
|
||||
#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { pio23 }]; #IO_L19N_T3_VREF_35 Sch=pio[23]
|
||||
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { pio26 }]; #IO_L2P_T0_34 Sch=pio[26]
|
||||
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports { pio27 }]; #IO_L2N_T0_34 Sch=pio[27]
|
||||
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports { pio28 }]; #IO_L1P_T0_34 Sch=pio[28]
|
||||
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports { pio29 }]; #IO_L3P_T0_DQS_34 Sch=pio[29]
|
||||
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports { pio30 }]; #IO_L1N_T0_34 Sch=pio[30]
|
||||
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports { pio31 }]; #IO_L3N_T0_DQS_34 Sch=pio[31]
|
||||
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports { pio32 }]; #IO_L5N_T0_34 Sch=pio[32]
|
||||
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports { pio33 }]; #IO_L5P_T0_34 Sch=pio[33]
|
||||
#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports { pio34 }]; #IO_L6N_T0_VREF_34 Sch=pio[34]
|
||||
#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { pio35 }]; #IO_L6P_T0_34 Sch=pio[35]
|
||||
#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { pio36 }]; #IO_L12P_T1_MRCC_34 Sch=pio[36]
|
||||
#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports { pio37 }]; #IO_L11N_T1_SRCC_34 Sch=pio[37]
|
||||
#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports { pio38 }]; #IO_L11P_T1_SRCC_34 Sch=pio[38]
|
||||
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { pio39 }]; #IO_L16N_T2_34 Sch=pio[39]
|
||||
#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports { pio40 }]; #IO_L12N_T1_MRCC_34 Sch=pio[40]
|
||||
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { pio41 }]; #IO_L16P_T2_34 Sch=pio[41]
|
||||
#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports { pio42 }]; #IO_L9N_T1_DQS_34 Sch=pio[42]
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { pio43 }]; #IO_L13N_T2_MRCC_34 Sch=pio[43]
|
||||
#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { pio44 }]; #IO_L9P_T1_DQS_34 Sch=pio[44]
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { pio45 }]; #IO_L19P_T3_34 Sch=pio[45]
|
||||
#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { pio46 }]; #IO_L13P_T2_MRCC_34 Sch=pio[46]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { pio47 }]; #IO_L14P_T2_SRCC_34 Sch=pio[47]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { pio48 }]; #IO_L14N_T2_SRCC_34 Sch=pio[48]
|
||||
|
||||
## UART
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
|
||||
|
||||
## Crypto 1 Wire Interface
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_0_14 Sch=crypto_sda
|
||||
|
||||
## QSPI
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Cellular RAM
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[0] }]; #IO_L11P_T1_SRCC_14 Sch=sram- a[0]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[1] }]; #IO_L11N_T1_SRCC_14 Sch=sram- a[1]
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[2] }]; #IO_L12N_T1_MRCC_14 Sch=sram- a[2]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[3] }]; #IO_L13P_T2_MRCC_14 Sch=sram- a[3]
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[4] }]; #IO_L13N_T2_MRCC_14 Sch=sram- a[4]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[5] }]; #IO_L14P_T2_SRCC_14 Sch=sram- a[5]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[6] }]; #IO_L14N_T2_SRCC_14 Sch=sram- a[6]
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[7] }]; #IO_L16N_T2_A15_D31_14 Sch=sram- a[7]
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[8] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram- a[8]
|
||||
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[9] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram- a[9]
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[10] }]; #IO_L16P_T2_CSI_B_14 Sch=sram- a[10]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[11] }]; #IO_L17P_T2_A14_D30_14 Sch=sram- a[11]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[12] }]; #IO_L17N_T2_A13_D29_14 Sch=sram- a[12]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[13] }]; #IO_L18P_T2_A12_D28_14 Sch=sram- a[13]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[14] }]; #IO_L18N_T2_A11_D27_14 Sch=sram- a[14]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[15] }]; #IO_L19P_T3_A10_D26_14 Sch=sram- a[15]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[16] }]; #IO_L20P_T3_A08_D24_14 Sch=sram- a[16]
|
||||
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[17] }]; #IO_L20N_T3_A07_D23_14 Sch=sram- a[17]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[18] }]; #IO_L21P_T3_DQS_14 Sch=sram- a[18]
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { MemDB[0] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram-dq[0]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { MemDB[1] }]; #IO_L22P_T3_A05_D21_14 Sch=sram-dq[1]
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { MemDB[2] }]; #IO_L22N_T3_A04_D20_14 Sch=sram-dq[2]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { MemDB[3] }]; #IO_L23P_T3_A03_D19_14 Sch=sram-dq[3]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { MemDB[4] }]; #IO_L23N_T3_A02_D18_14 Sch=sram-dq[4]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { MemDB[5] }]; #IO_L24P_T3_A01_D17_14 Sch=sram-dq[5]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { MemDB[6] }]; #IO_L24N_T3_A00_D16_14 Sch=sram-dq[6]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { MemDB[7] }]; #IO_25_14 Sch=sram-dq[7]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { RamOEn }]; #IO_L10P_T1_D14_14 Sch=sram-oe
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { RamWEn }]; #IO_L10N_T1_D15_14 Sch=sram-we
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports { RamCEn }]; #IO_L9N_T1_DQS_D13_14 Sch=sram-ce
|
||||
|
||||
@@ -0,0 +1,90 @@
|
||||
## This file is a general .xdc for the Cmod S7-25 Rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## 12 MHz System Clock
|
||||
#set_property -dict { PACKAGE_PIN M9 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_14 Sch=gclk
|
||||
#create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { clk }];
|
||||
|
||||
## Push Buttons
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6P_T0_34 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN D1 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L6N_T0_VREF_34 Sch=btn[1]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L10N_T1_34 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L9N_T1_DQS_34 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN F2 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L10P_T1_34 Sch=led0_r
|
||||
|
||||
## 4 LEDs
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L8P_T1_34 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L16P_T2_34 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L16N_T2_34 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8N_T1_34 Sch=led[4]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L14P_T2_SRCC_34 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L14N_T2_SRCC_34 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L13P_T2_MRCC_34 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L11N_T1_SRCC_34 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L13N_T2_MRCC_34 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12P_T1_MRCC_34 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L12N_T1_MRCC_34 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L11P_T1_SRCC_34 Sch=ja[10]
|
||||
|
||||
## USB UART
|
||||
## Note: Port names are from the perspoctive of the FPGA.
|
||||
#set_property -dict { PACKAGE_PIN L12 IOSTANDARD LVCMOS33 } [get_ports { uart_tx }]; #IO_L6N_T0_D08_VREF_14 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { uart_rx }]; #IO_L5N_T0_D07_14 Sch=uart_txd_in
|
||||
|
||||
## Analog Inputs on PIO Pins 32 and 33
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=ain_p[32]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=ain_n[32]
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=ain_p[33]
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=ain_n[33]
|
||||
|
||||
## Dedicated Digital I/O on the PIO Headers
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports { pio1 }]; #IO_L18N_T2_34 Sch=pio[01]
|
||||
#set_property -dict { PACKAGE_PIN M4 IOSTANDARD LVCMOS33 } [get_ports { pio2 }]; #IO_L19P_T3_34 Sch=pio[02]
|
||||
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { pio3 }]; #IO_L19N_T3_VREF_34 Sch=pio[03]
|
||||
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports { pio4 }]; #IO_L20P_T3_34 Sch=pio[04]
|
||||
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports { pio5 }]; #IO_L20N_T3_34 Sch=pio[05]
|
||||
#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { pio6 }]; #IO_L21P_T3_DQS_34 Sch=pio[06]
|
||||
#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports { pio7 }]; #IO_L21N_T3_DQS_34 Sch=pio[07]
|
||||
#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { pio8 }]; #IO_L22P_T3_34 Sch=pio[08]
|
||||
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports { pio9 }]; #IO_L22N_T3_34 Sch=pio[09]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { pio16 }]; #IO_L11P_T1_SRCC_14 Sch=pio[16]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { pio17 }]; #IO_L11N_T1_SRCC_14 Sch=pio[17]
|
||||
#set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 } [get_ports { pio18 }]; #IO_L8N_T1_D12_14 Sch=pio[18]
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { pio19 }]; #IO_L10N_T1_D15_14 Sch=pio[19]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { pio20 }]; #IO_L10P_T1_D14_14 Sch=pio[20]
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { pio21 }]; #IO_L9N_T1_DQS_D13_14 Sch=pio[21]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { pio22 }]; #IO_L9P_T1_DQS_14 Sch=pio[22]
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { pio23 }]; #IO_L4N_T0_D05_14 Sch=pio[23]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { pio26 }]; #IO_L7N_T1_D10_14 Sch=pio[26]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { pio27 }]; #IO_L4P_T0_D04_14 Sch=pio[27]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pio28 }]; #IO_L5P_T0_D06_14 Sch=pio[28]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { pio29 }]; #IO_L7P_T1_D09_14 Sch=pio[29]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { pio30 }]; #IO_L8P_T1_D11_14 Sch=pio[30]
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS33 } [get_ports { pio31 }]; #IO_0_14 Sch=pio[31]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { pio40 }]; #IO_L5P_T0_34 Sch=pio[40]
|
||||
#set_property -dict { PACKAGE_PIN A2 IOSTANDARD LVCMOS33 } [get_ports { pio41 }]; #IO_L2N_T0_34 Sch=pio[41]
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { pio42 }]; #IO_L2P_T0_34 Sch=pio[42]
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { pio43 }]; #IO_L4N_T0_34 Sch=pio[43]
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { pio44 }]; #IO_L4P_T0_34 Sch=pio[44]
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { pio45 }]; #IO_L3N_T0_DQS_34 Sch=pio[45]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { pio46 }]; #IO_L3P_T0_DQS_34 Sch=pio[46]
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { pio47 }]; #IO_L1N_T0_34 Sch=pio[47]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { pio48 }]; #IO_L1P_T0_34 Sch=pio[48]
|
||||
|
||||
## Quad SPI Flash
|
||||
## Note: QSPI clock can only be accessed through the STARTUPE2 primitive
|
||||
#set_property -dict { PACKAGE_PIN L11 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
@@ -0,0 +1,150 @@
|
||||
## This file is a general .xdc for the Cora Z7-07S Rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## PL System Clock
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L16P_T2_35 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_0_35 Sch=led1_b
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L22P_T3_AD7P_35 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L23N_T3_35 Sch=led1_r
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4N_T0_35 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4P_T0_35 Sch=btn[1]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L17P_T2_34 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L17N_T2_34 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L7P_T1_34 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L7N_T1_34 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4]
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }];
|
||||
|
||||
## Dedicated Analog Inputs
|
||||
#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVCMOS33 } [get_ports { v_p }]; #VP_0 Sch=xadc_v_p
|
||||
#set_property -dict { PACKAGE_PIN L10 IOSTANDARD LVCMOS33 } [get_ports { v_n }]; #VN_0 Sch=xadc_v_n
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3]
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5]
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L10N_T1_AD11N_35 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L12P_T1_MRCC_35 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L6P_T0_34 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L5P_T0_34 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L5N_T0_34 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L21P_T3_DQS_34 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L21N_T3_DQS_34 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19N_T3_VREF_34 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L6N_T0_VREF_34 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L13P_T2_MRCC_34 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L11N_T1_SRCC_34 Sch=ck_io[10]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L12N_T1_MRCC_35 Sch=ck_io[11]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12]
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L19N_T3_VREF_35 Sch=ck_io[13]
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19P_T3_34 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L2N_T0_34 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L10P_T1_34 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L9P_T1_DQS_34 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L9N_T1_DQS_34 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L20P_T3_34 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_34 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L23N_T3_34 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L23P_T3_34 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_AD10P_35 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L11N_T1_SRCC_35 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L13N_T2_MRCC_35 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_35 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9N_T1_DQS_AD3N_35 Sch=ck_io[41]
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=ck_sda
|
||||
|
||||
##Misc. ChipKit signals
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L7N_T1_AD2N_35 Sch=ck_ioa
|
||||
|
||||
## User Digital I/O Header J1
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[1] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=user_dio[1]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[2] }]; #IO_L7P_T1_AD2P_35 Sch=user_dio[2]
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[3] }]; #IO_L14P_T2_SRCC_34 Sch=user_dio[3]
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[4] }]; #IO_L14N_T2_SRCC_34 Sch=user_dio[4]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[5] }]; #IO_L13N_T2_MRCC_34 Sch=user_dio[5]
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[6] }]; #IO_0_34 Sch=user_dio[6]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[7] }]; #IO_L15P_T2_DQS_34 Sch=user_dio[7]
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[8] }]; #IO_25_34 Sch=user_dio[8]
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[9] }]; #IO_L15N_T2_DQS_34 Sch=user_dio[9]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[10] }]; #IO_L16P_T2_34 Sch=user_dio[10]
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[11] }]; #IO_L16N_T2_34 Sch=user_dio[11]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[12] }]; #IO_L10P_T1_AD11P_35 Sch=user_dio[12]
|
||||
@@ -0,0 +1,152 @@
|
||||
## This file is a general .xdc for the Cora Z7-10 Rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## PL System Clock
|
||||
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk]
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
|
||||
|
||||
## RGB LEDs
|
||||
set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
|
||||
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L16P_T2_35 Sch=led0_g
|
||||
set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
|
||||
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports led]
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_0_35 Sch=led1_b
|
||||
set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L22P_T3_AD7P_35 Sch=led1_g
|
||||
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L23N_T3_35 Sch=led1_r
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4N_T0_35 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4P_T0_35 Sch=btn[1]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L17P_T2_34 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L17N_T2_34 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L7P_T1_34 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L7N_T1_34 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4]
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }];
|
||||
|
||||
## Dedicated Analog Inputs
|
||||
#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVCMOS33 } [get_ports { v_p }]; #VP_0 Sch=xadc_v_p
|
||||
#set_property -dict { PACKAGE_PIN L10 IOSTANDARD LVCMOS33 } [get_ports { v_n }]; #VN_0 Sch=xadc_v_n
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3]
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5]
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L10N_T1_AD11N_35 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L12P_T1_MRCC_35 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L6P_T0_34 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L5P_T0_34 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L5N_T0_34 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L21P_T3_DQS_34 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L21N_T3_DQS_34 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19N_T3_VREF_34 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L6N_T0_VREF_34 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L13P_T2_MRCC_34 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L11N_T1_SRCC_34 Sch=ck_io[10]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L12N_T1_MRCC_35 Sch=ck_io[11]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12]
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L19N_T3_VREF_35 Sch=ck_io[13]
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19P_T3_34 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L2N_T0_34 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L10P_T1_34 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L9P_T1_DQS_34 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L9N_T1_DQS_34 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L20P_T3_34 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_34 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L23N_T3_34 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L23P_T3_34 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_AD10P_35 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L11N_T1_SRCC_35 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L13N_T2_MRCC_35 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_35 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9N_T1_DQS_AD3N_35 Sch=ck_io[41]
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=ck_sda
|
||||
|
||||
##Misc. ChipKit signals
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L7N_T1_AD2N_35 Sch=ck_ioa
|
||||
|
||||
## User Digital I/O Header J1
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[1] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=user_dio[1]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[2] }]; #IO_L7P_T1_AD2P_35 Sch=user_dio[2]
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[3] }]; #IO_L14P_T2_SRCC_34 Sch=user_dio[3]
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[4] }]; #IO_L14N_T2_SRCC_34 Sch=user_dio[4]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[5] }]; #IO_L13N_T2_MRCC_34 Sch=user_dio[5]
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[6] }]; #IO_0_34 Sch=user_dio[6]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[7] }]; #IO_L15P_T2_DQS_34 Sch=user_dio[7]
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[8] }]; #IO_25_34 Sch=user_dio[8]
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[9] }]; #IO_L15N_T2_DQS_34 Sch=user_dio[9]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[10] }]; #IO_L16P_T2_34 Sch=user_dio[10]
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[11] }]; #IO_L16N_T2_34 Sch=user_dio[11]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[12] }]; #IO_L10P_T1_AD11P_35 Sch=user_dio[12]
|
||||
|
||||
@@ -0,0 +1,115 @@
|
||||
## This file is a general .xdc for the Eclypse Z7 Rev. B.0
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## 125MHz Clock from Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC Sch=sysclk
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L11P_T1_SRCC Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11N_T1_SRCC Sch=btn[1]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L9N_T1_DQS_AD3N Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L8P_T1_AD10P Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L8N_T1_AD10N Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L9P_T1_DQS_AD3P Sch=led1_b
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L10P_T1_AD11P Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN A19 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L10N_T1_AD11N Sch=led1_r
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0 Sch=ja1_fpga
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_25 Sch=ja2_fpga
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L1N_T0_AD0N Sch=ja3_fpga
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L1P_T0_AD0P Sch=ja4_fpga
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L2N_T0_AD8N Sch=ja7_fpga
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L2P_T0_AD8P Sch=ja8_fpga
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L3N_T0_DQS_AD1N Sch=ja9_fpga
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L3P_T0_DQS_AD1P Sch=ja10_fpga
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L4N_T0 Sch=jb1_fpga
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L4P_T0 Sch=jb2_fpga
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L5N_T0_AD9N Sch=jb3_fpga
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L5P_T0_AD9P Sch=jb4_fpga
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6N_T0_VREF Sch=jb7_fpga
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L6P_T0 Sch=jb8_fpga
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L7N_T1_AD2N Sch=jb9_fpga
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L7P_T1_AD2P Sch=jb10_fpga
|
||||
|
||||
## Syzygy Port A
|
||||
#set_property -dict { PACKAGE_PIN N20 } [get_ports { syzygy_a_c2p_clk_n }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n
|
||||
#set_property -dict { PACKAGE_PIN N19 } [get_ports { syzygy_a_c2p_clk_p }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p
|
||||
#set_property -dict { PACKAGE_PIN T17 } [get_ports { syzygy_a_d_n[0] }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN T16 } [get_ports { syzygy_a_d_p[0] }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN T19 } [get_ports { syzygy_a_d_n[1] }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN R19 } [get_ports { syzygy_a_d_p[1] }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN T18 } [get_ports { syzygy_a_d_n[2] }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN R18 } [get_ports { syzygy_a_d_p[2] }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN P18 } [get_ports { syzygy_a_d_n[3] }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN P17 } [get_ports { syzygy_a_d_p[3] }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN R16 } [get_ports { syzygy_a_d_n[4] }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN P16 } [get_ports { syzygy_a_d_p[4] }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN P15 } [get_ports { syzygy_a_d_n[5] }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN N15 } [get_ports { syzygy_a_d_p[5] }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN K18 } [get_ports { syzygy_a_d_n[6] }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN J18 } [get_ports { syzygy_a_d_p[6] }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN K21 } [get_ports { syzygy_a_d_n[7] }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN J20 } [get_ports { syzygy_a_d_p[7] }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN M20 } [get_ports { syzygy_a_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n
|
||||
#set_property -dict { PACKAGE_PIN M19 } [get_ports { syzygy_a_p2c_clk_p }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p
|
||||
#set_property -dict { PACKAGE_PIN L19 } [get_ports { syzygy_a_s[16] }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16]
|
||||
#set_property -dict { PACKAGE_PIN K20 } [get_ports { syzygy_a_s[17] }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17]
|
||||
#set_property -dict { PACKAGE_PIN L18 } [get_ports { syzygy_a_s[18] }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18]
|
||||
#set_property -dict { PACKAGE_PIN K19 } [get_ports { syzygy_a_s[19] }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19]
|
||||
#set_property -dict { PACKAGE_PIN L22 } [get_ports { syzygy_a_s[20] }]; #IO_L10N_T1 Sch=syzygy_a_s[20]
|
||||
#set_property -dict { PACKAGE_PIN J22 } [get_ports { syzygy_a_s[21] }]; #IO_L8N_T1 Sch=syzygy_a_s[21]
|
||||
#set_property -dict { PACKAGE_PIN L21 } [get_ports { syzygy_a_s[22] }]; #IO_L10P_T1 Sch=syzygy_a_s[22]
|
||||
#set_property -dict { PACKAGE_PIN J21 } [get_ports { syzygy_a_s[23] }]; #IO_L8P_T1 Sch=syzygy_a_s[23]
|
||||
#set_property -dict { PACKAGE_PIN N22 } [get_ports { syzygy_a_s[24] }]; #IO_L16P_T2 Sch=syzygy_a_s[24]
|
||||
#set_property -dict { PACKAGE_PIN P22 } [get_ports { syzygy_a_s[25] }]; #IO_L16N_T2 Sch=syzygy_a_s[25]
|
||||
#set_property -dict { PACKAGE_PIN M21 } [get_ports { syzygy_a_s[26] }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26]
|
||||
#set_property -dict { PACKAGE_PIN M22 } [get_ports { syzygy_a_s[27] }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27]
|
||||
|
||||
## Syzygy Port B
|
||||
#set_property -dict { PACKAGE_PIN Y16 } [get_ports { syzygy_b_c2p_clk_n }]; #IO_L14N_T2_SRCC Sch=syzygy_b_c2p_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W16 } [get_ports { syzygy_b_c2p_clk_p }]; #IO_L14P_T2_SRCC Sch=syzygy_b_c2p_clk_p
|
||||
#set_property -dict { PACKAGE_PIN Y15 } [get_ports { syzygy_b_d_n[0] }]; #IO_L21N_T3_DQS Sch=syzygy_b_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN W15 } [get_ports { syzygy_b_d_p[0] }]; #IO_L21P_T3_DQS Sch=syzygy_b_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN W13 } [get_ports { syzygy_b_d_n[1] }]; #IO_L20N_T3 Sch=syzygy_b_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V13 } [get_ports { syzygy_b_d_p[1] }]; #IO_L20P_T3 Sch=syzygy_b_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AA13 } [get_ports { syzygy_b_d_n[2] }]; #IO_L23N_T3 Sch=syzygy_b_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN Y13 } [get_ports { syzygy_b_d_p[2] }]; #IO_L23P_T3 Sch=syzygy_b_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AB15 } [get_ports { syzygy_b_d_n[3] }]; #IO_L24N_T3 Sch=syzygy_b_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AB14 } [get_ports { syzygy_b_d_p[3] }]; #IO_L24P_T3 Sch=syzygy_b_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN AA14 } [get_ports { syzygy_b_d_n[4] }]; #IO_L22N_T3 Sch=syzygy_b_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN Y14 } [get_ports { syzygy_b_d_p[4] }]; #IO_L22P_T3 Sch=syzygy_b_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN V15 } [get_ports { syzygy_b_d_n[5] }]; #IO_L19N_T3_VREF Sch=syzygy_b_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN V14 } [get_ports { syzygy_b_d_p[5] }]; #IO_L19P_T3 Sch=syzygy_b_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN AB22 } [get_ports { syzygy_b_d_n[6] }]; #IO_L7N_T1 Sch=syzygy_b_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN AA22 } [get_ports { syzygy_b_d_p[6] }]; #IO_L7P_T1 Sch=syzygy_b_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN Y21 } [get_ports { syzygy_b_d_n[7] }]; #IO_L9N_T1_DQS Sch=syzygy_b_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN Y20 } [get_ports { syzygy_b_d_p[7] }]; #IO_L9P_T1_DQS Sch=syzygy_b_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN W18 } [get_ports { syzygy_b_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_b_p2c_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W17 } [get_ports { syzygy_b_p2c_clk_p }]; #IO_L13P_T2_MRCC Sch=syzygy_b_p2c_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AA18 } [get_ports { syzygy_b_s[16] }]; #IO_L12N_T1_MRCC Sch=syzygy_b_s[16]
|
||||
#set_property -dict { PACKAGE_PIN AA19 } [get_ports { syzygy_b_s[17] }]; #IO_L11N_T1_SRCC Sch=syzygy_b_s[17]
|
||||
#set_property -dict { PACKAGE_PIN Y18 } [get_ports { syzygy_b_s[18] }]; #IO_L12P_T1_MRCC Sch=syzygy_b_s[18]
|
||||
#set_property -dict { PACKAGE_PIN Y19 } [get_ports { syzygy_b_s[19] }]; #IO_L11P_T1_SRCC Sch=syzygy_b_s[19]
|
||||
#set_property -dict { PACKAGE_PIN AB20 } [get_ports { syzygy_b_s[20] }]; #IO_L10N_T1 Sch=syzygy_b_s[20]
|
||||
#set_property -dict { PACKAGE_PIN AB21 } [get_ports { syzygy_b_s[21] }]; #IO_L8N_T1 Sch=syzygy_b_s[21]
|
||||
#set_property -dict { PACKAGE_PIN AB19 } [get_ports { syzygy_b_s[22] }]; #IO_L10P_T1 Sch=syzygy_b_s[22]
|
||||
#set_property -dict { PACKAGE_PIN AA21 } [get_ports { syzygy_b_s[23] }]; #IO_L8P_T1 Sch=syzygy_b_s[23]
|
||||
#set_property -dict { PACKAGE_PIN U16 } [get_ports { syzygy_b_s[24] }]; #IO_L15N_T2_DQS Sch=syzygy_b_s[24]
|
||||
#set_property -dict { PACKAGE_PIN U15 } [get_ports { syzygy_b_s[25] }]; #IO_L15P_T2_DQS Sch=syzygy_b_s[25]
|
||||
#set_property -dict { PACKAGE_PIN V17 } [get_ports { syzygy_b_s[26] }]; #IO_L16N_T2 Sch=syzygy_b_s[26]
|
||||
#set_property -dict { PACKAGE_PIN U17 } [get_ports { syzygy_b_s[27] }]; #IO_L16P_T2 Sch=syzygy_b_s[27]
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L16P_T2 Sch=crypto_sda
|
||||
|
||||
## Miscellaneous
|
||||
#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[0] }]; #IO_L18N_T2_AD13N Sch=mcu_rsvd[1]
|
||||
#set_property -dict { PACKAGE_PIN B21 IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[1] }]; #IO_L18P_T2_AD13P Sch=mcu_rsvd[2]
|
||||
@@ -0,0 +1,437 @@
|
||||
#### This file is a general .xdc for the Genesys 2 Rev. H
|
||||
#### To use it in a project:
|
||||
#### - uncomment the lines corresponding to used pins
|
||||
#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
|
||||
#set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_0_15 Sch=btnd
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L6P_T0_15 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L24P_T3_17 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_L24N_T3_17 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_0_14 Sch=cpu_resetn
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN U29 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V26 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN W24 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN W23 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7]
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS12 } [get_ports { sw[0] }]; #IO_0_17 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS12 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS12 } [get_ports { sw[2] }]; #IO_L19P_T3_16 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { sw[3] }]; #IO_L6P_T0_17 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { sw[4] }]; #IO_L19P_T3_A22_15 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS12 } [get_ports { sw[5] }]; #IO_25_15 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L10P_T1_D14_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L8P_T1_D11_14 Sch=sw[7]
|
||||
|
||||
## USB HIDs For Both Mouse and Keyboard
|
||||
#set_property -dict { PACKAGE_PIN AD23 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_clk_0 }]; #IO_L12P_T1_MRCC_12 Sch=ps2_clk[0]
|
||||
#set_property -dict { PACKAGE_PIN AE20 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_data_0 }]; #IO_25_12 Sch=ps2_data[0]
|
||||
|
||||
## UART
|
||||
#set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }]; #IO_L1P_T0_12 Sch=uart_rx_out
|
||||
#set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_in }]; #IO_0_12 Sch=uart_tx_in
|
||||
|
||||
## SD Card
|
||||
#set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_d[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_d[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
|
||||
#set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_sclk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
|
||||
|
||||
## Audio Codec
|
||||
#set_property -dict { PACKAGE_PIN AH19 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L8N_T1_32 Sch=aud_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN AD19 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[0] }]; #IO_L10P_T1_32 Sch=aud_adr[0]
|
||||
#set_property -dict { PACKAGE_PIN AG19 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[1] }]; #IO_L8P_T1_32 Sch=aud_adr[1]
|
||||
#set_property -dict { PACKAGE_PIN AG18 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L11N_T1_SRCC_32 Sch=aud_bclk
|
||||
#set_property -dict { PACKAGE_PIN AJ19 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L7P_T1_32 Sch=aud_dac_sdata
|
||||
#set_property -dict { PACKAGE_PIN AJ18 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L9P_T1_DQS_32 Sch=aud_lrclk
|
||||
#set_property -dict { PACKAGE_PIN AK19 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L7N_T1_32 Sch=aud_mclk
|
||||
#set_property -dict { PACKAGE_PIN AE19 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L10N_T1_32 Sch=aud_scl
|
||||
#set_property -dict { PACKAGE_PIN AF18 IOSTANDARD LVCMOS18 } [get_ports { aud_sda }]; #IO_L11P_T1_SRCC_32 Sch=aud_sda
|
||||
|
||||
## Ethernet
|
||||
#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
|
||||
#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { ETH_PHYRST_N }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
|
||||
#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
|
||||
#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS15 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
|
||||
#set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
|
||||
#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
|
||||
#set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
|
||||
#set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
|
||||
#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
|
||||
#set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
|
||||
#set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
|
||||
#set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { ETH_TX_EN }]; #IO_L20P_T3_33 Sch=eth_tx_en
|
||||
|
||||
## VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3]
|
||||
#set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4]
|
||||
#set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5]
|
||||
#set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6]
|
||||
#set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3]
|
||||
#set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4]
|
||||
#set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5]
|
||||
#set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6]
|
||||
#set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3]
|
||||
#set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L18P_T2_12 Sch=vga_r[4]
|
||||
#set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L18N_T2_12 Sch=vga_r[5]
|
||||
#set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L17N_T2_12 Sch=vga_r[6]
|
||||
#set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L19P_T3_12 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN AG23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs
|
||||
|
||||
## HDMI in
|
||||
#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L2P_T0_12 Sch=hdmi_rx_cec
|
||||
#set_property -dict { PACKAGE_PIN AF28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AE28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L14P_T2_SRCC_13 Sch=hdmi_rx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AH29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpa }]; #IO_L13N_T2_MRCC_13 Sch=hdmi_rx_hpa
|
||||
#set_property -dict { PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L17P_T2_13 Sch=hdmi_rx_scl
|
||||
#set_property -dict { PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_13 Sch=hdmi_rx_sda
|
||||
#set_property -dict { PACKAGE_PIN AK26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L24N_T3_13 Sch=hdmi_rx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AJ26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L24P_T3_13 Sch=hdmi_rx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AG28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L21N_T3_DQS_13 Sch=hdmi_rx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AG27 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L21P_T3_DQS_13 Sch=hdmi_rx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AH27 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L22N_T3_13 Sch=hdmi_rx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AH26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L22P_T3_13 Sch=hdmi_rx_p[2]
|
||||
|
||||
## HDMI out
|
||||
#set_property -dict { PACKAGE_PIN Y24 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L1N_T0_12 Sch=hdmi_tx_cec
|
||||
#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L6N_T0_VREF_12 Sch=hdmi_tx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L6P_T0_12 Sch=hdmi_tx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AG29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L13P_T2_MRCC_13 Sch=hdmi_tx_hpd
|
||||
#set_property -dict { PACKAGE_PIN AF27 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L23N_T3_13 Sch=hdmi_tx_scl
|
||||
#set_property -dict { PACKAGE_PIN AF26 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L23P_T3_13 Sch=hdmi_tx_sda
|
||||
#set_property -dict { PACKAGE_PIN AC21 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_12 Sch=hdmi_tx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AC20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_12 Sch=hdmi_tx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AA23 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L4N_T0_12 Sch=hdmi_tx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AA22 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L4P_T0_12 Sch=hdmi_tx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AC25 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L7N_T1_12 Sch=hdmi_tx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AB24 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L7P_T1_12 Sch=hdmi_tx_p[2]
|
||||
|
||||
## OLED Display
|
||||
#set_property -dict { PACKAGE_PIN AC17 IOSTANDARD LVCMOS18 } [get_ports { oled_dc }]; #IO_L18N_T2_32 Sch=oled_dc
|
||||
#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS18 } [get_ports { oled_res }]; #IO_L18P_T2_32 Sch=oled_res
|
||||
#set_property -dict { PACKAGE_PIN AF17 IOSTANDARD LVCMOS18 } [get_ports { oled_sclk }]; #IO_L12P_T1_MRCC_32 Sch=oled_sclk
|
||||
#set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 } [get_ports { oled_sdin }]; #IO_L24N_T3_32 Sch=oled_sdin
|
||||
#set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_L3P_T0_DQS_12 Sch=oled_vbat
|
||||
#set_property -dict { PACKAGE_PIN AG17 IOSTANDARD LVCMOS18 } [get_ports { oled_vdd }]; #IO_L12N_T1_MRCC_32 Sch=oled_vdd
|
||||
|
||||
## PMOD Header JA
|
||||
#set_property -dict { PACKAGE_PIN U27 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L13P_T2_MRCC_14 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN U28 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L13N_T2_MRCC_14 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L12P_T1_MRCC_14 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L12N_T1_MRCC_14 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4]
|
||||
|
||||
## PMOD Header JB
|
||||
#set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L17P_T2_A14_D30_14 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN V30 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L17N_T2_A13_D29_14 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V25 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L18P_T2_A12_D28_14 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN W26 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L18N_T2_A11_D27_14 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN T25 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L14P_T2_SRCC_14 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN U25 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L14N_T2_SRCC_14 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L21P_T3_DQS_14 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN U23 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jb_n[4]
|
||||
|
||||
## PMOD Header JC
|
||||
#set_property -dict { PACKAGE_PIN AC26 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L19P_T3_13 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20P_T3_13 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L18N_T2_13 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN AK29 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15P_T2_DQS_13 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN AD26 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L19N_T3_VREF_13 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN AG30 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L18P_T2_13 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L15N_T2_DQS_13 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN AK28 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20N_T3_13 Sch=jc[10]
|
||||
|
||||
## PMOD Header JD
|
||||
#set_property -dict { PACKAGE_PIN V27 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L16N_T2_A15_D31_14 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN Y30 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L8P_T1_13 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN V24 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L23N_T3_A02_D18_14 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L24N_T3_A00_D16_14 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN U24 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L23P_T3_A03_D19_14 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN Y26 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L1P_T0_13 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L22N_T3_A04_D20_14 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd[10]
|
||||
|
||||
## XADC Header
|
||||
#set_property -dict { PACKAGE_PIN J24 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD0N_15 Sch=xadc0r_n
|
||||
#set_property -dict { PACKAGE_PIN J23 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD0P_15 Sch=xadc0r_p
|
||||
#set_property -dict { PACKAGE_PIN K24 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xadc1r_n
|
||||
#set_property -dict { PACKAGE_PIN K23 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xadc1r_p
|
||||
#set_property -dict { PACKAGE_PIN L23 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xadc8r_n
|
||||
#set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xadc8r_p
|
||||
#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L4N_T0_AD9N_15 Sch=xadc9r_n
|
||||
#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L4P_T0_AD9P_15 Sch=xadc9r_p
|
||||
|
||||
## FMC
|
||||
#set_property -dict { PACKAGE_PIN AB30 IOSTANDARD LVCMOS33 } [get_ports { FMC_CLK_DIR }]; #IO_L10N_T1_13 Sch=fmc_clk_dir
|
||||
#set_property -dict { PACKAGE_PIN E20 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_17 Sch=fmc_clk0_m2c_n
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_17 Sch=fmc_clk0_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN D28 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_n }]; #IO_L14N_T2_SRCC_16 Sch=fmc_clk1_m2c_n
|
||||
#set_property -dict { PACKAGE_PIN E28 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_p }]; #IO_L14P_T2_SRCC_16 Sch=fmc_clk1_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN K25 IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_N[2] }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=fmc_clk_n[2]
|
||||
#set_property -dict { PACKAGE_PIN L25 IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_P[2] }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=fmc_clk_p[2]
|
||||
#set_property -dict { PACKAGE_PIN K29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[00] }]; #IO_L13N_T2_MRCC_15 Sch=fmc_ha_n[00]
|
||||
#set_property -dict { PACKAGE_PIN K28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[00] }]; #IO_L13P_T2_MRCC_15 Sch=fmc_ha_p[00]
|
||||
#set_property -dict { PACKAGE_PIN L28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[01] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_ha_n[01]
|
||||
#set_property -dict { PACKAGE_PIN M28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[01] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_ha_p[01]
|
||||
#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[02] }]; #IO_L22N_T3_A16_15 Sch=fmc_ha_n[02]
|
||||
#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[02] }]; #IO_L22P_T3_A17_15 Sch=fmc_ha_p[02]
|
||||
#set_property -dict { PACKAGE_PIN N26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[03] }]; #IO_L18N_T2_A23_15 Sch=fmc_ha_n[03]
|
||||
#set_property -dict { PACKAGE_PIN N25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[03] }]; #IO_L18P_T2_A24_15 Sch=fmc_ha_p[03]
|
||||
#set_property -dict { PACKAGE_PIN M25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[04] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_ha_n[04]
|
||||
#set_property -dict { PACKAGE_PIN M24 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[04] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_ha_p[04]
|
||||
#set_property -dict { PACKAGE_PIN H29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[05] }]; #IO_L7N_T1_AD10N_15 Sch=fmc_ha_n[05]
|
||||
#set_property -dict { PACKAGE_PIN J29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[05] }]; #IO_L7P_T1_AD10P_15 Sch=fmc_ha_p[05]
|
||||
#set_property -dict { PACKAGE_PIN N30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[06] }]; #IO_L17N_T2_A25_15 Sch=fmc_ha_n[06]
|
||||
#set_property -dict { PACKAGE_PIN N29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[06] }]; #IO_L17P_T2_A26_15 Sch=fmc_ha_p[06]
|
||||
#set_property -dict { PACKAGE_PIN M30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[07] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_ha_n[07]
|
||||
#set_property -dict { PACKAGE_PIN M29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[07] }]; #IO_L15P_T2_DQS_15 Sch=fmc_ha_p[07]
|
||||
#set_property -dict { PACKAGE_PIN J28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[08] }]; #IO_L8N_T1_AD3N_15 Sch=fmc_ha_n[08]
|
||||
#set_property -dict { PACKAGE_PIN J27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[08] }]; #IO_L8P_T1_AD3P_15 Sch=fmc_ha_p[08]
|
||||
#set_property -dict { PACKAGE_PIN K30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[09] }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fmc_ha_n[09]
|
||||
#set_property -dict { PACKAGE_PIN L30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[09] }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fmc_ha_p[09]
|
||||
#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[10] }]; #IO_L20N_T3_A19_15 Sch=fmc_ha_n[10]
|
||||
#set_property -dict { PACKAGE_PIN N21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[10] }]; #IO_L20P_T3_A20_15 Sch=fmc_ha_p[10]
|
||||
#set_property -dict { PACKAGE_PIN N24 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[11] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_ha_n[11]
|
||||
#set_property -dict { PACKAGE_PIN P23 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[11] }]; #IO_L21P_T3_DQS_15 Sch=fmc_ha_p[11]
|
||||
#set_property -dict { PACKAGE_PIN L27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[12] }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=fmc_ha_n[12]
|
||||
#set_property -dict { PACKAGE_PIN L26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[12] }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=fmc_ha_p[12]
|
||||
#set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[13] }]; #IO_L10N_T1_AD4N_15 Sch=fmc_ha_n[13]
|
||||
#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[13] }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13]
|
||||
#set_property -dict { PACKAGE_PIN M27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[14] }]; #IO_L16N_T2_A27_15 Sch=fmc_ha_n[14]
|
||||
#set_property -dict { PACKAGE_PIN N27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[14] }]; #IO_L16P_T2_A28_15 Sch=fmc_ha_p[14]
|
||||
#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[15] }]; #IO_L5N_T0_AD2N_15 Sch=fmc_ha_n[15]
|
||||
#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[15] }]; #IO_L5P_T0_AD2P_15 Sch=fmc_ha_p[15]
|
||||
#set_property -dict { PACKAGE_PIN M23 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[16] }]; #IO_L24N_T3_RS0_15 Sch=fmc_ha_n[16]
|
||||
#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[16] }]; #IO_L24P_T3_RS1_15 Sch=fmc_ha_p[16]
|
||||
#set_property -dict { PACKAGE_PIN B25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[17] }]; #IO_L12N_T1_MRCC_16 Sch=fmc_ha_n[17]
|
||||
#set_property -dict { PACKAGE_PIN C25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[17] }]; #IO_L12P_T1_MRCC_16 Sch=fmc_ha_p[17]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[18] }]; #IO_L14N_T2_SRCC_17 Sch=fmc_ha_n[18]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[18] }]; #IO_L14P_T2_SRCC_17 Sch=fmc_ha_p[18]
|
||||
#set_property -dict { PACKAGE_PIN F30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[19] }]; #IO_L22N_T3_16 Sch=fmc_ha_n[19]
|
||||
#set_property -dict { PACKAGE_PIN G29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[19] }]; #IO_L22P_T3_16 Sch=fmc_ha_p[19]
|
||||
#set_property -dict { PACKAGE_PIN F27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[20] }]; #IO_L21N_T3_DQS_16 Sch=fmc_ha_n[20]
|
||||
#set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[20] }]; #IO_L21P_T3_DQS_16 Sch=fmc_ha_p[20]
|
||||
#set_property -dict { PACKAGE_PIN F28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[21] }]; #IO_L20N_T3_16 Sch=fmc_ha_n[21]
|
||||
#set_property -dict { PACKAGE_PIN G28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[21] }]; #IO_L20P_T3_16 Sch=fmc_ha_p[21]
|
||||
#set_property -dict { PACKAGE_PIN C21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[22] }]; #IO_L8N_T1_17 Sch=fmc_ha_n[22]
|
||||
#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[22] }]; #IO_L8P_T1_17 Sch=fmc_ha_p[22]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[23] }]; #IO_L16N_T2_17 Sch=fmc_ha_n[23]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[23] }]; #IO_L16P_T2_17 Sch=fmc_ha_p[23]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[00] }]; #IO_L12N_T1_MRCC_18 Sch=fmc_hb_n[00]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[00] }]; #IO_L12P_T1_MRCC_18 Sch=fmc_hb_p[00]
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[01] }]; #IO_L7N_T1_18 Sch=fmc_hb_n[01]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[01] }]; #IO_L7P_T1_18 Sch=fmc_hb_p[01]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[02] }]; #IO_L2N_T0_18 Sch=fmc_hb_n[02]
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[02] }]; #IO_L2P_T0_18 Sch=fmc_hb_p[02]
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[03] }]; #IO_L11N_T1_SRCC_18 Sch=fmc_hb_n[03]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[03] }]; #IO_L11P_T1_SRCC_18 Sch=fmc_hb_p[03]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[04] }]; #IO_L9N_T1_DQS_18 Sch=fmc_hb_n[04]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[04] }]; #IO_L9P_T1_DQS_18 Sch=fmc_hb_p[04]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[05] }]; #IO_L1N_T0_18 Sch=fmc_hb_n[05]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[05] }]; #IO_L1P_T0_18 Sch=fmc_hb_p[05]
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[06] }]; #IO_L14N_T2_SRCC_18 Sch=fmc_hb_n[06]
|
||||
#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[06] }]; #IO_L14P_T2_SRCC_18 Sch=fmc_hb_p[06]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[07] }]; #IO_L22N_T3_18 Sch=fmc_hb_n[07]
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[07] }]; #IO_L22P_T3_18 Sch=fmc_hb_p[07]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[08] }]; #IO_L5N_T0_18 Sch=fmc_hb_n[08]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[08] }]; #IO_L5P_T0_18 Sch=fmc_hb_p[08]
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[09] }]; #IO_L23N_T3_18 Sch=fmc_hb_n[09]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[09] }]; #IO_L23P_T3_18 Sch=fmc_hb_p[09]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[10] }]; #IO_L8N_T1_18 Sch=fmc_hb_n[10]
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[10] }]; #IO_L8P_T1_18 Sch=fmc_hb_p[10]
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[11] }]; #IO_L18N_T2_18 Sch=fmc_hb_n[11]
|
||||
#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[11] }]; #IO_L18P_T2_18 Sch=fmc_hb_p[11]
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[12] }]; #IO_L17N_T2_18 Sch=fmc_hb_n[12]
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[12] }]; #IO_L17P_T2_18 Sch=fmc_hb_p[12]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[13] }]; #IO_L15N_T2_DQS_18 Sch=fmc_hb_n[13]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[13] }]; #IO_L15P_T2_DQS_18 Sch=fmc_hb_p[13]
|
||||
#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[14] }]; #IO_L10N_T1_18 Sch=fmc_hb_n[14]
|
||||
#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[14] }]; #IO_L10P_T1_18 Sch=fmc_hb_p[14]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[15] }]; #IO_L3N_T0_DQS_18 Sch=fmc_hb_n[15]
|
||||
#set_property -dict { PACKAGE_PIN L12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[15] }]; #IO_L3P_T0_DQS_18 Sch=fmc_hb_p[15]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[16] }]; #IO_L4N_T0_18 Sch=fmc_hb_n[16]
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[16] }]; #IO_L4P_T0_18 Sch=fmc_hb_p[16]
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[17] }]; #IO_L13N_T2_MRCC_18 Sch=fmc_hb_n[17]
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[17] }]; #IO_L13P_T2_MRCC_18 Sch=fmc_hb_p[17]
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[18] }]; #IO_L20N_T3_18 Sch=fmc_hb_n[18]
|
||||
#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[18] }]; #IO_L20P_T3_18 Sch=fmc_hb_p[18]
|
||||
#set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[19] }]; #IO_L16N_T2_18 Sch=fmc_hb_n[19]
|
||||
#set_property -dict { PACKAGE_PIN F11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[19] }]; #IO_L16P_T2_18 Sch=fmc_hb_p[19]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[20] }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20]
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[20] }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[21] }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[21] }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21]
|
||||
#set_property -dict { PACKAGE_PIN C27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[00] }]; #IO_L13N_T2_MRCC_16 Sch=fmc_la_n[00]
|
||||
#set_property -dict { PACKAGE_PIN D27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[00] }]; #IO_L13P_T2_MRCC_16 Sch=fmc_la_p[00]
|
||||
#set_property -dict { PACKAGE_PIN C26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[01] }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la_n[01]
|
||||
#set_property -dict { PACKAGE_PIN D26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[01] }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la_p[01]
|
||||
#set_property -dict { PACKAGE_PIN G30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[02] }]; #IO_L24N_T3_16 Sch=fmc_la_n[02]
|
||||
#set_property -dict { PACKAGE_PIN H30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[02] }]; #IO_L24P_T3_16 Sch=fmc_la_p[02]
|
||||
#set_property -dict { PACKAGE_PIN E30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[03] }]; #IO_L18N_T2_16 Sch=fmc_la_n[03]
|
||||
#set_property -dict { PACKAGE_PIN E29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[03] }]; #IO_L18P_T2_16 Sch=fmc_la_p[03]
|
||||
#set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[04] }]; #IO_L23N_T3_16 Sch=fmc_la_n[04]
|
||||
#set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[04] }]; #IO_L23P_T3_16 Sch=fmc_la_p[04]
|
||||
#set_property -dict { PACKAGE_PIN A30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[05] }]; #IO_L17N_T2_16 Sch=fmc_la_n[05]
|
||||
#set_property -dict { PACKAGE_PIN B30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[05] }]; #IO_L17P_T2_16 Sch=fmc_la_p[05]
|
||||
#set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[06] }]; #IO_L16N_T2_16 Sch=fmc_la_n[06]
|
||||
#set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[06] }]; #IO_L16P_T2_16 Sch=fmc_la_p[06]
|
||||
#set_property -dict { PACKAGE_PIN E25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[07] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[07]
|
||||
#set_property -dict { PACKAGE_PIN F25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[07] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[07]
|
||||
#set_property -dict { PACKAGE_PIN B29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[08] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[08]
|
||||
#set_property -dict { PACKAGE_PIN C29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[08] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[08]
|
||||
#set_property -dict { PACKAGE_PIN A28 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[09] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[09]
|
||||
#set_property -dict { PACKAGE_PIN B28 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[09] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[09]
|
||||
#set_property -dict { PACKAGE_PIN A27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[10] }]; #IO_L7N_T1_16 Sch=fmc_la_n[10]
|
||||
#set_property -dict { PACKAGE_PIN B27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[10] }]; #IO_L7P_T1_16 Sch=fmc_la_p[10]
|
||||
#set_property -dict { PACKAGE_PIN A26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[11] }]; #IO_L10N_T1_16 Sch=fmc_la_n[11]
|
||||
#set_property -dict { PACKAGE_PIN A25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[11] }]; #IO_L10P_T1_16 Sch=fmc_la_p[11]
|
||||
#set_property -dict { PACKAGE_PIN E26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[12] }]; #IO_L5N_T0_16 Sch=fmc_la_n[12]
|
||||
#set_property -dict { PACKAGE_PIN F26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[12] }]; #IO_L5P_T0_16 Sch=fmc_la_p[12]
|
||||
#set_property -dict { PACKAGE_PIN D24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[13] }]; #IO_L4N_T0_16 Sch=fmc_la_n[13]
|
||||
#set_property -dict { PACKAGE_PIN E24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[13] }]; #IO_L4P_T0_16 Sch=fmc_la_p[13]
|
||||
#set_property -dict { PACKAGE_PIN B24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[14] }]; #IO_L8N_T1_16 Sch=fmc_la_n[14]
|
||||
#set_property -dict { PACKAGE_PIN C24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[14] }]; #IO_L8P_T1_16 Sch=fmc_la_p[14]
|
||||
#set_property -dict { PACKAGE_PIN A23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[15] }]; #IO_L1N_T0_16 Sch=fmc_la_n[15]
|
||||
#set_property -dict { PACKAGE_PIN B23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[15] }]; #IO_L1P_T0_16 Sch=fmc_la_p[15]
|
||||
#set_property -dict { PACKAGE_PIN D23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[16] }]; #IO_L2N_T0_16 Sch=fmc_la_n[16]
|
||||
#set_property -dict { PACKAGE_PIN E23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[16] }]; #IO_L2P_T0_16 Sch=fmc_la_p[16]
|
||||
#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[17] }]; #IO_L11N_T1_SRCC_17 Sch=fmc_la_n[17]
|
||||
#set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[17] }]; #IO_L11P_T1_SRCC_17 Sch=fmc_la_p[17]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[18] }]; #IO_L13N_T2_MRCC_17 Sch=fmc_la_n[18]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[18] }]; #IO_L13P_T2_MRCC_17 Sch=fmc_la_p[18]
|
||||
#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[19] }]; #IO_L7N_T1_17 Sch=fmc_la_n[19]
|
||||
#set_property -dict { PACKAGE_PIN H21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[19] }]; #IO_L7P_T1_17 Sch=fmc_la_p[19]
|
||||
#set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[20] }]; #IO_L9N_T1_DQS_17 Sch=fmc_la_n[20]
|
||||
#set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[20] }]; #IO_L9P_T1_DQS_17 Sch=fmc_la_p[20]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[21] }]; #IO_L5N_T0_17 Sch=fmc_la_n[21]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[21] }]; #IO_L5P_T0_17 Sch=fmc_la_p[21]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0_DQS_17 Sch=fmc_la_n[22]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0_DQS_17 Sch=fmc_la_p[22]
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[23] }]; #IO_L18N_T2_17 Sch=fmc_la_n[23]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[23] }]; #IO_L18P_T2_17 Sch=fmc_la_p[23]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[24] }]; #IO_L2N_T0_17 Sch=fmc_la_n[24]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[24] }]; #IO_L2P_T0_17 Sch=fmc_la_p[24]
|
||||
#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[25] }]; #IO_L10N_T1_17 Sch=fmc_la_n[25]
|
||||
#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[25] }]; #IO_L10P_T1_17 Sch=fmc_la_p[25]
|
||||
#set_property -dict { PACKAGE_PIN A22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[26] }]; #IO_L23N_T3_17 Sch=fmc_la_n[26]
|
||||
#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[26] }]; #IO_L23P_T3_17 Sch=fmc_la_p[26]
|
||||
#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[27] }]; #IO_L21N_T3_DQS_17 Sch=fmc_la_n[27]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[27] }]; #IO_L21P_T3_DQS_17 Sch=fmc_la_p[27]
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[28] }]; #IO_L4N_T0_17 Sch=fmc_la_n[28]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[28] }]; #IO_L4P_T0_17 Sch=fmc_la_p[28]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[29] }]; #IO_L22N_T3_17 Sch=fmc_la_n[29]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[29] }]; #IO_L22P_T3_17 Sch=fmc_la_p[29]
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[30] }]; #IO_L20N_T3_17 Sch=fmc_la_n[30]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[30] }]; #IO_L20P_T3_17 Sch=fmc_la_p[30]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[31] }]; #IO_L17N_T2_17 Sch=fmc_la_n[31]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[31] }]; #IO_L17P_T2_17 Sch=fmc_la_p[31]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[32] }]; #IO_L1N_T0_17 Sch=fmc_la_n[32]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[32] }]; #IO_L1P_T0_17 Sch=fmc_la_p[32]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[33] }]; #IO_L15N_T2_DQS_17 Sch=fmc_la_n[33]
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[33] }]; #IO_L15P_T2_DQS_17 Sch=fmc_la_p[33]
|
||||
#set_property -dict { PACKAGE_PIN AC24 IOSTANDARD LVCMOS33 } [get_ports { FMC_SCL }]; #IO_L9P_T1_DQS_12 Sch=fmc_scl
|
||||
#set_property -dict { PACKAGE_PIN AD24 IOSTANDARD LVCMOS33 } [get_ports { FMC_SDA }]; #IO_L9N_T1_DQS_12 Sch=fmc_sda
|
||||
|
||||
## Fan Control
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { FAN_PWM }]; #IO_25_14 Sch=fan_pwm
|
||||
#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tach
|
||||
|
||||
## DPTI
|
||||
## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins.
|
||||
#set_property -dict { PACKAGE_PIN AB27 IOSTANDARD LVCMOS33 } [get_ports { PROG_CLKO }]; #IO_L12P_T1_MRCC_13 Sch=prog_clko
|
||||
#set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[0] }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck
|
||||
#set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[1] }]; #IO_L2P_T0_13 Sch=prog_d1/mosi
|
||||
#set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[2] }]; #IO_L2N_T0_13 Sch=prog_d2/miso
|
||||
#set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[3] }]; #IO_L4P_T0_13 Sch=prog_d3/ss
|
||||
#set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[4] }]; #IO_L4N_T0_13 Sch=prog_d[4]
|
||||
#set_property -dict { PACKAGE_PIN Y28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[5] }]; #IO_L3P_T0_DQS_13 Sch=prog_d[5]
|
||||
#set_property -dict { PACKAGE_PIN AA28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[6] }]; #IO_L3N_T0_DQS_13 Sch=prog_d[6]
|
||||
#set_property -dict { PACKAGE_PIN AA26 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[7] }]; #IO_L1N_T0_13 Sch=prog_d[7]
|
||||
#set_property -dict { PACKAGE_PIN AC30 IOSTANDARD LVCMOS33 } [get_ports { PROG_OEN }]; #IO_L7N_T1_13 Sch=prog_oen
|
||||
#set_property -dict { PACKAGE_PIN AB25 IOSTANDARD LVCMOS33 } [get_ports { PROG_RDN }]; #IO_L6N_T0_VREF_13 Sch=prog_rdn
|
||||
#set_property -dict { PACKAGE_PIN AB29 IOSTANDARD LVCMOS33 } [get_ports { PROG_RXFN }]; #IO_L10P_T1_13 Sch=prog_rxfn
|
||||
#set_property -dict { PACKAGE_PIN AB28 IOSTANDARD LVCMOS33 } [get_ports { PROG_SIWUN }]; #IO_L5N_T0_13 Sch=prog_siwun
|
||||
#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien
|
||||
#set_property -dict { PACKAGE_PIN AA25 IOSTANDARD LVCMOS33 } [get_ports { PROG_TXEN }]; #IO_L6P_T0_13 Sch=prog_txen
|
||||
#set_property -dict { PACKAGE_PIN AC27 IOSTANDARD LVCMOS33 } [get_ports { PROG_WRN }]; #IO_L12N_T1_MRCC_13 Sch=prog_wrn
|
||||
|
||||
## DSPI
|
||||
## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins.
|
||||
#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien
|
||||
#set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { PROG_SCK }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck
|
||||
#set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { PROG_MOSI }]; #IO_L2P_T0_13 Sch=prog_d1/mosi
|
||||
#set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { PROG_MISO }]; #IO_L2N_T0_13 Sch=prog_d2/miso
|
||||
#set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SS }]; #IO_L4P_T0_13 Sch=prog_d3/ss
|
||||
|
||||
## QSPI
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
#set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0]
|
||||
#set_property -dict { PACKAGE_PIN R25 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1]
|
||||
#set_property -dict { PACKAGE_PIN R20 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2]
|
||||
#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3]
|
||||
|
||||
## IIC Bus
|
||||
#set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { SYS_SCL }]; #IO_L16P_T2_13 Sch=sys_scl
|
||||
#set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { SYS_SDA }]; #IO_L16N_T2_13 Sch=sys_sda
|
||||
|
||||
## Display Port IN
|
||||
#set_property -dict { PACKAGE_PIN AC19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_N }]; #IO_L17N_T2_32 Sch=rx_aux_ch_n
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_N }]; #IO_L15N_T2_DQS_32 Sch=rx_aux_ch_n
|
||||
#set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_P }]; #IO_L17P_T2_32 Sch=rx_aux_ch_p
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_P }]; #IO_L15P_T2_DQS_32 Sch=rx_aux_ch_p
|
||||
#set_property -dict { PACKAGE_PIN AE21 IOSTANDARD LVCMOS33 } [get_ports { RX_HPD }]; #IO_L10N_T1_12 Sch=rx_hpd
|
||||
|
||||
## Display Port OUT
|
||||
#set_property -dict { PACKAGE_PIN AD16 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_N }]; #IO_L14N_T2_SRCC_32 Sch=tx_aux_ch_n
|
||||
#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_N }]; #IO_L16N_T2_32 Sch=tx_aux_ch_n
|
||||
#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_P }]; #IO_L16P_T2_32 Sch=tx_aux_ch_p
|
||||
#set_property -dict { PACKAGE_PIN AD17 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_P }]; #IO_L14P_T2_SRCC_32 Sch=tx_aux_ch_p
|
||||
#set_property -dict { PACKAGE_PIN AD21 IOSTANDARD LVCMOS33 } [get_ports { TX_HPD }]; #IO_L10P_T1_12 Sch=tx_hpd
|
||||
|
||||
## USB
|
||||
#set_property -dict { PACKAGE_PIN AD18 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_CLK }]; #IO_L13P_T2_MRCC_32 Sch=usb_otg_clk
|
||||
#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[0] }]; #IO_L19N_T3_VREF_32 Sch=usb_otg_d[0]
|
||||
#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[1] }]; #IO_L19P_T3_32 Sch=usb_otg_d[1]
|
||||
#set_property -dict { PACKAGE_PIN AC15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[2] }]; #IO_L21N_T3_DQS_32 Sch=usb_otg_d[2]
|
||||
#set_property -dict { PACKAGE_PIN AC16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[3] }]; #IO_L21P_T3_DQS_32 Sch=usb_otg_d[3]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[4] }]; #IO_L20N_T3_32 Sch=usb_otg_d[4]
|
||||
#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[5] }]; #IO_L20P_T3_32 Sch=usb_otg_d[5]
|
||||
#set_property -dict { PACKAGE_PIN AD14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[6] }]; #IO_L22N_T3_32 Sch=usb_otg_d[6]
|
||||
#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[7] }]; #IO_L22P_T3_32 Sch=usb_otg_d[7]
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_DIR }]; #IO_L24P_T3_32 Sch=usb_otg_dir
|
||||
#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_NXT }]; #IO_L23N_T3_32 Sch=usb_otg_nxt
|
||||
#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_RESETB }]; #IO_25_VRP_32 Sch=usb_otg_resetb
|
||||
#set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_STP }]; #IO_L23P_T3_32 Sch=usb_otg_stp
|
||||
#set_property -dict { PACKAGE_PIN AF16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_VBUSOC }]; #IO_L6N_T0_VREF_32 Sch=usb_otg_vbusoc
|
||||
|
||||
@@ -0,0 +1,272 @@
|
||||
#### This file is a general .xdc for the Genesys ZU-3EG Rev. D
|
||||
#### To use it in a project:
|
||||
#### - uncomment the lines corresponding to used pins
|
||||
#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
#set_property DCI_CASCADE {64} [get_iobanks 65]
|
||||
|
||||
## Crypto
|
||||
#set_property -dict { PACKAGE_PIN AD15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L5P_HDGC_44/24 Sch=crypto_sda
|
||||
|
||||
# Sysclk is a 125 MHz PL reference clock generated by the external Ethernet PHY
|
||||
# It connects to an HDGC pin, so it has direct connection only to BUFG primitives.
|
||||
# When using it as input clock to CMT primitives (MMCM/PLL), it needs to go through
|
||||
# BUFG first. Choose "Global Buffer" in Clocking Wizard IP customization.
|
||||
# Might need CLOCK_DEDICATED_ROUTE FALSE
|
||||
#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS18 } [get_ports { sysclk }];
|
||||
|
||||
## MIPI A Port
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS12 } [get_ports { mipi_a_pwup_ls }]; #IO_L22N_T3U_N7_DBC_AD0N_66 Sch=mipi_a_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN G1 [get_ports mipi_a_clk_p] #IO_L1P_T0L_N0_DBC_66 Sch=mipi_a_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_n]
|
||||
##set_property PACKAGE_PIN E1 [get_ports mipi_a_lane_p[0]] #IO_L2P_T0L_N2_66 Sch=mipi_a_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[0]]
|
||||
##set_property PACKAGE_PIN F2 [get_ports mipi_a_lane_p[1]] #IO_L3P_T0L_N4_AD15P_66 Sch=mipi_a_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[1]]]
|
||||
|
||||
## MIPI B Port
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS12 } [get_ports { mipi_b_pwup_ls }]; #IO_L23P_T3U_N8_66 Sch=mipi_b_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN B5 [get_ports mipi_b_clk_p] #IO_L19P_T3L_N0_DBC_AD9P_66 Sch=mipi_b_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_n]
|
||||
##set_property PACKAGE_PIN C6 [get_ports mipi_b_lane_p[0]] #IO_L20P_T3L_N2_AD1P_66 Sch=mipi_b_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[0]]
|
||||
##set_property PACKAGE_PIN A7 [get_ports mipi_b_lane_p[1]] #IO_L21P_T3L_N4_AD8P_66 Sch=mipi_b_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[1]]
|
||||
|
||||
## Audio CODEC I2S, I2C
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L11N_AD9N_45/25 Sch=aud_scl
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS18 } [get_ports { aud_sda_io }]; #IO_L12P_AD8P_45/25 Sch=aud_sda
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_AD10N_45/25 Sch=aud_lrclk
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L12N_AD8N_45/25 Sch=aud_bclk
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L9P_AD11P_45/25 Sch=aud_mclk
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L10P_AD10P_45/25 Sch=aud_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L8N_HDGC_45/25 Sch=aud_dac_sdata
|
||||
|
||||
## PMOD XADC
|
||||
## Commented because pins are contrained by System Management Wizard. Only >2018.2 lets us select bank 43.
|
||||
#set_property -dict { PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_n }]; #IO_L10N_AD2N_43/44 Sch=ja1_r_n
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_p }]; #IO_L10P_AD2P_43/44 Sch=ja1_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_n }]; #IO_L9N_AD3N_43/44 Sch=ja2_r_n
|
||||
#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_p }]; #IO_L9P_AD3P_43/44 Sch=ja2_r_p
|
||||
#set_property -dict { PACKAGE_PIN AB9 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_n }]; #IO_L12N_AD0N_43/44 Sch=ja3_r_n
|
||||
#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_p }]; #IO_L12P_AD0P_43/44 Sch=ja3_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_n }]; #IO_L11N_AD1N_43/44 Sch=ja4_r_n
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_p }]; #IO_L11P_AD1P_43/44 Sch=ja4_r_p
|
||||
|
||||
## Platform MCU signals
|
||||
#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[0] }]; #IO_L6P_HDGC_44/24 Sch=vadj_level[0]
|
||||
#set_property -dict { PACKAGE_PIN AC13 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[1] }]; #IO_L6N_HDGC_44/24 Sch=vadj_level[1]
|
||||
#set_property -dict { PACKAGE_PIN G10 IOSTANDARD LVCMOS18 } [get_ports { vadj_auton }]; #IO_L3N_AD13N_45/25 Sch=vadj_auton
|
||||
#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_detectedn }]; #IO_L3P_AD13P_45/25 Sch=syzygy_detectedn
|
||||
|
||||
##DisplayPort AUX channel over EMIO
|
||||
#set_property -dict { PACKAGE_PIN K12 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_din }]; #IO_L2N_AD14N_45/25 Sch=dp_aux_din
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_doe }]; #IO_L2P_AD14P_45/25 Sch=dp_aux_doe
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_dout }]; #IO_L1P_AD15P_45/25 Sch=dp_aux_dout
|
||||
#set_property -dict { PACKAGE_PIN J10 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_hotplug_detect }]; #IO_L1N_AD15N_45/25 Sch=dp_aux_hotplug_detect
|
||||
|
||||
## Mini PCIe Auxiliary
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { pcie_w_disable2n }]; #IO_L12P_AD8P_44/24 Sch=pcie_w_disable2n
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS12 } [get_ports { pcie_w_disable[1] }]; #IO_L9P_T1L_N4_AD12P_66 Sch=pcie_w_disable[1]
|
||||
|
||||
## USB 2.0 Overcurrent EMIO
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS12 PULLUP true } [get_ports { usb20_ocn }];#IO_L18N_T2U_N11_AD2N_66 Sch=usb20_ocn
|
||||
|
||||
## Ethernet JTAG
|
||||
#set_property -dict { PACKAGE_PIN F7 LVCMOS12 } [get_ports { eth_tms_ls }]; #IO_L16N_T2U_N7_QBC_AD3N_66 Sch=eth_tms_ls
|
||||
#set_property -dict { PACKAGE_PIN F8 LVCMOS12 } [get_ports { eth_tdi_ls }]; #IO_L17P_T2U_N8_AD10P_66 Sch=eth_tdi_ls
|
||||
#set_property -dict { PACKAGE_PIN E8 LVCMOS12 } [get_ports { eth_tck_ls }]; #IO_L17N_T2U_N9_AD10N_66 Sch=eth_tck_ls
|
||||
#set_property -dict { PACKAGE_PIN E9 LVCMOS12 } [get_ports { eth_tdo_ls }]; #IO_L18P_T2U_N10_AD2P_66 Sch=eth_tdo_ls
|
||||
|
||||
## PMOD JB
|
||||
#set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8N_HDGC_AD4N_46/26 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN AG14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L2N_AD10N_46/26 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_AD11P_46/26 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN AG13 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L8P_HDGC_AD4P_46/26 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6P_HDGC_AD6P_46/26 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN AF13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L2P_AD10P_46/26 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L5P_HDGC_AD7P_46/26 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN AH13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L1N_AD11N_46/26 Sch=jb[10]
|
||||
|
||||
## PMOD JC
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L6N_HDGC_AD6N_46/26 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L7P_HDGC_AD5P_46/26 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L3P_AD9P_46/26 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L5N_HDGC_AD7N_46/26 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L7N_HDGC_AD5N_46/26 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L4N_AD8N_46/26 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L4P_AD8P_46/26 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L3N_AD9N_46/26 Sch=jc[10]
|
||||
|
||||
## PMOD JD
|
||||
#set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L4P_AD12P_44/24 Sch=jd[1]
|
||||
#set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L2P_AD14P_44/24 Sch=jd[2]
|
||||
#set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L2N_AD14N_44/24 Sch=jd[3]
|
||||
#set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L3P_AD13P_44/24 Sch=jd[4]
|
||||
#set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L1N_AD15N_44/24 Sch=jd[7]
|
||||
#set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L4N_AD12N_44/24 Sch=jd[8]
|
||||
#set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L1P_AD15P_44/24 Sch=jd[9]
|
||||
#set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L3N_AD13N_44/24 Sch=jd[10]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN B10 IOSTANDARD LVCMOS18 } [get_ports { btn[2] }]; #IO_L9N_AD11N_45/25 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports { btn[3] }]; #IO_L4N_AD12N_45/25 Sch=btn[3]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS18 } [get_ports { btn[4] }]; #IO_L4P_AD12P_45/25 Sch=btn[4]
|
||||
#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS18 } [get_ports { btn[5] }]; #IO_L6P_HDGC_45/25 Sch=btn[5]
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS18 } [get_ports { btn[6] }]; #IO_L11P_AD9P_45/25 Sch=btn[6]
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L8N_HDGC_44/24 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L10N_AD10N_44/24 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L11P_AD9P_44/24 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L8P_HDGC_44/24 Sch=sw[3]
|
||||
|
||||
## LED
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ld[0] }]; #IO_L12P_AD0P_46/26 Sch=ld[1]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { ld[1] }]; #IO_L12N_AD0N_46/26 Sch=ld[2]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ld[2] }]; #IO_L11P_AD1P_46/26 Sch=ld[3]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ld[3] }]; #IO_L11N_AD1N_46/26 Sch=ld[4]
|
||||
|
||||
## RGB LED
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS12 } [get_ports { ld5_b }]; #IO_L23N_T3U_N9_66 Sch=ld5_b
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS12 } [get_ports { ld5_g }]; #IO_L24N_T3U_N11_66 Sch=ld5_g
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS12 } [get_ports { ld5_r }]; #IO_L24P_T3U_N10_66 Sch=ld5_r
|
||||
|
||||
## GTH reference clock jitter filter auxiliary
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS12 } [get_ports { clkgth_intrn_ls }]; #IO_L11N_T1U_N9_GC_66 Sch=clkgth_intrn_ls
|
||||
#set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS12 } [get_ports { clkgth_loln_ls }]; #IO_L13N_T2L_N1_GC_QBC_66 Sch=clkgth_loln_ls
|
||||
#set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS12 } [get_ports { clkgth_rst }]; #IO_L16P_T2U_N6_QBC_AD3P_66 Sch=clkgth_rst
|
||||
|
||||
## MUX I2C
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS12 } [get_ports { fpga_mux_rst }]; #IO_L15N_T2L_N5_AD11N_66 Sch=fpga_mux_rst
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_scl_ls }]; #IO_L9P_AD3P_46/26 Sch=mux_scl_ls
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_sda_ls }]; #IO_L9N_AD3N_46/26 Sch=mux_sda_ls
|
||||
|
||||
## SYZYGY
|
||||
#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[0] }]; #IO_L18P_T2U_N10_AD2P_64 Sch=syzygy_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AE2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[1] }]; #IO_L22P_T3U_N6_DBC_AD0P_64 Sch=syzygy_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AE3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[2] }]; #IO_L21P_T3L_N4_AD8P_64 Sch=syzygy_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AE5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[3] }]; #IO_L12P_T1U_N10_GC_64 Sch=syzygy_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN AD7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[4] }]; #IO_L4P_T0U_N6_DBC_AD7P_64 Sch=syzygy_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN AG6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[5] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=syzygy_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[6] }]; #IO_L3P_T0L_N4_AD15P_65 Sch=syzygy_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[7] }]; #IO_L2P_T0L_N2_65 Sch=syzygy_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN AC1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[0] }]; #IO_L18P_T2U_N11_AD2P_64 Sch=syzygy_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AF2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[1] }]; #IO_L22P_T3U_N7_DBC_AD0P_64 Sch=syzygy_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AF3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[2] }]; #IO_L21P_T3L_N5_AD8P_64 Sch=syzygy_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AF5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[3] }]; #IO_L12P_T1U_N11_GC_64 Sch=syzygy_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AE7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[4] }]; #IO_L4P_T0U_N7_DBC_AD7P_64 Sch=syzygy_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN AG5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[5] }]; #IO_L10P_T1U_N7_QBC_AD4P_64 Sch=syzygy_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[6] }]; #IO_L3P_T0L_N5_AD15P_65 Sch=syzygy_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[7] }]; #IO_L2P_T0L_N3_65 Sch=syzygy_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L4P_AD8P_43/44 Sch=syzygy_s[16]
|
||||
#set_property -dict { PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L6P_HDGC_AD6P_43/44 Sch=syzygy_s[17]
|
||||
#set_property -dict { PACKAGE_PIN AF10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L4N_AD8N_43/44 Sch=syzygy_s[18]
|
||||
#set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L6N_HDGC_AD6N_43/44 Sch=syzygy_s[19]
|
||||
#set_property -dict { PACKAGE_PIN AF11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L2P_AD10P_43/44 Sch=syzygy_s[20]
|
||||
#set_property -dict { PACKAGE_PIN AE12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L5P_HDGC_AD7P_43/44 Sch=syzygy_s[21]
|
||||
#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L5N_HDGC_AD7N_43/44 Sch=syzygy_s[22]
|
||||
#set_property -dict { PACKAGE_PIN AH12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L3P_AD9P_43/44 Sch=syzygy_s[23]
|
||||
#set_property -dict { PACKAGE_PIN AG11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L2N_AD10N_43/44 Sch=syzygy_s[24]
|
||||
#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L1P_AD11P_43/44 Sch=syzygy_s[25]
|
||||
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L3N_AD9N_43/44 Sch=syzygy_s[26]
|
||||
#set_property -dict { PACKAGE_PIN AH10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L1N_AD11N_43/44 Sch=syzygy_s[27]
|
||||
#set_property -dict { PACKAGE_PIN AD4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_n }]; #IO_L13N_T2L_N1_GC_QBC_64 Sch=syzygy_in_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AD5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_p }]; #IO_L13P_T2L_N0_GC_QBC_64 Sch=syzygy_in_clk_p
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_n }]; #IO_L1N_T0L_N1_DBC_65 Sch=syzygy_out_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_p }]; #IO_L1P_T0L_N0_DBC_65 Sch=syzygy_out_clk_p
|
||||
|
||||
## FMC connector
|
||||
#set_property -dict { PACKAGE_PIN M6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk0_m2c_p }]; #IO_L14P_T2L_N2_GC_65 Sch=fmc_clk0_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk1_m2c_p }]; #IO_L12P_T1U_N10_GC_65 Sch=fmc_clk1_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L6 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2L_N1_GC_QBC_65 Sch=fmc_la00_cc_n
|
||||
#set_property -dict { PACKAGE_PIN L7 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2L_N0_GC_QBC_65 Sch=fmc_la00_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_n }]; #IO_L7N_T1L_N1_QBC_AD13N_65 Sch=fmc_la01_cc_n
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_p }]; #IO_L7P_T1L_N0_QBC_AD13P_65 Sch=fmc_la01_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVDS } [get_ports { fmc_la_n[02] }]; #IO_L20N_T3L_N3_AD1N_65 Sch=fmc_la_n[02]
|
||||
#set_property -dict { PACKAGE_PIN J6 IOSTANDARD LVDS } [get_ports { fmc_la_p[02] }]; #IO_L20P_T3L_N2_AD1P_65 Sch=fmc_la_p[02]
|
||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVDS } [get_ports { fmc_la_n[03] }]; #IO_L11N_T1U_N9_GC_65 Sch=fmc_la_n[03]
|
||||
#set_property -dict { PACKAGE_PIN K4 IOSTANDARD LVDS } [get_ports { fmc_la_p[03] }]; #IO_L11P_T1U_N8_GC_65 Sch=fmc_la_p[03]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVDS } [get_ports { fmc_la_n[04] }]; #IO_L9N_T1L_N5_AD12N_65 Sch=fmc_la_n[04]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVDS } [get_ports { fmc_la_p[04] }]; #IO_L9P_T1L_N4_AD12P_65 Sch=fmc_la_p[04]
|
||||
#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVDS } [get_ports { fmc_la_n[05] }]; #IO_L6N_T0U_N11_AD6N_65 Sch=fmc_la_n[05]
|
||||
#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVDS } [get_ports { fmc_la_p[05] }]; #IO_L6P_T0U_N10_AD6P_65 Sch=fmc_la_p[05]
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVDS } [get_ports { fmc_la_n[06] }]; #IO_L17N_T2U_N9_AD10N_65 Sch=fmc_la_n[06]
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVDS } [get_ports { fmc_la_p[06] }]; #IO_L17P_T2U_N8_AD10P_65 Sch=fmc_la_p[06]
|
||||
#set_property -dict { PACKAGE_PIN J9 IOSTANDARD LVDS } [get_ports { fmc_la_n[07] }]; #IO_L23N_T3U_N9_65 Sch=fmc_la_n[07]
|
||||
#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVDS } [get_ports { fmc_la_p[07] }]; #IO_L23P_T3U_N8_I2C_SCLK_65 Sch=fmc_la_p[07]
|
||||
#set_property -dict { PACKAGE_PIN T7 IOSTANDARD LVDS } [get_ports { fmc_la_n[08] }]; #IO_L5N_T0U_N9_AD14N_65 Sch=fmc_la_n[08]
|
||||
#set_property -dict { PACKAGE_PIN R7 IOSTANDARD LVDS } [get_ports { fmc_la_p[08] }]; #IO_L5P_T0U_N8_AD14P_65 Sch=fmc_la_p[08]
|
||||
#set_property -dict { PACKAGE_PIN L8 IOSTANDARD LVDS } [get_ports { fmc_la_n[09] }]; #IO_L18N_T2U_N11_AD2N_65 Sch=fmc_la_n[09]
|
||||
#set_property -dict { PACKAGE_PIN M8 IOSTANDARD LVDS } [get_ports { fmc_la_p[09] }]; #IO_L18P_T2U_N10_AD2P_65 Sch=fmc_la_p[09]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVDS } [get_ports { fmc_la_n[10] }]; #IO_L8N_T1L_N3_AD5N_65 Sch=fmc_la_n[10]
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVDS } [get_ports { fmc_la_p[10] }]; #IO_L8P_T1L_N2_AD5P_65 Sch=fmc_la_p[10]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVDS } [get_ports { fmc_la_n[11] }]; #IO_L19N_T3L_N1_DBC_AD9N_65 Sch=fmc_la_n[11]
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVDS } [get_ports { fmc_la_p[11] }]; #IO_L19P_T3L_N0_DBC_AD9P_65 Sch=fmc_la_p[11]
|
||||
#set_property -dict { PACKAGE_PIN H7 IOSTANDARD LVDS } [get_ports { fmc_la_n[12] }]; #IO_L21N_T3L_N5_AD8N_65 Sch=fmc_la_n[12]
|
||||
#set_property -dict { PACKAGE_PIN J7 IOSTANDARD LVDS } [get_ports { fmc_la_p[12] }]; #IO_L21P_T3L_N4_AD8P_65 Sch=fmc_la_p[12]
|
||||
#set_property -dict { PACKAGE_PIN N6 IOSTANDARD LVDS } [get_ports { fmc_la_n[13] }]; #IO_L15N_T2L_N5_AD11N_65 Sch=fmc_la_n[13]
|
||||
#set_property -dict { PACKAGE_PIN N7 IOSTANDARD LVDS } [get_ports { fmc_la_p[13] }]; #IO_L15P_T2L_N4_AD11P_65 Sch=fmc_la_p[13]
|
||||
#set_property -dict { PACKAGE_PIN P6 IOSTANDARD LVDS } [get_ports { fmc_la_n[14] }]; #IO_L16N_T2U_N7_QBC_AD3N_65 Sch=fmc_la_n[14]
|
||||
#set_property -dict { PACKAGE_PIN P7 IOSTANDARD LVDS } [get_ports { fmc_la_p[14] }]; #IO_L16P_T2U_N6_QBC_AD3P_65 Sch=fmc_la_p[14]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVDS } [get_ports { fmc_la_n[15] }]; #IO_L4N_T0U_N7_DBC_AD7N_65 Sch=fmc_la_n[15]
|
||||
#set_property -dict { PACKAGE_PIN R8 IOSTANDARD LVDS } [get_ports { fmc_la_p[15] }]; #IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 Sch=fmc_la_p[15]
|
||||
#set_property -dict { PACKAGE_PIN K7 IOSTANDARD LVDS } [get_ports { fmc_la_n[16] }]; #IO_L22N_T3U_N7_DBC_AD0N_65 Sch=fmc_la_n[16]
|
||||
#set_property -dict { PACKAGE_PIN K8 IOSTANDARD LVDS } [get_ports { fmc_la_p[16] }]; #IO_L22P_T3U_N6_DBC_AD0P_65 Sch=fmc_la_p[16]
|
||||
#set_property -dict { PACKAGE_PIN AD1 IOSTANDARD LVDS } [get_ports { fmc_la_n[17] }]; #IO_L16N_T2U_N7_QBC_AD3N_64 Sch=fmc_la17_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AD2 IOSTANDARD LVDS } [get_ports { fmc_la_p[17] }]; #IO_L16P_T2U_N6_QBC_AD3P_64 Sch=fmc_la17_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AH9 IOSTANDARD LVDS } [get_ports { fmc_la_n[18] }]; #IO_L10N_T1U_N7_QBC_AD4N_64 Sch=fmc_la18_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AG9 IOSTANDARD LVDS } [get_ports { fmc_la_p[18] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=fmc_la18_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AC3 IOSTANDARD LVDS } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2U_N9_AD10N_64 Sch=fmc_la_n[19]
|
||||
#set_property -dict { PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2U_N8_AD10P_64 Sch=fmc_la_p[19]
|
||||
#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD LVDS } [get_ports { fmc_la_n[20] }]; #IO_L15N_T2L_N5_AD11N_64 Sch=fmc_la_n[20]
|
||||
#set_property -dict { PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports { fmc_la_p[20] }]; #IO_L15P_T2L_N4_AD11P_64 Sch=fmc_la_p[20]
|
||||
#set_property -dict { PACKAGE_PIN AG1 IOSTANDARD LVDS } [get_ports { fmc_la_n[21] }]; #IO_L24N_T3U_N11_64 Sch=fmc_la_n[21]
|
||||
#set_property -dict { PACKAGE_PIN AF1 IOSTANDARD LVDS } [get_ports { fmc_la_p[21] }]; #IO_L24P_T3U_N10_64 Sch=fmc_la_p[21]
|
||||
#set_property -dict { PACKAGE_PIN AC8 IOSTANDARD LVDS } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0L_N5_AD15N_64 Sch=fmc_la_n[22]
|
||||
#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVDS } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0L_N4_AD15P_64 Sch=fmc_la_p[22]
|
||||
#set_property -dict { PACKAGE_PIN AH1 IOSTANDARD LVDS } [get_ports { fmc_la_n[23] }]; #IO_L23N_T3U_N9_64 Sch=fmc_la_n[23]
|
||||
#set_property -dict { PACKAGE_PIN AH2 IOSTANDARD LVDS } [get_ports { fmc_la_p[23] }]; #IO_L23P_T3U_N8_64 Sch=fmc_la_p[23]
|
||||
#set_property -dict { PACKAGE_PIN AF6 IOSTANDARD LVDS } [get_ports { fmc_la_n[24] }]; #IO_L11N_T1U_N9_GC_64 Sch=fmc_la_n[24]
|
||||
#set_property -dict { PACKAGE_PIN AF7 IOSTANDARD LVDS } [get_ports { fmc_la_p[24] }]; #IO_L11P_T1U_N8_GC_64 Sch=fmc_la_p[24]
|
||||
#set_property -dict { PACKAGE_PIN AH3 IOSTANDARD LVDS } [get_ports { fmc_la_n[25] }]; #IO_L20N_T3L_N3_AD1N_64 Sch=fmc_la_n[25]
|
||||
#set_property -dict { PACKAGE_PIN AG3 IOSTANDARD LVDS } [get_ports { fmc_la_p[25] }]; #IO_L20P_T3L_N2_AD1P_64 Sch=fmc_la_p[25]
|
||||
#set_property -dict { PACKAGE_PIN AD9 IOSTANDARD LVDS } [get_ports { fmc_la_n[26] }]; #IO_L1N_T0L_N1_DBC_64 Sch=fmc_la_n[26]
|
||||
#set_property -dict { PACKAGE_PIN AC9 IOSTANDARD LVDS } [get_ports { fmc_la_p[26] }]; #IO_L1P_T0L_N0_DBC_64 Sch=fmc_la_p[26]
|
||||
#set_property -dict { PACKAGE_PIN AH4 IOSTANDARD LVDS } [get_ports { fmc_la_n[27] }]; #IO_L19N_T3L_N1_DBC_AD9N_64 Sch=fmc_la_n[27]
|
||||
#set_property -dict { PACKAGE_PIN AG4 IOSTANDARD LVDS } [get_ports { fmc_la_p[27] }]; #IO_L19P_T3L_N0_DBC_AD9P_64 Sch=fmc_la_p[27]
|
||||
#set_property -dict { PACKAGE_PIN AE8 IOSTANDARD LVDS } [get_ports { fmc_la_n[28] }]; #IO_L2N_T0L_N3_64 Sch=fmc_la_n[28]
|
||||
#set_property -dict { PACKAGE_PIN AE9 IOSTANDARD LVDS } [get_ports { fmc_la_p[28] }]; #IO_L2P_T0L_N2_64 Sch=fmc_la_p[28]
|
||||
#set_property -dict { PACKAGE_PIN AH7 IOSTANDARD LVDS } [get_ports { fmc_la_n[29] }]; #IO_L9N_T1L_N5_AD12N_64 Sch=fmc_la_n[29]
|
||||
#set_property -dict { PACKAGE_PIN AH8 IOSTANDARD LVDS } [get_ports { fmc_la_p[29] }]; #IO_L9P_T1L_N4_AD12P_64 Sch=fmc_la_p[29]
|
||||
#set_property -dict { PACKAGE_PIN AC7 IOSTANDARD LVDS } [get_ports { fmc_la_n[30] }]; #IO_L5N_T0U_N9_AD14N_64 Sch=fmc_la_n[30]
|
||||
#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVDS } [get_ports { fmc_la_p[30] }]; #IO_L5P_T0U_N8_AD14P_64 Sch=fmc_la_p[30]
|
||||
#set_property -dict { PACKAGE_PIN AG8 IOSTANDARD LVDS } [get_ports { fmc_la_n[31] }]; #IO_L8N_T1L_N3_AD5N_64 Sch=fmc_la_n[31]
|
||||
#set_property -dict { PACKAGE_PIN AF8 IOSTANDARD LVDS } [get_ports { fmc_la_p[31] }]; #IO_L8P_T1L_N2_AD5P_64 Sch=fmc_la_p[31]
|
||||
#set_property -dict { PACKAGE_PIN AC2 IOSTANDARD LVDS } [get_ports { fmc_la_n[32] }]; #IO_L14N_T2L_N3_GC_64 Sch=fmc_la_n[32]
|
||||
#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD LVDS } [get_ports { fmc_la_p[32] }]; #IO_L14P_T2L_N2_GC_64 Sch=fmc_la_p[32]
|
||||
#set_property -dict { PACKAGE_PIN AC6 IOSTANDARD LVDS } [get_ports { fmc_la_n[33] }]; #IO_L6N_T0U_N11_AD6N_64 Sch=fmc_la_n[33]
|
||||
#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVDS } [get_ports { fmc_la_p[33] }]; #IO_L6P_T0U_N10_AD6P_64 Sch=fmc_la_p[33]
|
||||
|
||||
#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { fmc_prsntn_m2c }]; #IO_L11N_AD9N_44/24
|
||||
|
||||
## Power-good input for VADJ supply rail
|
||||
#set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS33 } [get_ports { pg_vadj_r }]; #IO_L12N_AD8N_44/24 Sch=pg_vadj_r
|
||||
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y168/PAD]
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y116/PAD]
|
||||
|
||||
#set_property IOSTANDARD ANALOG [get_ports Vp_Vn_0_v_p]
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,269 @@
|
||||
#### This file is a general .xdc for the Genesys ZU-3EG Rev. B
|
||||
#### To use it in a project:
|
||||
#### - uncomment the lines corresponding to used pins
|
||||
#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
#set_property DCI_CASCADE {64} [get_iobanks 65]
|
||||
|
||||
## Crypto
|
||||
#set_property -dict { PACKAGE_PIN AD15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L5P_HDGC_44/24 Sch=crypto_sda
|
||||
|
||||
# Sysclk is a 125 MHz PL reference clock generated by the external Ethernet PHY
|
||||
# It connects to an HDGC pin, so it has direct connection only to BUFG primitives.
|
||||
# When using it as input clock to CMT primitives (MMCM/PLL), it needs to go through
|
||||
# BUFG first. Choose "Global Buffer" in Clocking Wizard IP customization.
|
||||
# Might need CLOCK_DEDICATED_ROUTE FALSE
|
||||
#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS18 } [get_ports { sysclk }];
|
||||
|
||||
## MIPI A Port
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS12 } [get_ports { mipi_a_pwup_ls }]; #IO_L22N_T3U_N7_DBC_AD0N_66 Sch=mipi_a_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN G1 [get_ports mipi_a_clk_p] #IO_L1P_T0L_N0_DBC_66 Sch=mipi_a_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_n]
|
||||
##set_property PACKAGE_PIN E1 [get_ports mipi_a_lane_p[0]] #IO_L2P_T0L_N2_66 Sch=mipi_a_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[0]]
|
||||
##set_property PACKAGE_PIN F2 [get_ports mipi_a_lane_p[1]] #IO_L3P_T0L_N4_AD15P_66 Sch=mipi_a_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[1]]]
|
||||
|
||||
## MIPI B Port
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS12 } [get_ports { mipi_b_pwup_ls }]; #IO_L23P_T3U_N8_66 Sch=mipi_b_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN B5 [get_ports mipi_b_clk_p] #IO_L19P_T3L_N0_DBC_AD9P_66 Sch=mipi_b_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_n]
|
||||
##set_property PACKAGE_PIN C6 [get_ports mipi_b_lane_p[0]] #IO_L20P_T3L_N2_AD1P_66 Sch=mipi_b_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[0]]
|
||||
##set_property PACKAGE_PIN A7 [get_ports mipi_b_lane_p[1]] #IO_L21P_T3L_N4_AD8P_66 Sch=mipi_b_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[1]]
|
||||
|
||||
## Audio CODEC I2S, I2C
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L11N_AD9N_45/25 Sch=aud_scl
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS18 } [get_ports { aud_sda_io }]; #IO_L12P_AD8P_45/25 Sch=aud_sda
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_AD10N_45/25 Sch=aud_lrclk
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L12N_AD8N_45/25 Sch=aud_bclk
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L9P_AD11P_45/25 Sch=aud_mclk
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L10P_AD10P_45/25 Sch=aud_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L8N_HDGC_45/25 Sch=aud_dac_sdata
|
||||
|
||||
## PMOD XADC
|
||||
## Commented because pins are contrained by System Management Wizard. Only >2018.2 lets us select bank 43.
|
||||
#set_property -dict { PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_n }]; #IO_L10N_AD2N_43/44 Sch=ja1_r_n
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_p }]; #IO_L10P_AD2P_43/44 Sch=ja1_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_n }]; #IO_L9N_AD3N_43/44 Sch=ja2_r_n
|
||||
#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_p }]; #IO_L9P_AD3P_43/44 Sch=ja2_r_p
|
||||
#set_property -dict { PACKAGE_PIN AB9 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_n }]; #IO_L12N_AD0N_43/44 Sch=ja3_r_n
|
||||
#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_p }]; #IO_L12P_AD0P_43/44 Sch=ja3_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_n }]; #IO_L11N_AD1N_43/44 Sch=ja4_r_n
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_p }]; #IO_L11P_AD1P_43/44 Sch=ja4_r_p
|
||||
|
||||
## Platform MCU signals
|
||||
#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[0] }]; #IO_L6P_HDGC_44/24 Sch=vadj_level[0]
|
||||
#set_property -dict { PACKAGE_PIN AC13 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[1] }]; #IO_L6N_HDGC_44/24 Sch=vadj_level[1]
|
||||
#set_property -dict { PACKAGE_PIN G10 IOSTANDARD LVCMOS18 } [get_ports { vadj_auton }]; #IO_L3N_AD13N_45/25 Sch=vadj_auton
|
||||
#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_detectedn }]; #IO_L3P_AD13P_45/25 Sch=syzygy_detectedn
|
||||
|
||||
##DisplayPort AUX channel over EMIO
|
||||
#set_property -dict { PACKAGE_PIN K12 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_din }]; #IO_L2N_AD14N_45/25 Sch=dp_aux_din
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_doe }]; #IO_L2P_AD14P_45/25 Sch=dp_aux_doe
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_dout }]; #IO_L1P_AD15P_45/25 Sch=dp_aux_dout
|
||||
#set_property -dict { PACKAGE_PIN J10 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_hotplug_detect }]; #IO_L1N_AD15N_45/25 Sch=dp_aux_hotplug_detect
|
||||
|
||||
## Mini PCIe Auxiliary
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { pcie_w_disable2n }]; #IO_L12P_AD8P_44/24 Sch=pcie_w_disable2n
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS12 } [get_ports { pcie_w_disable[1] }]; #IO_L9P_T1L_N4_AD12P_66 Sch=pcie_w_disable[1]
|
||||
|
||||
## USB 2.0 Overcurrent EMIO
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS12 PULLUP true } [get_ports { usb20_ocn }];#IO_L18N_T2U_N11_AD2N_66 Sch=usb20_ocn
|
||||
|
||||
## Ethernet JTAG
|
||||
#set_property -dict { PACKAGE_PIN F7 LVCMOS12 } [get_ports { eth_tms_ls }]; #IO_L16N_T2U_N7_QBC_AD3N_66 Sch=eth_tms_ls
|
||||
#set_property -dict { PACKAGE_PIN F8 LVCMOS12 } [get_ports { eth_tdi_ls }]; #IO_L17P_T2U_N8_AD10P_66 Sch=eth_tdi_ls
|
||||
#set_property -dict { PACKAGE_PIN E8 LVCMOS12 } [get_ports { eth_tck_ls }]; #IO_L17N_T2U_N9_AD10N_66 Sch=eth_tck_ls
|
||||
#set_property -dict { PACKAGE_PIN E9 LVCMOS12 } [get_ports { eth_tdo_ls }]; #IO_L18P_T2U_N10_AD2P_66 Sch=eth_tdo_ls
|
||||
|
||||
## PMOD JB
|
||||
#set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8N_HDGC_AD4N_46/26 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN AG14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L2N_AD10N_46/26 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_AD11P_46/26 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN AG13 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L8P_HDGC_AD4P_46/26 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6P_HDGC_AD6P_46/26 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN AF13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L2P_AD10P_46/26 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L5P_HDGC_AD7P_46/26 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN AH13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L1N_AD11N_46/26 Sch=jb[10]
|
||||
|
||||
## PMOD JC
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L6N_HDGC_AD6N_46/26 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L7P_HDGC_AD5P_46/26 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L3P_AD9P_46/26 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L5N_HDGC_AD7N_46/26 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L7N_HDGC_AD5N_46/26 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L4N_AD8N_46/26 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L4P_AD8P_46/26 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L3N_AD9N_46/26 Sch=jc[10]
|
||||
|
||||
## PMOD JD
|
||||
#set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L4P_AD12P_44/24 Sch=jd[1]
|
||||
#set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L2P_AD14P_44/24 Sch=jd[2]
|
||||
#set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L2N_AD14N_44/24 Sch=jd[3]
|
||||
#set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L3P_AD13P_44/24 Sch=jd[4]
|
||||
#set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L1N_AD15N_44/24 Sch=jd[7]
|
||||
#set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L4N_AD12N_44/24 Sch=jd[8]
|
||||
#set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L1P_AD15P_44/24 Sch=jd[9]
|
||||
#set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L3N_AD13N_44/24 Sch=jd[10]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN B10 IOSTANDARD LVCMOS18 } [get_ports { btn[2] }]; #IO_L9N_AD11N_45/25 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports { btn[3] }]; #IO_L4N_AD12N_45/25 Sch=btn[3]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS18 } [get_ports { btn[4] }]; #IO_L4P_AD12P_45/25 Sch=btn[4]
|
||||
#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS18 } [get_ports { btn[5] }]; #IO_L6P_HDGC_45/25 Sch=btn[5]
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS18 } [get_ports { btn[6] }]; #IO_L11P_AD9P_45/25 Sch=btn[6]
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L8N_HDGC_44/24 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L10N_AD10N_44/24 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L11P_AD9P_44/24 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L8P_HDGC_44/24 Sch=sw[3]
|
||||
|
||||
## LED
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ld[0] }]; #IO_L12P_AD0P_46/26 Sch=ld[1]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { ld[1] }]; #IO_L12N_AD0N_46/26 Sch=ld[2]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ld[2] }]; #IO_L11P_AD1P_46/26 Sch=ld[3]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ld[3] }]; #IO_L11N_AD1N_46/26 Sch=ld[4]
|
||||
|
||||
## RGB LED
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS12 } [get_ports { ld5_b }]; #IO_L23N_T3U_N9_66 Sch=ld5_b
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS12 } [get_ports { ld5_g }]; #IO_L24N_T3U_N11_66 Sch=ld5_g
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS12 } [get_ports { ld5_r }]; #IO_L24P_T3U_N10_66 Sch=ld5_r
|
||||
|
||||
## GTH reference clock jitter filter auxiliary
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS12 } [get_ports { clkgth_intrn_ls }]; #IO_L11N_T1U_N9_GC_66 Sch=clkgth_intrn_ls
|
||||
#set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS12 } [get_ports { clkgth_loln_ls }]; #IO_L13N_T2L_N1_GC_QBC_66 Sch=clkgth_loln_ls
|
||||
#set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS12 } [get_ports { clkgth_rst }]; #IO_L16P_T2U_N6_QBC_AD3P_66 Sch=clkgth_rst
|
||||
|
||||
## MUX I2C
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS12 } [get_ports { fpga_mux_rst }]; #IO_L15N_T2L_N5_AD11N_66 Sch=fpga_mux_rst
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_scl_ls }]; #IO_L9P_AD3P_46/26 Sch=mux_scl_ls
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_sda_ls }]; #IO_L9N_AD3N_46/26 Sch=mux_sda_ls
|
||||
|
||||
## SYZYGY
|
||||
#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[0] }]; #IO_L18P_T2U_N10_AD2P_64 Sch=syzygy_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AE2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[1] }]; #IO_L22P_T3U_N6_DBC_AD0P_64 Sch=syzygy_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AE3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[2] }]; #IO_L21P_T3L_N4_AD8P_64 Sch=syzygy_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AE5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[3] }]; #IO_L12P_T1U_N10_GC_64 Sch=syzygy_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN AD7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[4] }]; #IO_L4P_T0U_N6_DBC_AD7P_64 Sch=syzygy_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN AG6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[5] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=syzygy_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[6] }]; #IO_L3P_T0L_N4_AD15P_65 Sch=syzygy_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[7] }]; #IO_L2P_T0L_N2_65 Sch=syzygy_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN AC1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[0] }]; #IO_L18P_T2U_N11_AD2P_64 Sch=syzygy_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AF2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[1] }]; #IO_L22P_T3U_N7_DBC_AD0P_64 Sch=syzygy_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AF3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[2] }]; #IO_L21P_T3L_N5_AD8P_64 Sch=syzygy_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AF5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[3] }]; #IO_L12P_T1U_N11_GC_64 Sch=syzygy_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AE7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[4] }]; #IO_L4P_T0U_N7_DBC_AD7P_64 Sch=syzygy_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN AG5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[5] }]; #IO_L10P_T1U_N7_QBC_AD4P_64 Sch=syzygy_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[6] }]; #IO_L3P_T0L_N5_AD15P_65 Sch=syzygy_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[7] }]; #IO_L2P_T0L_N3_65 Sch=syzygy_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L4P_AD8P_43/44 Sch=syzygy_s[16]
|
||||
#set_property -dict { PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L6P_HDGC_AD6P_43/44 Sch=syzygy_s[17]
|
||||
#set_property -dict { PACKAGE_PIN AF10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L4N_AD8N_43/44 Sch=syzygy_s[18]
|
||||
#set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L6N_HDGC_AD6N_43/44 Sch=syzygy_s[19]
|
||||
#set_property -dict { PACKAGE_PIN AF11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L2P_AD10P_43/44 Sch=syzygy_s[20]
|
||||
#set_property -dict { PACKAGE_PIN AE12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L5P_HDGC_AD7P_43/44 Sch=syzygy_s[21]
|
||||
#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L5N_HDGC_AD7N_43/44 Sch=syzygy_s[22]
|
||||
#set_property -dict { PACKAGE_PIN AH12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L3P_AD9P_43/44 Sch=syzygy_s[23]
|
||||
#set_property -dict { PACKAGE_PIN AG11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L2N_AD10N_43/44 Sch=syzygy_s[24]
|
||||
#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L1P_AD11P_43/44 Sch=syzygy_s[25]
|
||||
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L3N_AD9N_43/44 Sch=syzygy_s[26]
|
||||
#set_property -dict { PACKAGE_PIN AH10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L1N_AD11N_43/44 Sch=syzygy_s[27]
|
||||
#set_property -dict { PACKAGE_PIN AD4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_n }]; #IO_L13N_T2L_N1_GC_QBC_64 Sch=syzygy_in_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AD5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_p }]; #IO_L13P_T2L_N0_GC_QBC_64 Sch=syzygy_in_clk_p
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_n }]; #IO_L1N_T0L_N1_DBC_65 Sch=syzygy_out_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_p }]; #IO_L1P_T0L_N0_DBC_65 Sch=syzygy_out_clk_p
|
||||
|
||||
## FMC connector
|
||||
#set_property -dict { PACKAGE_PIN M6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk0_m2c_p }]; #IO_L14P_T2L_N2_GC_65 Sch=fmc_clk0_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk1_m2c_p }]; #IO_L12P_T1U_N10_GC_65 Sch=fmc_clk1_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L6 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2L_N1_GC_QBC_65 Sch=fmc_la00_cc_n
|
||||
#set_property -dict { PACKAGE_PIN L7 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2L_N0_GC_QBC_65 Sch=fmc_la00_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_n }]; #IO_L7N_T1L_N1_QBC_AD13N_65 Sch=fmc_la01_cc_n
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_p }]; #IO_L7P_T1L_N0_QBC_AD13P_65 Sch=fmc_la01_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVDS } [get_ports { fmc_la_n[02] }]; #IO_L20N_T3L_N3_AD1N_65 Sch=fmc_la_n[02]
|
||||
#set_property -dict { PACKAGE_PIN J6 IOSTANDARD LVDS } [get_ports { fmc_la_p[02] }]; #IO_L20P_T3L_N2_AD1P_65 Sch=fmc_la_p[02]
|
||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVDS } [get_ports { fmc_la_n[03] }]; #IO_L11N_T1U_N9_GC_65 Sch=fmc_la_n[03]
|
||||
#set_property -dict { PACKAGE_PIN K4 IOSTANDARD LVDS } [get_ports { fmc_la_p[03] }]; #IO_L11P_T1U_N8_GC_65 Sch=fmc_la_p[03]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVDS } [get_ports { fmc_la_n[04] }]; #IO_L9N_T1L_N5_AD12N_65 Sch=fmc_la_n[04]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVDS } [get_ports { fmc_la_p[04] }]; #IO_L9P_T1L_N4_AD12P_65 Sch=fmc_la_p[04]
|
||||
#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVDS } [get_ports { fmc_la_n[05] }]; #IO_L6N_T0U_N11_AD6N_65 Sch=fmc_la_n[05]
|
||||
#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVDS } [get_ports { fmc_la_p[05] }]; #IO_L6P_T0U_N10_AD6P_65 Sch=fmc_la_p[05]
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVDS } [get_ports { fmc_la_n[06] }]; #IO_L17N_T2U_N9_AD10N_65 Sch=fmc_la_n[06]
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVDS } [get_ports { fmc_la_p[06] }]; #IO_L17P_T2U_N8_AD10P_65 Sch=fmc_la_p[06]
|
||||
#set_property -dict { PACKAGE_PIN J9 IOSTANDARD LVDS } [get_ports { fmc_la_n[07] }]; #IO_L23N_T3U_N9_65 Sch=fmc_la_n[07]
|
||||
#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVDS } [get_ports { fmc_la_p[07] }]; #IO_L23P_T3U_N8_I2C_SCLK_65 Sch=fmc_la_p[07]
|
||||
#set_property -dict { PACKAGE_PIN T7 IOSTANDARD LVDS } [get_ports { fmc_la_n[08] }]; #IO_L5N_T0U_N9_AD14N_65 Sch=fmc_la_n[08]
|
||||
#set_property -dict { PACKAGE_PIN R7 IOSTANDARD LVDS } [get_ports { fmc_la_p[08] }]; #IO_L5P_T0U_N8_AD14P_65 Sch=fmc_la_p[08]
|
||||
#set_property -dict { PACKAGE_PIN L8 IOSTANDARD LVDS } [get_ports { fmc_la_n[09] }]; #IO_L18N_T2U_N11_AD2N_65 Sch=fmc_la_n[09]
|
||||
#set_property -dict { PACKAGE_PIN M8 IOSTANDARD LVDS } [get_ports { fmc_la_p[09] }]; #IO_L18P_T2U_N10_AD2P_65 Sch=fmc_la_p[09]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVDS } [get_ports { fmc_la_n[10] }]; #IO_L8N_T1L_N3_AD5N_65 Sch=fmc_la_n[10]
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVDS } [get_ports { fmc_la_p[10] }]; #IO_L8P_T1L_N2_AD5P_65 Sch=fmc_la_p[10]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVDS } [get_ports { fmc_la_n[11] }]; #IO_L19N_T3L_N1_DBC_AD9N_65 Sch=fmc_la_n[11]
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVDS } [get_ports { fmc_la_p[11] }]; #IO_L19P_T3L_N0_DBC_AD9P_65 Sch=fmc_la_p[11]
|
||||
#set_property -dict { PACKAGE_PIN H7 IOSTANDARD LVDS } [get_ports { fmc_la_n[12] }]; #IO_L21N_T3L_N5_AD8N_65 Sch=fmc_la_n[12]
|
||||
#set_property -dict { PACKAGE_PIN J7 IOSTANDARD LVDS } [get_ports { fmc_la_p[12] }]; #IO_L21P_T3L_N4_AD8P_65 Sch=fmc_la_p[12]
|
||||
#set_property -dict { PACKAGE_PIN N6 IOSTANDARD LVDS } [get_ports { fmc_la_n[13] }]; #IO_L15N_T2L_N5_AD11N_65 Sch=fmc_la_n[13]
|
||||
#set_property -dict { PACKAGE_PIN N7 IOSTANDARD LVDS } [get_ports { fmc_la_p[13] }]; #IO_L15P_T2L_N4_AD11P_65 Sch=fmc_la_p[13]
|
||||
#set_property -dict { PACKAGE_PIN P6 IOSTANDARD LVDS } [get_ports { fmc_la_n[14] }]; #IO_L16N_T2U_N7_QBC_AD3N_65 Sch=fmc_la_n[14]
|
||||
#set_property -dict { PACKAGE_PIN P7 IOSTANDARD LVDS } [get_ports { fmc_la_p[14] }]; #IO_L16P_T2U_N6_QBC_AD3P_65 Sch=fmc_la_p[14]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVDS } [get_ports { fmc_la_n[15] }]; #IO_L4N_T0U_N7_DBC_AD7N_65 Sch=fmc_la_n[15]
|
||||
#set_property -dict { PACKAGE_PIN R8 IOSTANDARD LVDS } [get_ports { fmc_la_p[15] }]; #IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 Sch=fmc_la_p[15]
|
||||
#set_property -dict { PACKAGE_PIN K7 IOSTANDARD LVDS } [get_ports { fmc_la_n[16] }]; #IO_L22N_T3U_N7_DBC_AD0N_65 Sch=fmc_la_n[16]
|
||||
#set_property -dict { PACKAGE_PIN K8 IOSTANDARD LVDS } [get_ports { fmc_la_p[16] }]; #IO_L22P_T3U_N6_DBC_AD0P_65 Sch=fmc_la_p[16]
|
||||
#set_property -dict { PACKAGE_PIN AD1 IOSTANDARD LVDS } [get_ports { fmc_la_n[17] }]; #IO_L16N_T2U_N7_QBC_AD3N_64 Sch=fmc_la17_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AD2 IOSTANDARD LVDS } [get_ports { fmc_la_p[17] }]; #IO_L16P_T2U_N6_QBC_AD3P_64 Sch=fmc_la17_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AH9 IOSTANDARD LVDS } [get_ports { fmc_la_n[18] }]; #IO_L10N_T1U_N7_QBC_AD4N_64 Sch=fmc_la18_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AG9 IOSTANDARD LVDS } [get_ports { fmc_la_p[18] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=fmc_la18_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AC3 IOSTANDARD LVDS } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2U_N9_AD10N_64 Sch=fmc_la_n[19]
|
||||
#set_property -dict { PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2U_N8_AD10P_64 Sch=fmc_la_p[19]
|
||||
#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD LVDS } [get_ports { fmc_la_n[20] }]; #IO_L15N_T2L_N5_AD11N_64 Sch=fmc_la_n[20]
|
||||
#set_property -dict { PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports { fmc_la_p[20] }]; #IO_L15P_T2L_N4_AD11P_64 Sch=fmc_la_p[20]
|
||||
#set_property -dict { PACKAGE_PIN AG1 IOSTANDARD LVDS } [get_ports { fmc_la_n[21] }]; #IO_L24N_T3U_N11_64 Sch=fmc_la_n[21]
|
||||
#set_property -dict { PACKAGE_PIN AF1 IOSTANDARD LVDS } [get_ports { fmc_la_p[21] }]; #IO_L24P_T3U_N10_64 Sch=fmc_la_p[21]
|
||||
#set_property -dict { PACKAGE_PIN AC8 IOSTANDARD LVDS } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0L_N5_AD15N_64 Sch=fmc_la_n[22]
|
||||
#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVDS } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0L_N4_AD15P_64 Sch=fmc_la_p[22]
|
||||
#set_property -dict { PACKAGE_PIN AH1 IOSTANDARD LVDS } [get_ports { fmc_la_n[23] }]; #IO_L23N_T3U_N9_64 Sch=fmc_la_n[23]
|
||||
#set_property -dict { PACKAGE_PIN AH2 IOSTANDARD LVDS } [get_ports { fmc_la_p[23] }]; #IO_L23P_T3U_N8_64 Sch=fmc_la_p[23]
|
||||
#set_property -dict { PACKAGE_PIN AF6 IOSTANDARD LVDS } [get_ports { fmc_la_n[24] }]; #IO_L11N_T1U_N9_GC_64 Sch=fmc_la_n[24]
|
||||
#set_property -dict { PACKAGE_PIN AF7 IOSTANDARD LVDS } [get_ports { fmc_la_p[24] }]; #IO_L11P_T1U_N8_GC_64 Sch=fmc_la_p[24]
|
||||
#set_property -dict { PACKAGE_PIN AH3 IOSTANDARD LVDS } [get_ports { fmc_la_n[25] }]; #IO_L20N_T3L_N3_AD1N_64 Sch=fmc_la_n[25]
|
||||
#set_property -dict { PACKAGE_PIN AG3 IOSTANDARD LVDS } [get_ports { fmc_la_p[25] }]; #IO_L20P_T3L_N2_AD1P_64 Sch=fmc_la_p[25]
|
||||
#set_property -dict { PACKAGE_PIN AD9 IOSTANDARD LVDS } [get_ports { fmc_la_n[26] }]; #IO_L1N_T0L_N1_DBC_64 Sch=fmc_la_n[26]
|
||||
#set_property -dict { PACKAGE_PIN AC9 IOSTANDARD LVDS } [get_ports { fmc_la_p[26] }]; #IO_L1P_T0L_N0_DBC_64 Sch=fmc_la_p[26]
|
||||
#set_property -dict { PACKAGE_PIN AH4 IOSTANDARD LVDS } [get_ports { fmc_la_n[27] }]; #IO_L19N_T3L_N1_DBC_AD9N_64 Sch=fmc_la_n[27]
|
||||
#set_property -dict { PACKAGE_PIN AG4 IOSTANDARD LVDS } [get_ports { fmc_la_p[27] }]; #IO_L19P_T3L_N0_DBC_AD9P_64 Sch=fmc_la_p[27]
|
||||
#set_property -dict { PACKAGE_PIN AE8 IOSTANDARD LVDS } [get_ports { fmc_la_n[28] }]; #IO_L2N_T0L_N3_64 Sch=fmc_la_n[28]
|
||||
#set_property -dict { PACKAGE_PIN AE9 IOSTANDARD LVDS } [get_ports { fmc_la_p[28] }]; #IO_L2P_T0L_N2_64 Sch=fmc_la_p[28]
|
||||
#set_property -dict { PACKAGE_PIN AH7 IOSTANDARD LVDS } [get_ports { fmc_la_n[29] }]; #IO_L9N_T1L_N5_AD12N_64 Sch=fmc_la_n[29]
|
||||
#set_property -dict { PACKAGE_PIN AH8 IOSTANDARD LVDS } [get_ports { fmc_la_p[29] }]; #IO_L9P_T1L_N4_AD12P_64 Sch=fmc_la_p[29]
|
||||
#set_property -dict { PACKAGE_PIN AC7 IOSTANDARD LVDS } [get_ports { fmc_la_n[30] }]; #IO_L5N_T0U_N9_AD14N_64 Sch=fmc_la_n[30]
|
||||
#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVDS } [get_ports { fmc_la_p[30] }]; #IO_L5P_T0U_N8_AD14P_64 Sch=fmc_la_p[30]
|
||||
#set_property -dict { PACKAGE_PIN AG8 IOSTANDARD LVDS } [get_ports { fmc_la_n[31] }]; #IO_L8N_T1L_N3_AD5N_64 Sch=fmc_la_n[31]
|
||||
#set_property -dict { PACKAGE_PIN AF8 IOSTANDARD LVDS } [get_ports { fmc_la_p[31] }]; #IO_L8P_T1L_N2_AD5P_64 Sch=fmc_la_p[31]
|
||||
#set_property -dict { PACKAGE_PIN AC2 IOSTANDARD LVDS } [get_ports { fmc_la_n[32] }]; #IO_L14N_T2L_N3_GC_64 Sch=fmc_la_n[32]
|
||||
#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD LVDS } [get_ports { fmc_la_p[32] }]; #IO_L14P_T2L_N2_GC_64 Sch=fmc_la_p[32]
|
||||
#set_property -dict { PACKAGE_PIN AC6 IOSTANDARD LVDS } [get_ports { fmc_la_n[33] }]; #IO_L6N_T0U_N11_AD6N_64 Sch=fmc_la_n[33]
|
||||
#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVDS } [get_ports { fmc_la_p[33] }]; #IO_L6P_T0U_N10_AD6P_64 Sch=fmc_la_p[33]
|
||||
|
||||
#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { fmc_prsntn_m2c }]; #IO_L11N_AD9N_44/24
|
||||
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y168/PAD]
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y116/PAD]
|
||||
|
||||
#set_property IOSTANDARD ANALOG [get_ports Vp_Vn_0_v_p]
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,272 @@
|
||||
#### This file is a general .xdc for the Genesys ZU-5EV Rev. D
|
||||
#### To use it in a project:
|
||||
#### - uncomment the lines corresponding to used pins
|
||||
#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
#set_property DCI_CASCADE {64} [get_iobanks 65]
|
||||
|
||||
## Crypto
|
||||
#set_property -dict { PACKAGE_PIN AD15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L5P_HDGC_44/24 Sch=crypto_sda
|
||||
|
||||
# Sysclk is a 125 MHz PL reference clock generated by the external Ethernet PHY
|
||||
# It connects to an HDGC pin, so it has direct connection only to BUFG primitives.
|
||||
# When using it as input clock to CMT primitives (MMCM/PLL), it needs to go through
|
||||
# BUFG first. Choose "Global Buffer" in Clocking Wizard IP customization.
|
||||
# Might need CLOCK_DEDICATED_ROUTE FALSE
|
||||
#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS18 } [get_ports { sysclk }];
|
||||
|
||||
## MIPI A Port
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS12 } [get_ports { mipi_a_pwup_ls }]; #IO_L22N_T3U_N7_DBC_AD0N_66 Sch=mipi_a_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN G1 [get_ports mipi_a_clk_p] #IO_L1P_T0L_N0_DBC_66 Sch=mipi_a_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_n]
|
||||
##set_property PACKAGE_PIN E1 [get_ports mipi_a_lane_p[0]] #IO_L2P_T0L_N2_66 Sch=mipi_a_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[0]]
|
||||
##set_property PACKAGE_PIN F2 [get_ports mipi_a_lane_p[1]] #IO_L3P_T0L_N4_AD15P_66 Sch=mipi_a_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[1]]]
|
||||
|
||||
## MIPI B Port
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS12 } [get_ports { mipi_b_pwup_ls }]; #IO_L23P_T3U_N8_66 Sch=mipi_b_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN B5 [get_ports mipi_b_clk_p] #IO_L19P_T3L_N0_DBC_AD9P_66 Sch=mipi_b_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_n]
|
||||
##set_property PACKAGE_PIN C6 [get_ports mipi_b_lane_p[0]] #IO_L20P_T3L_N2_AD1P_66 Sch=mipi_b_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[0]]
|
||||
##set_property PACKAGE_PIN A7 [get_ports mipi_b_lane_p[1]] #IO_L21P_T3L_N4_AD8P_66 Sch=mipi_b_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[1]]
|
||||
|
||||
## Audio CODEC I2S, I2C
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L11N_AD9N_45/25 Sch=aud_scl
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS18 } [get_ports { aud_sda_io }]; #IO_L12P_AD8P_45/25 Sch=aud_sda
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_AD10N_45/25 Sch=aud_lrclk
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L12N_AD8N_45/25 Sch=aud_bclk
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L9P_AD11P_45/25 Sch=aud_mclk
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L10P_AD10P_45/25 Sch=aud_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L8N_HDGC_45/25 Sch=aud_dac_sdata
|
||||
|
||||
## PMOD XADC
|
||||
## Commented because pins are contrained by System Management Wizard. Only >2018.2 lets us select bank 43.
|
||||
#set_property -dict { PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_n }]; #IO_L10N_AD2N_43/44 Sch=ja1_r_n
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_p }]; #IO_L10P_AD2P_43/44 Sch=ja1_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_n }]; #IO_L9N_AD3N_43/44 Sch=ja2_r_n
|
||||
#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_p }]; #IO_L9P_AD3P_43/44 Sch=ja2_r_p
|
||||
#set_property -dict { PACKAGE_PIN AB9 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_n }]; #IO_L12N_AD0N_43/44 Sch=ja3_r_n
|
||||
#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_p }]; #IO_L12P_AD0P_43/44 Sch=ja3_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_n }]; #IO_L11N_AD1N_43/44 Sch=ja4_r_n
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_p }]; #IO_L11P_AD1P_43/44 Sch=ja4_r_p
|
||||
|
||||
## Platform MCU signals
|
||||
#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[0] }]; #IO_L6P_HDGC_44/24 Sch=vadj_level[0]
|
||||
#set_property -dict { PACKAGE_PIN AC13 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[1] }]; #IO_L6N_HDGC_44/24 Sch=vadj_level[1]
|
||||
#set_property -dict { PACKAGE_PIN G10 IOSTANDARD LVCMOS18 } [get_ports { vadj_auton }]; #IO_L3N_AD13N_45/25 Sch=vadj_auton
|
||||
#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_detectedn }]; #IO_L3P_AD13P_45/25 Sch=syzygy_detectedn
|
||||
|
||||
##DisplayPort AUX channel over EMIO
|
||||
#set_property -dict { PACKAGE_PIN K12 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_din }]; #IO_L2N_AD14N_45/25 Sch=dp_aux_din
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_doe }]; #IO_L2P_AD14P_45/25 Sch=dp_aux_doe
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_dout }]; #IO_L1P_AD15P_45/25 Sch=dp_aux_dout
|
||||
#set_property -dict { PACKAGE_PIN J10 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_hotplug_detect }]; #IO_L1N_AD15N_45/25 Sch=dp_aux_hotplug_detect
|
||||
|
||||
## Mini PCIe Auxiliary
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { pcie_w_disable2n }]; #IO_L12P_AD8P_44/24 Sch=pcie_w_disable2n
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS12 } [get_ports { pcie_w_disable[1] }]; #IO_L9P_T1L_N4_AD12P_66 Sch=pcie_w_disable[1]
|
||||
|
||||
## USB 2.0 Overcurrent EMIO
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS12 PULLUP true } [get_ports { usb20_ocn }];#IO_L18N_T2U_N11_AD2N_66 Sch=usb20_ocn
|
||||
|
||||
## Ethernet JTAG
|
||||
#set_property -dict { PACKAGE_PIN F7 LVCMOS12 } [get_ports { eth_tms_ls }]; #IO_L16N_T2U_N7_QBC_AD3N_66 Sch=eth_tms_ls
|
||||
#set_property -dict { PACKAGE_PIN F8 LVCMOS12 } [get_ports { eth_tdi_ls }]; #IO_L17P_T2U_N8_AD10P_66 Sch=eth_tdi_ls
|
||||
#set_property -dict { PACKAGE_PIN E8 LVCMOS12 } [get_ports { eth_tck_ls }]; #IO_L17N_T2U_N9_AD10N_66 Sch=eth_tck_ls
|
||||
#set_property -dict { PACKAGE_PIN E9 LVCMOS12 } [get_ports { eth_tdo_ls }]; #IO_L18P_T2U_N10_AD2P_66 Sch=eth_tdo_ls
|
||||
|
||||
## PMOD JB
|
||||
#set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8N_HDGC_AD4N_46/26 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN AG14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L2N_AD10N_46/26 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_AD11P_46/26 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN AG13 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L8P_HDGC_AD4P_46/26 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6P_HDGC_AD6P_46/26 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN AF13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L2P_AD10P_46/26 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L5P_HDGC_AD7P_46/26 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN AH13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L1N_AD11N_46/26 Sch=jb[10]
|
||||
|
||||
## PMOD JC
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L6N_HDGC_AD6N_46/26 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L7P_HDGC_AD5P_46/26 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L3P_AD9P_46/26 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L5N_HDGC_AD7N_46/26 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L7N_HDGC_AD5N_46/26 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L4N_AD8N_46/26 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L4P_AD8P_46/26 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L3N_AD9N_46/26 Sch=jc[10]
|
||||
|
||||
## PMOD JD
|
||||
#set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L4P_AD12P_44/24 Sch=jd[1]
|
||||
#set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L2P_AD14P_44/24 Sch=jd[2]
|
||||
#set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L2N_AD14N_44/24 Sch=jd[3]
|
||||
#set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L3P_AD13P_44/24 Sch=jd[4]
|
||||
#set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L1N_AD15N_44/24 Sch=jd[7]
|
||||
#set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L4N_AD12N_44/24 Sch=jd[8]
|
||||
#set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L1P_AD15P_44/24 Sch=jd[9]
|
||||
#set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L3N_AD13N_44/24 Sch=jd[10]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN B10 IOSTANDARD LVCMOS18 } [get_ports { btn[2] }]; #IO_L9N_AD11N_45/25 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports { btn[3] }]; #IO_L4N_AD12N_45/25 Sch=btn[3]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS18 } [get_ports { btn[4] }]; #IO_L4P_AD12P_45/25 Sch=btn[4]
|
||||
#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS18 } [get_ports { btn[5] }]; #IO_L6P_HDGC_45/25 Sch=btn[5]
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS18 } [get_ports { btn[6] }]; #IO_L11P_AD9P_45/25 Sch=btn[6]
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L8N_HDGC_44/24 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L10N_AD10N_44/24 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L11P_AD9P_44/24 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L8P_HDGC_44/24 Sch=sw[3]
|
||||
|
||||
## LED
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ld[0] }]; #IO_L12P_AD0P_46/26 Sch=ld[1]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { ld[1] }]; #IO_L12N_AD0N_46/26 Sch=ld[2]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ld[2] }]; #IO_L11P_AD1P_46/26 Sch=ld[3]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ld[3] }]; #IO_L11N_AD1N_46/26 Sch=ld[4]
|
||||
|
||||
## RGB LED
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS12 } [get_ports { ld5_b }]; #IO_L23N_T3U_N9_66 Sch=ld5_b
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS12 } [get_ports { ld5_g }]; #IO_L24N_T3U_N11_66 Sch=ld5_g
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS12 } [get_ports { ld5_r }]; #IO_L24P_T3U_N10_66 Sch=ld5_r
|
||||
|
||||
## GTH reference clock jitter filter auxiliary
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS12 } [get_ports { clkgth_intrn_ls }]; #IO_L11N_T1U_N9_GC_66 Sch=clkgth_intrn_ls
|
||||
#set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS12 } [get_ports { clkgth_loln_ls }]; #IO_L13N_T2L_N1_GC_QBC_66 Sch=clkgth_loln_ls
|
||||
#set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS12 } [get_ports { clkgth_rst }]; #IO_L16P_T2U_N6_QBC_AD3P_66 Sch=clkgth_rst
|
||||
|
||||
## MUX I2C
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS12 } [get_ports { fpga_mux_rst }]; #IO_L15N_T2L_N5_AD11N_66 Sch=fpga_mux_rst
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_scl_ls }]; #IO_L9P_AD3P_46/26 Sch=mux_scl_ls
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_sda_ls }]; #IO_L9N_AD3N_46/26 Sch=mux_sda_ls
|
||||
|
||||
## SYZYGY
|
||||
#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[0] }]; #IO_L18P_T2U_N10_AD2P_64 Sch=syzygy_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AE2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[1] }]; #IO_L22P_T3U_N6_DBC_AD0P_64 Sch=syzygy_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AE3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[2] }]; #IO_L21P_T3L_N4_AD8P_64 Sch=syzygy_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AE5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[3] }]; #IO_L12P_T1U_N10_GC_64 Sch=syzygy_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN AD7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[4] }]; #IO_L4P_T0U_N6_DBC_AD7P_64 Sch=syzygy_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN AG6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[5] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=syzygy_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[6] }]; #IO_L3P_T0L_N4_AD15P_65 Sch=syzygy_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[7] }]; #IO_L2P_T0L_N2_65 Sch=syzygy_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN AC1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[0] }]; #IO_L18P_T2U_N11_AD2P_64 Sch=syzygy_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AF2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[1] }]; #IO_L22P_T3U_N7_DBC_AD0P_64 Sch=syzygy_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AF3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[2] }]; #IO_L21P_T3L_N5_AD8P_64 Sch=syzygy_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AF5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[3] }]; #IO_L12P_T1U_N11_GC_64 Sch=syzygy_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AE7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[4] }]; #IO_L4P_T0U_N7_DBC_AD7P_64 Sch=syzygy_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN AG5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[5] }]; #IO_L10P_T1U_N7_QBC_AD4P_64 Sch=syzygy_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[6] }]; #IO_L3P_T0L_N5_AD15P_65 Sch=syzygy_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[7] }]; #IO_L2P_T0L_N3_65 Sch=syzygy_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L4P_AD8P_43/44 Sch=syzygy_s[16]
|
||||
#set_property -dict { PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L6P_HDGC_AD6P_43/44 Sch=syzygy_s[17]
|
||||
#set_property -dict { PACKAGE_PIN AF10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L4N_AD8N_43/44 Sch=syzygy_s[18]
|
||||
#set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L6N_HDGC_AD6N_43/44 Sch=syzygy_s[19]
|
||||
#set_property -dict { PACKAGE_PIN AF11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L2P_AD10P_43/44 Sch=syzygy_s[20]
|
||||
#set_property -dict { PACKAGE_PIN AE12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L5P_HDGC_AD7P_43/44 Sch=syzygy_s[21]
|
||||
#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L5N_HDGC_AD7N_43/44 Sch=syzygy_s[22]
|
||||
#set_property -dict { PACKAGE_PIN AH12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L3P_AD9P_43/44 Sch=syzygy_s[23]
|
||||
#set_property -dict { PACKAGE_PIN AG11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L2N_AD10N_43/44 Sch=syzygy_s[24]
|
||||
#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L1P_AD11P_43/44 Sch=syzygy_s[25]
|
||||
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L3N_AD9N_43/44 Sch=syzygy_s[26]
|
||||
#set_property -dict { PACKAGE_PIN AH10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L1N_AD11N_43/44 Sch=syzygy_s[27]
|
||||
#set_property -dict { PACKAGE_PIN AD4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_n }]; #IO_L13N_T2L_N1_GC_QBC_64 Sch=syzygy_in_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AD5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_p }]; #IO_L13P_T2L_N0_GC_QBC_64 Sch=syzygy_in_clk_p
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_n }]; #IO_L1N_T0L_N1_DBC_65 Sch=syzygy_out_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_p }]; #IO_L1P_T0L_N0_DBC_65 Sch=syzygy_out_clk_p
|
||||
|
||||
## FMC connector
|
||||
#set_property -dict { PACKAGE_PIN M6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk0_m2c_p }]; #IO_L14P_T2L_N2_GC_65 Sch=fmc_clk0_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk1_m2c_p }]; #IO_L12P_T1U_N10_GC_65 Sch=fmc_clk1_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L6 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2L_N1_GC_QBC_65 Sch=fmc_la00_cc_n
|
||||
#set_property -dict { PACKAGE_PIN L7 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2L_N0_GC_QBC_65 Sch=fmc_la00_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_n }]; #IO_L7N_T1L_N1_QBC_AD13N_65 Sch=fmc_la01_cc_n
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_p }]; #IO_L7P_T1L_N0_QBC_AD13P_65 Sch=fmc_la01_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVDS } [get_ports { fmc_la_n[02] }]; #IO_L20N_T3L_N3_AD1N_65 Sch=fmc_la_n[02]
|
||||
#set_property -dict { PACKAGE_PIN J6 IOSTANDARD LVDS } [get_ports { fmc_la_p[02] }]; #IO_L20P_T3L_N2_AD1P_65 Sch=fmc_la_p[02]
|
||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVDS } [get_ports { fmc_la_n[03] }]; #IO_L11N_T1U_N9_GC_65 Sch=fmc_la_n[03]
|
||||
#set_property -dict { PACKAGE_PIN K4 IOSTANDARD LVDS } [get_ports { fmc_la_p[03] }]; #IO_L11P_T1U_N8_GC_65 Sch=fmc_la_p[03]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVDS } [get_ports { fmc_la_n[04] }]; #IO_L9N_T1L_N5_AD12N_65 Sch=fmc_la_n[04]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVDS } [get_ports { fmc_la_p[04] }]; #IO_L9P_T1L_N4_AD12P_65 Sch=fmc_la_p[04]
|
||||
#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVDS } [get_ports { fmc_la_n[05] }]; #IO_L6N_T0U_N11_AD6N_65 Sch=fmc_la_n[05]
|
||||
#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVDS } [get_ports { fmc_la_p[05] }]; #IO_L6P_T0U_N10_AD6P_65 Sch=fmc_la_p[05]
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVDS } [get_ports { fmc_la_n[06] }]; #IO_L17N_T2U_N9_AD10N_65 Sch=fmc_la_n[06]
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVDS } [get_ports { fmc_la_p[06] }]; #IO_L17P_T2U_N8_AD10P_65 Sch=fmc_la_p[06]
|
||||
#set_property -dict { PACKAGE_PIN J9 IOSTANDARD LVDS } [get_ports { fmc_la_n[07] }]; #IO_L23N_T3U_N9_65 Sch=fmc_la_n[07]
|
||||
#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVDS } [get_ports { fmc_la_p[07] }]; #IO_L23P_T3U_N8_I2C_SCLK_65 Sch=fmc_la_p[07]
|
||||
#set_property -dict { PACKAGE_PIN T7 IOSTANDARD LVDS } [get_ports { fmc_la_n[08] }]; #IO_L5N_T0U_N9_AD14N_65 Sch=fmc_la_n[08]
|
||||
#set_property -dict { PACKAGE_PIN R7 IOSTANDARD LVDS } [get_ports { fmc_la_p[08] }]; #IO_L5P_T0U_N8_AD14P_65 Sch=fmc_la_p[08]
|
||||
#set_property -dict { PACKAGE_PIN L8 IOSTANDARD LVDS } [get_ports { fmc_la_n[09] }]; #IO_L18N_T2U_N11_AD2N_65 Sch=fmc_la_n[09]
|
||||
#set_property -dict { PACKAGE_PIN M8 IOSTANDARD LVDS } [get_ports { fmc_la_p[09] }]; #IO_L18P_T2U_N10_AD2P_65 Sch=fmc_la_p[09]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVDS } [get_ports { fmc_la_n[10] }]; #IO_L8N_T1L_N3_AD5N_65 Sch=fmc_la_n[10]
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVDS } [get_ports { fmc_la_p[10] }]; #IO_L8P_T1L_N2_AD5P_65 Sch=fmc_la_p[10]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVDS } [get_ports { fmc_la_n[11] }]; #IO_L19N_T3L_N1_DBC_AD9N_65 Sch=fmc_la_n[11]
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVDS } [get_ports { fmc_la_p[11] }]; #IO_L19P_T3L_N0_DBC_AD9P_65 Sch=fmc_la_p[11]
|
||||
#set_property -dict { PACKAGE_PIN H7 IOSTANDARD LVDS } [get_ports { fmc_la_n[12] }]; #IO_L21N_T3L_N5_AD8N_65 Sch=fmc_la_n[12]
|
||||
#set_property -dict { PACKAGE_PIN J7 IOSTANDARD LVDS } [get_ports { fmc_la_p[12] }]; #IO_L21P_T3L_N4_AD8P_65 Sch=fmc_la_p[12]
|
||||
#set_property -dict { PACKAGE_PIN N6 IOSTANDARD LVDS } [get_ports { fmc_la_n[13] }]; #IO_L15N_T2L_N5_AD11N_65 Sch=fmc_la_n[13]
|
||||
#set_property -dict { PACKAGE_PIN N7 IOSTANDARD LVDS } [get_ports { fmc_la_p[13] }]; #IO_L15P_T2L_N4_AD11P_65 Sch=fmc_la_p[13]
|
||||
#set_property -dict { PACKAGE_PIN P6 IOSTANDARD LVDS } [get_ports { fmc_la_n[14] }]; #IO_L16N_T2U_N7_QBC_AD3N_65 Sch=fmc_la_n[14]
|
||||
#set_property -dict { PACKAGE_PIN P7 IOSTANDARD LVDS } [get_ports { fmc_la_p[14] }]; #IO_L16P_T2U_N6_QBC_AD3P_65 Sch=fmc_la_p[14]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVDS } [get_ports { fmc_la_n[15] }]; #IO_L4N_T0U_N7_DBC_AD7N_65 Sch=fmc_la_n[15]
|
||||
#set_property -dict { PACKAGE_PIN R8 IOSTANDARD LVDS } [get_ports { fmc_la_p[15] }]; #IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 Sch=fmc_la_p[15]
|
||||
#set_property -dict { PACKAGE_PIN K7 IOSTANDARD LVDS } [get_ports { fmc_la_n[16] }]; #IO_L22N_T3U_N7_DBC_AD0N_65 Sch=fmc_la_n[16]
|
||||
#set_property -dict { PACKAGE_PIN K8 IOSTANDARD LVDS } [get_ports { fmc_la_p[16] }]; #IO_L22P_T3U_N6_DBC_AD0P_65 Sch=fmc_la_p[16]
|
||||
#set_property -dict { PACKAGE_PIN AD1 IOSTANDARD LVDS } [get_ports { fmc_la_n[17] }]; #IO_L16N_T2U_N7_QBC_AD3N_64 Sch=fmc_la17_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AD2 IOSTANDARD LVDS } [get_ports { fmc_la_p[17] }]; #IO_L16P_T2U_N6_QBC_AD3P_64 Sch=fmc_la17_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AH9 IOSTANDARD LVDS } [get_ports { fmc_la_n[18] }]; #IO_L10N_T1U_N7_QBC_AD4N_64 Sch=fmc_la18_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AG9 IOSTANDARD LVDS } [get_ports { fmc_la_p[18] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=fmc_la18_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AC3 IOSTANDARD LVDS } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2U_N9_AD10N_64 Sch=fmc_la_n[19]
|
||||
#set_property -dict { PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2U_N8_AD10P_64 Sch=fmc_la_p[19]
|
||||
#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD LVDS } [get_ports { fmc_la_n[20] }]; #IO_L15N_T2L_N5_AD11N_64 Sch=fmc_la_n[20]
|
||||
#set_property -dict { PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports { fmc_la_p[20] }]; #IO_L15P_T2L_N4_AD11P_64 Sch=fmc_la_p[20]
|
||||
#set_property -dict { PACKAGE_PIN AG1 IOSTANDARD LVDS } [get_ports { fmc_la_n[21] }]; #IO_L24N_T3U_N11_64 Sch=fmc_la_n[21]
|
||||
#set_property -dict { PACKAGE_PIN AF1 IOSTANDARD LVDS } [get_ports { fmc_la_p[21] }]; #IO_L24P_T3U_N10_64 Sch=fmc_la_p[21]
|
||||
#set_property -dict { PACKAGE_PIN AC8 IOSTANDARD LVDS } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0L_N5_AD15N_64 Sch=fmc_la_n[22]
|
||||
#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVDS } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0L_N4_AD15P_64 Sch=fmc_la_p[22]
|
||||
#set_property -dict { PACKAGE_PIN AH1 IOSTANDARD LVDS } [get_ports { fmc_la_n[23] }]; #IO_L23N_T3U_N9_64 Sch=fmc_la_n[23]
|
||||
#set_property -dict { PACKAGE_PIN AH2 IOSTANDARD LVDS } [get_ports { fmc_la_p[23] }]; #IO_L23P_T3U_N8_64 Sch=fmc_la_p[23]
|
||||
#set_property -dict { PACKAGE_PIN AF6 IOSTANDARD LVDS } [get_ports { fmc_la_n[24] }]; #IO_L11N_T1U_N9_GC_64 Sch=fmc_la_n[24]
|
||||
#set_property -dict { PACKAGE_PIN AF7 IOSTANDARD LVDS } [get_ports { fmc_la_p[24] }]; #IO_L11P_T1U_N8_GC_64 Sch=fmc_la_p[24]
|
||||
#set_property -dict { PACKAGE_PIN AH3 IOSTANDARD LVDS } [get_ports { fmc_la_n[25] }]; #IO_L20N_T3L_N3_AD1N_64 Sch=fmc_la_n[25]
|
||||
#set_property -dict { PACKAGE_PIN AG3 IOSTANDARD LVDS } [get_ports { fmc_la_p[25] }]; #IO_L20P_T3L_N2_AD1P_64 Sch=fmc_la_p[25]
|
||||
#set_property -dict { PACKAGE_PIN AD9 IOSTANDARD LVDS } [get_ports { fmc_la_n[26] }]; #IO_L1N_T0L_N1_DBC_64 Sch=fmc_la_n[26]
|
||||
#set_property -dict { PACKAGE_PIN AC9 IOSTANDARD LVDS } [get_ports { fmc_la_p[26] }]; #IO_L1P_T0L_N0_DBC_64 Sch=fmc_la_p[26]
|
||||
#set_property -dict { PACKAGE_PIN AH4 IOSTANDARD LVDS } [get_ports { fmc_la_n[27] }]; #IO_L19N_T3L_N1_DBC_AD9N_64 Sch=fmc_la_n[27]
|
||||
#set_property -dict { PACKAGE_PIN AG4 IOSTANDARD LVDS } [get_ports { fmc_la_p[27] }]; #IO_L19P_T3L_N0_DBC_AD9P_64 Sch=fmc_la_p[27]
|
||||
#set_property -dict { PACKAGE_PIN AE8 IOSTANDARD LVDS } [get_ports { fmc_la_n[28] }]; #IO_L2N_T0L_N3_64 Sch=fmc_la_n[28]
|
||||
#set_property -dict { PACKAGE_PIN AE9 IOSTANDARD LVDS } [get_ports { fmc_la_p[28] }]; #IO_L2P_T0L_N2_64 Sch=fmc_la_p[28]
|
||||
#set_property -dict { PACKAGE_PIN AH7 IOSTANDARD LVDS } [get_ports { fmc_la_n[29] }]; #IO_L9N_T1L_N5_AD12N_64 Sch=fmc_la_n[29]
|
||||
#set_property -dict { PACKAGE_PIN AH8 IOSTANDARD LVDS } [get_ports { fmc_la_p[29] }]; #IO_L9P_T1L_N4_AD12P_64 Sch=fmc_la_p[29]
|
||||
#set_property -dict { PACKAGE_PIN AC7 IOSTANDARD LVDS } [get_ports { fmc_la_n[30] }]; #IO_L5N_T0U_N9_AD14N_64 Sch=fmc_la_n[30]
|
||||
#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVDS } [get_ports { fmc_la_p[30] }]; #IO_L5P_T0U_N8_AD14P_64 Sch=fmc_la_p[30]
|
||||
#set_property -dict { PACKAGE_PIN AG8 IOSTANDARD LVDS } [get_ports { fmc_la_n[31] }]; #IO_L8N_T1L_N3_AD5N_64 Sch=fmc_la_n[31]
|
||||
#set_property -dict { PACKAGE_PIN AF8 IOSTANDARD LVDS } [get_ports { fmc_la_p[31] }]; #IO_L8P_T1L_N2_AD5P_64 Sch=fmc_la_p[31]
|
||||
#set_property -dict { PACKAGE_PIN AC2 IOSTANDARD LVDS } [get_ports { fmc_la_n[32] }]; #IO_L14N_T2L_N3_GC_64 Sch=fmc_la_n[32]
|
||||
#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD LVDS } [get_ports { fmc_la_p[32] }]; #IO_L14P_T2L_N2_GC_64 Sch=fmc_la_p[32]
|
||||
#set_property -dict { PACKAGE_PIN AC6 IOSTANDARD LVDS } [get_ports { fmc_la_n[33] }]; #IO_L6N_T0U_N11_AD6N_64 Sch=fmc_la_n[33]
|
||||
#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVDS } [get_ports { fmc_la_p[33] }]; #IO_L6P_T0U_N10_AD6P_64 Sch=fmc_la_p[33]
|
||||
|
||||
#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { fmc_prsntn_m2c }]; #IO_L11N_AD9N_44/24
|
||||
|
||||
## Power-good input for VADJ supply rail
|
||||
#set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS33 } [get_ports { pg_vadj_r }]; #IO_L12N_AD8N_44/24 Sch=pg_vadj_r
|
||||
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y168/PAD]
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y116/PAD]
|
||||
|
||||
#set_property IOSTANDARD ANALOG [get_ports Vp_Vn_0_v_p]
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2017 Digilent
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
@@ -0,0 +1,265 @@
|
||||
## This file is a general .xdc for the Nexys4 DDR Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
|
||||
|
||||
|
||||
##Switches
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
|
||||
## LEDs
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
|
||||
##7 segment display
|
||||
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||
|
||||
|
||||
##VGA Connector
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
|
||||
|
||||
##Micro SD Connector
|
||||
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||
|
||||
|
||||
##Accelerometer
|
||||
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||
|
||||
|
||||
##Temperature Sensor
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||
|
||||
##Omnidirectional Microphone
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
|
||||
|
||||
|
||||
##PWM Audio Amplifier
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,722 @@
|
||||
## This file is a general .xdc for the Nexys4 rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
|
||||
#set_property PACKAGE_PIN E3 [get_ports clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
## Switches
|
||||
##Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0
|
||||
#set_property PACKAGE_PIN U9 [get_ports {sw[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
|
||||
##Bank = 34, Pin name = IO_25_34, Sch name = SW1
|
||||
#set_property PACKAGE_PIN U8 [get_ports {sw[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
|
||||
##Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2
|
||||
#set_property PACKAGE_PIN R7 [get_ports {sw[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
|
||||
##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3
|
||||
#set_property PACKAGE_PIN R6 [get_ports {sw[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
|
||||
##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4
|
||||
#set_property PACKAGE_PIN R5 [get_ports {sw[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
|
||||
##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5
|
||||
#set_property PACKAGE_PIN V7 [get_ports {sw[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
|
||||
##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6
|
||||
#set_property PACKAGE_PIN V6 [get_ports {sw[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
|
||||
##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7
|
||||
#set_property PACKAGE_PIN V5 [get_ports {sw[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
|
||||
##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8
|
||||
#set_property PACKAGE_PIN U4 [get_ports {sw[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
|
||||
##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9
|
||||
#set_property PACKAGE_PIN V2 [get_ports {sw[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
|
||||
##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10
|
||||
#set_property PACKAGE_PIN U2 [get_ports {sw[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
|
||||
##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11
|
||||
#set_property PACKAGE_PIN T3 [get_ports {sw[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
|
||||
##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12
|
||||
#set_property PACKAGE_PIN T1 [get_ports {sw[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
|
||||
##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13
|
||||
#set_property PACKAGE_PIN R3 [get_ports {sw[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
|
||||
##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14
|
||||
#set_property PACKAGE_PIN P3 [get_ports {sw[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
|
||||
##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15
|
||||
#set_property PACKAGE_PIN P4 [get_ports {sw[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
|
||||
|
||||
|
||||
|
||||
## LEDs
|
||||
##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0
|
||||
#set_property PACKAGE_PIN T8 [get_ports {led[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
|
||||
##Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1
|
||||
#set_property PACKAGE_PIN V9 [get_ports {led[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
|
||||
##Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2
|
||||
#set_property PACKAGE_PIN R8 [get_ports {led[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
|
||||
##Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3
|
||||
#set_property PACKAGE_PIN T6 [get_ports {led[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
|
||||
##Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4
|
||||
#set_property PACKAGE_PIN T5 [get_ports {led[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
|
||||
##Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5
|
||||
#set_property PACKAGE_PIN T4 [get_ports {led[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
|
||||
##Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6
|
||||
#set_property PACKAGE_PIN U7 [get_ports {led[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
|
||||
##Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7
|
||||
#set_property PACKAGE_PIN U6 [get_ports {led[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
|
||||
##Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8
|
||||
#set_property PACKAGE_PIN V4 [get_ports {led[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
|
||||
##Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9
|
||||
#set_property PACKAGE_PIN U3 [get_ports {led[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
|
||||
##Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10
|
||||
#set_property PACKAGE_PIN V1 [get_ports {led[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
|
||||
##Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11
|
||||
#set_property PACKAGE_PIN R1 [get_ports {led[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
|
||||
##Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12
|
||||
#set_property PACKAGE_PIN P5 [get_ports {led[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
|
||||
##Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13
|
||||
#set_property PACKAGE_PIN U1 [get_ports {led[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
|
||||
##Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14
|
||||
#set_property PACKAGE_PIN R2 [get_ports {led[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
|
||||
##Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15
|
||||
#set_property PACKAGE_PIN P2 [get_ports {led[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
|
||||
|
||||
##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R
|
||||
#set_property PACKAGE_PIN K5 [get_ports RGB1_Red]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Red]
|
||||
##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G
|
||||
#set_property PACKAGE_PIN F13 [get_ports RGB1_Green]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Green]
|
||||
##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B
|
||||
#set_property PACKAGE_PIN F6 [get_ports RGB1_Blue]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Blue]
|
||||
##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R
|
||||
#set_property PACKAGE_PIN K6 [get_ports RGB2_Red]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Red]
|
||||
##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G
|
||||
#set_property PACKAGE_PIN H6 [get_ports RGB2_Green]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Green]
|
||||
##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B
|
||||
#set_property PACKAGE_PIN L16 [get_ports RGB2_Blue]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Blue]
|
||||
|
||||
|
||||
|
||||
##7 segment display
|
||||
##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA
|
||||
#set_property PACKAGE_PIN L3 [get_ports {seg[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
|
||||
##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB
|
||||
#set_property PACKAGE_PIN N1 [get_ports {seg[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
|
||||
##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC
|
||||
#set_property PACKAGE_PIN L5 [get_ports {seg[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
|
||||
##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD
|
||||
#set_property PACKAGE_PIN L4 [get_ports {seg[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
|
||||
##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE
|
||||
#set_property PACKAGE_PIN K3 [get_ports {seg[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
|
||||
##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF
|
||||
#set_property PACKAGE_PIN M2 [get_ports {seg[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
|
||||
##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG
|
||||
#set_property PACKAGE_PIN L6 [get_ports {seg[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
|
||||
|
||||
##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP
|
||||
#set_property PACKAGE_PIN M4 [get_ports dp]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
|
||||
|
||||
##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0
|
||||
#set_property PACKAGE_PIN N6 [get_ports {an[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
|
||||
##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1
|
||||
#set_property PACKAGE_PIN M6 [get_ports {an[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
|
||||
##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2
|
||||
#set_property PACKAGE_PIN M3 [get_ports {an[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
|
||||
##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3
|
||||
#set_property PACKAGE_PIN N5 [get_ports {an[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
|
||||
##Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4
|
||||
#set_property PACKAGE_PIN N2 [get_ports {an[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}]
|
||||
##Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5
|
||||
#set_property PACKAGE_PIN N4 [get_ports {an[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}]
|
||||
##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6
|
||||
#set_property PACKAGE_PIN L1 [get_ports {an[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}]
|
||||
##Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7
|
||||
#set_property PACKAGE_PIN M1 [get_ports {an[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}]
|
||||
|
||||
|
||||
|
||||
##Buttons
|
||||
##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET
|
||||
#set_property PACKAGE_PIN C12 [get_ports btnCpuReset]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnCpuReset]
|
||||
##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC
|
||||
#set_property PACKAGE_PIN E16 [get_ports btnC]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
|
||||
##Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU
|
||||
#set_property PACKAGE_PIN F15 [get_ports btnU]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
|
||||
##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL
|
||||
#set_property PACKAGE_PIN T16 [get_ports btnL]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
|
||||
##Bank = 14, Pin name = IO_25_14, Sch name = BTNR
|
||||
#set_property PACKAGE_PIN R10 [get_ports btnR]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
|
||||
##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND
|
||||
#set_property PACKAGE_PIN V10 [get_ports btnD]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1
|
||||
#set_property PACKAGE_PIN B13 [get_ports {JA[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
|
||||
##Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2
|
||||
#set_property PACKAGE_PIN F14 [get_ports {JA[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
|
||||
##Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3
|
||||
#set_property PACKAGE_PIN D17 [get_ports {JA[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
|
||||
##Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4
|
||||
#set_property PACKAGE_PIN E17 [get_ports {JA[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
|
||||
##Bank = 15, Pin name = IO_0_15, Sch name = JA7
|
||||
#set_property PACKAGE_PIN G13 [get_ports {JA[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
|
||||
##Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8
|
||||
#set_property PACKAGE_PIN C17 [get_ports {JA[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
|
||||
##Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9
|
||||
#set_property PACKAGE_PIN D18 [get_ports {JA[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
|
||||
##Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10
|
||||
#set_property PACKAGE_PIN E18 [get_ports {JA[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1
|
||||
#set_property PACKAGE_PIN G14 [get_ports {JB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
|
||||
##Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2
|
||||
#set_property PACKAGE_PIN P15 [get_ports {JB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
|
||||
##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3
|
||||
#set_property PACKAGE_PIN V11 [get_ports {JB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
|
||||
##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4
|
||||
#set_property PACKAGE_PIN V15 [get_ports {JB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
|
||||
##Bank = 15, Pin name = IO_25_15, Sch name = JB7
|
||||
#set_property PACKAGE_PIN K16 [get_ports {JB[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
|
||||
##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8
|
||||
#set_property PACKAGE_PIN R16 [get_ports {JB[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
|
||||
##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9
|
||||
#set_property PACKAGE_PIN T9 [get_ports {JB[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
|
||||
##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10
|
||||
#set_property PACKAGE_PIN U11 [get_ports {JB[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
##Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1
|
||||
#set_property PACKAGE_PIN K2 [get_ports {JC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
|
||||
##Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2
|
||||
#set_property PACKAGE_PIN E7 [get_ports {JC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
|
||||
##Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3
|
||||
#set_property PACKAGE_PIN J3 [get_ports {JC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
|
||||
##Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4
|
||||
#set_property PACKAGE_PIN J4 [get_ports {JC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
|
||||
##Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7
|
||||
#set_property PACKAGE_PIN K1 [get_ports {JC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
|
||||
##Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8
|
||||
#set_property PACKAGE_PIN E6 [get_ports {JC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
|
||||
##Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9
|
||||
#set_property PACKAGE_PIN J2 [get_ports {JC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
|
||||
##Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10
|
||||
#set_property PACKAGE_PIN G6 [get_ports {JC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
##Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1
|
||||
#set_property PACKAGE_PIN H4 [get_ports {JD[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}]
|
||||
##Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2
|
||||
#set_property PACKAGE_PIN H1 [get_ports {JD[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}]
|
||||
##Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3
|
||||
#set_property PACKAGE_PIN G1 [get_ports {JD[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}]
|
||||
##Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4
|
||||
#set_property PACKAGE_PIN G3 [get_ports {JD[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}]
|
||||
##Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7
|
||||
#set_property PACKAGE_PIN H2 [get_ports {JD[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}]
|
||||
##Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8
|
||||
#set_property PACKAGE_PIN G4 [get_ports {JD[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}]
|
||||
##Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9
|
||||
#set_property PACKAGE_PIN G2 [get_ports {JD[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}]
|
||||
##Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10
|
||||
#set_property PACKAGE_PIN F3 [get_ports {JD[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P
|
||||
#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
|
||||
##Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P
|
||||
#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
|
||||
##Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P
|
||||
#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
|
||||
##Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P
|
||||
#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
|
||||
##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N
|
||||
#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
|
||||
##Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N
|
||||
#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
|
||||
##Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N
|
||||
#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
|
||||
##Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N
|
||||
#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
|
||||
|
||||
|
||||
|
||||
##VGA Connector
|
||||
##Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0
|
||||
#set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
|
||||
##Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1
|
||||
#set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
|
||||
##Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2
|
||||
#set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
|
||||
##Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3
|
||||
#set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
|
||||
##Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0
|
||||
#set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
|
||||
##Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1
|
||||
#set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
|
||||
##Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2
|
||||
#set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
|
||||
##Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3
|
||||
#set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
|
||||
##Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0
|
||||
#set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
|
||||
##Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1
|
||||
#set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
|
||||
##Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2
|
||||
#set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
|
||||
##Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3
|
||||
#set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
|
||||
##Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS
|
||||
#set_property PACKAGE_PIN B11 [get_ports Hsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
|
||||
##Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_VS
|
||||
#set_property PACKAGE_PIN B12 [get_ports Vsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
|
||||
|
||||
|
||||
|
||||
##Micro SD Connector
|
||||
##Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET
|
||||
#set_property PACKAGE_PIN E2 [get_ports sdReset]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports sdReset]
|
||||
##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD
|
||||
#set_property PACKAGE_PIN A1 [get_ports sdCD]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports sdCD]
|
||||
##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK
|
||||
#set_property PACKAGE_PIN B1 [get_ports sdSCK]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports sdSCK]
|
||||
##Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD
|
||||
#set_property PACKAGE_PIN C1 [get_ports sdCmd]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports sdCmd]
|
||||
##Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0
|
||||
#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}]
|
||||
##Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1
|
||||
#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}]
|
||||
##Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2
|
||||
#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}]
|
||||
##Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3
|
||||
#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}]
|
||||
|
||||
|
||||
|
||||
##Accelerometer
|
||||
##Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO
|
||||
#set_property PACKAGE_PIN D13 [get_ports aclMISO]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclMISO]
|
||||
##Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI
|
||||
#set_property PACKAGE_PIN B14 [get_ports aclMOSI]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclMOSI]
|
||||
##Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK
|
||||
#set_property PACKAGE_PIN D15 [get_ports aclSCK]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclSCK]
|
||||
##Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN
|
||||
#set_property PACKAGE_PIN C15 [get_ports aclSS]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclSS]
|
||||
##Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1
|
||||
#set_property PACKAGE_PIN C16 [get_ports aclInt1]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclInt1]
|
||||
##Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2
|
||||
#set_property PACKAGE_PIN E15 [get_ports aclInt2]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclInt2]
|
||||
|
||||
|
||||
|
||||
##Temperature Sensor
|
||||
##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL
|
||||
#set_property PACKAGE_PIN F16 [get_ports tmpSCL]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL]
|
||||
##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA
|
||||
#set_property PACKAGE_PIN G16 [get_ports tmpSDA]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA]
|
||||
##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT
|
||||
#set_property PACKAGE_PIN D14 [get_ports tmpInt]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports tmpInt]
|
||||
##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT
|
||||
#set_property PACKAGE_PIN C14 [get_ports tmpCT]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports tmpCT]
|
||||
|
||||
|
||||
|
||||
##Omnidirectional Microphone
|
||||
##Bank = 35, Pin name = IO_25_35, Sch name = M_CLK
|
||||
#set_property PACKAGE_PIN J5 [get_ports micClk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports micClk]
|
||||
##Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA
|
||||
#set_property PACKAGE_PIN H5 [get_ports micData]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports micData]
|
||||
##Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL
|
||||
#set_property PACKAGE_PIN F5 [get_ports micLRSel]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports micLRSel]
|
||||
|
||||
|
||||
|
||||
##PWM Audio Amplifier
|
||||
##Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM
|
||||
#set_property PACKAGE_PIN A11 [get_ports ampPWM]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ampPWM]
|
||||
##Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD
|
||||
#set_property PACKAGE_PIN D12 [get_ports ampSD]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ampSD]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
##Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN
|
||||
#set_property PACKAGE_PIN C4 [get_ports RsRx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
|
||||
##Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT
|
||||
#set_property PACKAGE_PIN D4 [get_ports RsTx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
|
||||
##Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS
|
||||
#set_property PACKAGE_PIN D3 [get_ports RsCts]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsCts]
|
||||
##Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS
|
||||
#set_property PACKAGE_PIN E5 [get_ports RsRts]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsRts]
|
||||
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
##Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK
|
||||
#set_property PACKAGE_PIN F4 [get_ports PS2Clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
|
||||
#set_property PULLUP true [get_ports PS2Clk]
|
||||
##Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA
|
||||
#set_property PACKAGE_PIN B2 [get_ports PS2Data]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
|
||||
#set_property PULLUP true [get_ports PS2Data]
|
||||
|
||||
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
##Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC
|
||||
#set_property PACKAGE_PIN C9 [get_ports PhyMdc]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc]
|
||||
##Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO
|
||||
#set_property PACKAGE_PIN A9 [get_ports PhyMdio]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio]
|
||||
##Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN
|
||||
#set_property PACKAGE_PIN B3 [get_ports PhyRstn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn]
|
||||
##Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV
|
||||
#set_property PACKAGE_PIN D9 [get_ports PhyCrs]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs]
|
||||
##Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR
|
||||
#set_property PACKAGE_PIN C10 [get_ports PhyRxErr]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr]
|
||||
##Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0
|
||||
#set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}]
|
||||
##Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1
|
||||
#set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}]
|
||||
##Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN
|
||||
#set_property PACKAGE_PIN B9 [get_ports PhyTxEn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn]
|
||||
##Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0
|
||||
#set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}]
|
||||
##Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1
|
||||
#set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}]
|
||||
##Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK
|
||||
#set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz]
|
||||
##Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN
|
||||
#set_property PACKAGE_PIN B8 [get_ports PhyIntn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn]
|
||||
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK
|
||||
#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}]
|
||||
##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0
|
||||
#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
|
||||
##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1
|
||||
#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
|
||||
##Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2
|
||||
#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
|
||||
##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3
|
||||
#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
|
||||
##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN
|
||||
#set_property PACKAGE_PIN L13 [get_ports QspiCSn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
|
||||
|
||||
|
||||
|
||||
##Cellular RAM
|
||||
##Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK
|
||||
#set_property PACKAGE_PIN T15 [get_ports RamCLK]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamCLK]
|
||||
##Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN
|
||||
#set_property PACKAGE_PIN T13 [get_ports RamADVn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamADVn]
|
||||
##Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN
|
||||
#set_property PACKAGE_PIN L18 [get_ports RamCEn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamCEn]
|
||||
##Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE
|
||||
#set_property PACKAGE_PIN J14 [get_ports RamCRE]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamCRE]
|
||||
##Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN
|
||||
#set_property PACKAGE_PIN H14 [get_ports RamOEn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamOEn]
|
||||
##Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN
|
||||
#set_property PACKAGE_PIN R11 [get_ports RamWEn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamWEn]
|
||||
##Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN
|
||||
#set_property PACKAGE_PIN J15 [get_ports RamLBn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamLBn]
|
||||
##Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN
|
||||
#set_property PACKAGE_PIN J13 [get_ports RamUBn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamUBn]
|
||||
##Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT
|
||||
#set_property PACKAGE_PIN T14 [get_ports RamWait]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamWait]
|
||||
|
||||
##Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0
|
||||
#set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[0]}]
|
||||
##Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1
|
||||
#set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[1]}]
|
||||
##Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2
|
||||
#set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[2]}]
|
||||
##Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3
|
||||
#set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[3]}]
|
||||
##Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4
|
||||
#set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[4]}]
|
||||
##Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5
|
||||
#set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[5]}]
|
||||
##Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6
|
||||
#set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[6]}]
|
||||
##Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7
|
||||
#set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[7]}]
|
||||
##Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8
|
||||
#set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[8]}]
|
||||
##Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9
|
||||
#set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[9]}]
|
||||
##Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10
|
||||
#set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[10]}]
|
||||
##Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11
|
||||
#set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[11]}]
|
||||
##Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12
|
||||
#set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[12]}]
|
||||
##Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13
|
||||
#set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[13]}]
|
||||
##Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14
|
||||
#set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[14]}]
|
||||
##Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15
|
||||
#set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[15]}]
|
||||
|
||||
##Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0
|
||||
#set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[0]}]
|
||||
##Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1
|
||||
#set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[1]}]
|
||||
##Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2
|
||||
#set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[2]}]
|
||||
##Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3
|
||||
#set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[3]}]
|
||||
##Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4
|
||||
#set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[4]}]
|
||||
##Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5
|
||||
#set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[5]}]
|
||||
##Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6
|
||||
#set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[6]}]
|
||||
##Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7
|
||||
#set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[7]}]
|
||||
##Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8
|
||||
#set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[8]}]
|
||||
##Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9
|
||||
#set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[9]}]
|
||||
##Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10
|
||||
#set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[10]}]
|
||||
##Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11
|
||||
#set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[11]}]
|
||||
##Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12
|
||||
#set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[12]}]
|
||||
##Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13
|
||||
#set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[13]}]
|
||||
##Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14
|
||||
#set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[14]}]
|
||||
##Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15
|
||||
#set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[15]}]
|
||||
##Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16
|
||||
#set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[16]}]
|
||||
##Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17
|
||||
#set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[17]}]
|
||||
##Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18
|
||||
#set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[18]}]
|
||||
##Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19
|
||||
#set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[19]}]
|
||||
##Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20
|
||||
#set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[20]}]
|
||||
##Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21
|
||||
#set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}]
|
||||
##Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22
|
||||
#set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}]
|
||||
|
||||
@@ -0,0 +1,211 @@
|
||||
## This file is a general .xdc for the Nexys A7-100T
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
|
||||
|
||||
|
||||
##Switches
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
##7 segment display
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
##Buttons
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
##Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||
|
||||
##Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||
|
||||
##Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||
|
||||
##Pmod Header JXADC
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||
|
||||
##VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
|
||||
##Micro SD Connector
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||
|
||||
##Accelerometer
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||
|
||||
##Temperature Sensor
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||
|
||||
##Omnidirectional Microphone
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
|
||||
|
||||
##PWM Audio Amplifier
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
##Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
@@ -0,0 +1,211 @@
|
||||
## This file is a general .xdc for the Nexys A7-50T
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
|
||||
|
||||
|
||||
##Switches
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
##7 segment display
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
##Buttons
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
##Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||
|
||||
##Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||
|
||||
##Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||
|
||||
##Pmod Header JXADC
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||
|
||||
##VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
|
||||
##Micro SD Connector
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||
|
||||
##Accelerometer
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||
|
||||
##Temperature Sensor
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||
|
||||
##Omnidirectional Microphone
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
|
||||
|
||||
##PWM Audio Amplifier
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
##Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
@@ -0,0 +1,312 @@
|
||||
### This file is a general .xdc for the Nexys Video Rev. A
|
||||
### To use it in a project:
|
||||
### - uncomment the lines corresponding to used pins
|
||||
### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
|
||||
## Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_34 Sch=sysclk
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
## FMC Transceiver clocks (Must be set to value provided by Mezzanine card, currently set to 156.25 MHz)
|
||||
## Note: This clock is attached to a MGTREFCLK pin
|
||||
#set_property -dict { PACKAGE_PIN E6 } [get_ports { GTP_CLK_N }];
|
||||
#set_property -dict { PACKAGE_PIN F6 } [get_ports { GTP_CLK_P }];
|
||||
#create_clock -add -name gtpclk0_pin -period 6.400 -waveform {0 3.200} [get_ports {GTP_CLK_P}];
|
||||
#set_property -dict { PACKAGE_PIN E10 } [get_ports { FMC_MGT_CLK_N }];
|
||||
#set_property -dict { PACKAGE_PIN F10 } [get_ports { FMC_MGT_CLK_P }];
|
||||
#create_clock -add -name mgtclk1_pin -period 6.400 -waveform {0 3.200} [get_ports {FMC_MGT_CLK_P}];
|
||||
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { led[0] }]; #IO_L15P_T2_DQS_13 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS25 } [get_ports { led[1] }]; #IO_L15N_T2_DQS_13 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS25 } [get_ports { led[2] }]; #IO_L17P_T2_13 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS25 } [get_ports { led[3] }]; #IO_L17N_T2_13 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS25 } [get_ports { led[4] }]; #IO_L14N_T2_SRCC_13 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS25 } [get_ports { led[5] }]; #IO_L16N_T2_13 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS25 } [get_ports { led[6] }]; #IO_L16P_T2_13 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { led[7] }]; #IO_L5P_T0_13 Sch=led[7]
|
||||
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_L20N_T3_16 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_L22N_T3_16 Sch=btnd
|
||||
#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L20P_T3_16 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L6P_T0_16 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_0_16 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS15 } [get_ports { cpu_resetn }]; #IO_L12N_T1_MRCC_35 Sch=cpu_resetn
|
||||
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN E22 IOSTANDARD LVCMOS12 } [get_ports { sw[0] }]; #IO_L22P_T3_16 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN G21 IOSTANDARD LVCMOS12 } [get_ports { sw[2] }]; #IO_L24P_T3_16 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { sw[3] }]; #IO_L24N_T3_16 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { sw[4] }]; #IO_L6P_T0_15 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { sw[5] }]; #IO_0_15 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { sw[6] }]; #IO_L19P_T3_A22_15 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS12 } [get_ports { sw[7] }]; #IO_25_15 Sch=sw[7]
|
||||
|
||||
|
||||
## OLED Display
|
||||
#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { oled_dc }]; #IO_L7N_T1_D10_14 Sch=oled_dc
|
||||
#set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { oled_res }]; #IO_L4N_T0_D05_14 Sch=oled_res
|
||||
#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { oled_sclk }]; #IO_L7P_T1_D09_14 Sch=oled_sclk
|
||||
#set_property -dict { PACKAGE_PIN Y22 IOSTANDARD LVCMOS33 } [get_ports { oled_sdin }]; #IO_L9N_T1_DQS_D13_14 Sch=oled_sdin
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_0_14 Sch=oled_vbat
|
||||
#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { oled_vdd }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=oled_vdd
|
||||
|
||||
|
||||
## HDMI in
|
||||
#set_property -dict { PACKAGE_PIN AA5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec
|
||||
#set_property -dict { PACKAGE_PIN W4 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN V4 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa
|
||||
#set_property -dict { PACKAGE_PIN Y4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
|
||||
#set_property -dict { PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda
|
||||
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen
|
||||
#set_property -dict { PACKAGE_PIN AA3 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN Y3 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN Y2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]
|
||||
|
||||
|
||||
## HDMI out
|
||||
#set_property -dict { PACKAGE_PIN AA4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
|
||||
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AB13 IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd
|
||||
#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rscl }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl
|
||||
#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rsda }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda
|
||||
#set_property -dict { PACKAGE_PIN Y1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN W1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AA1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]
|
||||
|
||||
|
||||
## Display Port
|
||||
#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_n }]; #IO_L8N_T1_13 Sch=dp_tx_aux_n
|
||||
#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_n }]; #IO_L9N_T1_DQS_13 Sch=dp_tx_aux_n
|
||||
#set_property -dict { PACKAGE_PIN AA9 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_p }]; #IO_L8P_T1_13 Sch=dp_tx_aux_p
|
||||
#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_p }]; #IO_L9P_T1_DQS_13 Sch=dp_tx_aux_p
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { dp_tx_hpd }]; #IO_25_14 Sch=dp_tx_hpd
|
||||
|
||||
|
||||
## Audio Codec
|
||||
#set_property -dict { PACKAGE_PIN T4 IOSTANDARD LVCMOS33 } [get_ports { ac_adc_sdata }]; #IO_L13N_T2_MRCC_34 Sch=ac_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_L14P_T2_SRCC_34 Sch=ac_bclk
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { ac_dac_sdata }]; #IO_L15P_T2_DQS_34 Sch=ac_dac_sdata
|
||||
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { ac_lrclk }]; #IO_L14N_T2_SRCC_34 Sch=ac_lrclk
|
||||
#set_property -dict { PACKAGE_PIN U6 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L16P_T2_34 Sch=ac_mclk
|
||||
|
||||
|
||||
## Pmod header JA
|
||||
#set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L10N_T1_D15_14 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L10P_T1_D14_14 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L8N_T1_D12_14 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
|
||||
|
||||
|
||||
## Pmod header JB
|
||||
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L21P_T3_DQS_34 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L21N_T3_DQS_34 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L19P_T3_34 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L19N_T3_VREF_34 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L24P_T3_34 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L24N_T3_34 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L23P_T3_34 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L23N_T3_34 Sch=jb_n[4]
|
||||
|
||||
|
||||
## Pmod header JC
|
||||
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18P_T2_34 Sch=jc_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_34 Sch=jc_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22P_T3_34 Sch=jc_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L22N_T3_34 Sch=jc_n[2]
|
||||
#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L17P_T2_34 Sch=jc_p[3]
|
||||
#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L17N_T2_34 Sch=jc_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L20P_T3_34 Sch=jc_p[4]
|
||||
#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20N_T3_34 Sch=jc_n[4]
|
||||
|
||||
|
||||
## XADC Header
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L1P_T0_AD0P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L1N_T0_AD0N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L5P_T0_AD9P_15 Sch=xa_p[4]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L5N_T0_AD9N_15 Sch=xa_n[4]
|
||||
|
||||
|
||||
## UART
|
||||
#set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_in }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
|
||||
|
||||
|
||||
## Ethernet
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS25 } [get_ports { eth_int_b }]; #IO_L6N_T0_VREF_13 Sch=eth_int_b
|
||||
#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdc }]; #IO_L1N_T0_13 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdio }]; #IO_L1P_T0_13 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS25 } [get_ports { eth_pme_b }]; #IO_L6P_T0_13 Sch=eth_pme_b
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_25_34 Sch=eth_rst_b
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS25 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_13 Sch=eth_rxck
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS25 } [get_ports { eth_rxctl }]; #IO_L10N_T1_13 Sch=eth_rxctl
|
||||
#set_property -dict { PACKAGE_PIN AB16 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[0] }]; #IO_L2P_T0_13 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[1] }]; #IO_L4P_T0_13 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[2] }]; #IO_L4N_T0_13 Sch=eth_rxd[2]
|
||||
#set_property -dict { PACKAGE_PIN AB11 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[3] }]; #IO_L7P_T1_13 Sch=eth_rxd[3]
|
||||
#set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS25 } [get_ports { eth_txck }]; #IO_L5N_T0_13 Sch=eth_txck
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS25 } [get_ports { eth_txctl }]; #IO_L10P_T1_13 Sch=eth_txctl
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[0] }]; #IO_L11N_T1_SRCC_13 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_13 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[2] }]; #IO_L12P_T1_MRCC_13 Sch=eth_txd[2]
|
||||
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[3] }]; #IO_L11P_T1_SRCC_13 Sch=eth_txd[3]
|
||||
|
||||
|
||||
## Fan PWM
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS25 } [get_ports { fan_pwm }]; #IO_L14P_T2_SRCC_13 Sch=fan_pwm
|
||||
|
||||
|
||||
## DPTI/DSPI
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { prog_clko }]; #IO_L13P_T2_MRCC_14 Sch=prog_clko
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { prog_d[0]}]; #IO_L11P_T1_SRCC_14 Sch=prog_d0/sck
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { prog_d[1] }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/mosi
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { prog_d[2] }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/miso
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { prog_d[3]}]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { prog_d[4] }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { prog_d[5] }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { prog_d[6] }]; #IO_L20P_T3_A08_D24_14 Sch=prog_d[6]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { prog_d[7] }]; #IO_L23N_T3_A02_D18_14 Sch=prog_d[7]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { prog_oen }]; #IO_L16P_T2_CSI_B_14 Sch=prog_oen
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { prog_rdn }]; #IO_L5P_T0_D06_14 Sch=prog_rdn
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { prog_rxen }]; #IO_L21P_T3_DQS_14 Sch=prog_rxen
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { prog_siwun }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=prog_siwun
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { prog_spien }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=prog_spien
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { prog_txen }]; #IO_L13N_T2_MRCC_14 Sch=prog_txen
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { prog_wrn }]; #IO_L5N_T0_D07_14 Sch=prog_wrn
|
||||
|
||||
|
||||
## HID port
|
||||
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_clk }]; #IO_L16N_T2_A15_D31_14 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_data }]; #IO_L23P_T3_A03_D19_14 Sch=ps2_data
|
||||
|
||||
|
||||
## QSPI
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
|
||||
## SD card
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { sd_cclk }]; #IO_L12P_T1_MRCC_14 Sch=sd_cclk
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L20N_T3_A07_D23_14 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L12N_T1_MRCC_14 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { sd_d[0] }]; #IO_L14N_T2_SRCC_14 Sch=sd_d[0]
|
||||
#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L4P_T0_D04_14 Sch=sd_d[1]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sd_d[2]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sd_d[3] }]; #IO_L18N_T2_A11_D27_14 Sch=sd_d[3]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L11N_T1_SRCC_14 Sch=sd_reset
|
||||
|
||||
|
||||
## I2C
|
||||
#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { scl }]; #IO_L15N_T2_DQS_34 Sch=scl
|
||||
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { sda }]; #IO_L16N_T2_34 Sch=sda
|
||||
|
||||
|
||||
## Voltage Adjust
|
||||
#set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[0] }]; #IO_L3P_T0_DQS_13 Sch=set_vadj[0]
|
||||
#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[1] }]; #IO_L2N_T0_13 Sch=set_vadj[1]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS25 } [get_ports { vadj_en }]; #IO_L13N_T2_MRCC_13 Sch=vadj_en
|
||||
|
||||
|
||||
## FMC
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_15 Sch=fmc_clk0_m2c_n
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_15 Sch=fmc_clk0_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_n }]; #IO_L13N_T2_MRCC_16 Sch=fmc_clk1_m2c_n
|
||||
#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_p }]; #IO_L13P_T2_MRCC_16 Sch=fmc_clk1_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2_MRCC_15 Sch=fmc_la00_cc_n
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2_MRCC_15 Sch=fmc_la00_cc_p
|
||||
#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la01_cc_n }]; #IO_L11N_T1_SRCC_15 Sch=fmc_la01_cc_n
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la01_cc_p }]; #IO_L11P_T1_SRCC_15 Sch=fmc_la01_cc_p
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[02] }]; #IO_L16N_T2_A27_15 Sch=fmc_la_n[02]
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[02] }]; #IO_L16P_T2_A28_15 Sch=fmc_la_p[02]
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[03] }]; #IO_L17N_T2_A25_15 Sch=fmc_la_n[03]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[03] }]; #IO_L17P_T2_A26_15 Sch=fmc_la_p[03]
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[04] }]; #IO_L18N_T2_A23_15 Sch=fmc_la_n[04]
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[04] }]; #IO_L18P_T2_A24_15 Sch=fmc_la_p[04]
|
||||
#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[05] }]; #IO_L10N_T1_AD11N_15 Sch=fmc_la_n[05]
|
||||
#set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[05] }]; #IO_L10P_T1_AD11P_15 Sch=fmc_la_p[05]
|
||||
#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[06] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_la_n[06]
|
||||
#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[06] }]; #IO_L15P_T2_DQS_15 Sch=fmc_la_p[06]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[07] }]; #IO_L20N_T3_A19_15 Sch=fmc_la_n[07]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[07] }]; #IO_L20P_T3_A20_15 Sch=fmc_la_p[07]
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[08] }]; #IO_L24N_T3_RS0_15 Sch=fmc_la_n[08]
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[08] }]; #IO_L24P_T3_RS1_15 Sch=fmc_la_p[08]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[09] }]; #IO_L8N_T1_AD10N_15 Sch=fmc_la_n[09]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[09] }]; #IO_L8P_T1_AD10P_15 Sch=fmc_la_p[09]
|
||||
#set_property -dict { PACKAGE_PIN K22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[10] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=fmc_la_n[10]
|
||||
#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[10] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=fmc_la_p[10]
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[11] }]; #IO_L22N_T3_A16_15 Sch=fmc_la_n[11]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[11] }]; #IO_L22P_T3_A17_15 Sch=fmc_la_p[11]
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[12] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_la_n[12]
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[12] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_la_p[12]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[13] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_la_n[13]
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[13] }]; #IO_L21P_T3_DQS_15 Sch=fmc_la_p[13]
|
||||
#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[14] }]; #IO_L7N_T1_AD2N_15 Sch=fmc_la_n[14]
|
||||
#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[14] }]; #IO_L7P_T1_AD2P_15 Sch=fmc_la_p[14]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[15] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_la_n[15]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[15] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_la_p[15]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[16] }]; #IO_L4N_T0_15 Sch=fmc_la_n[16]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[16] }]; #IO_L4P_T0_15 Sch=fmc_la_p[16]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la17_cc_n }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la17_cc_n
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la17_cc_p }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la17_cc_p
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la18_cc_n }]; #IO_L12N_T1_MRCC_16 Sch=fmc_la18_cc_n
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la18_cc_p }]; #IO_L12P_T1_MRCC_16 Sch=fmc_la18_cc_p
|
||||
#set_property -dict { PACKAGE_PIN A19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2_16 Sch=fmc_la_n[19]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2_16 Sch=fmc_la_p[19]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[20] }]; #IO_L18N_T2_16 Sch=fmc_la_n[20]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[20] }]; #IO_L18P_T2_16 Sch=fmc_la_p[20]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[21] }]; #IO_L14N_T2_SRCC_16 Sch=fmc_la_n[21]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[21] }]; #IO_L14P_T2_SRCC_16 Sch=fmc_la_p[21]
|
||||
#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[22] }]; #IO_L23N_T3_16 Sch=fmc_la_n[22]
|
||||
#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[22] }]; #IO_L23P_T3_16 Sch=fmc_la_p[22]
|
||||
#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[23] }]; #IO_L21N_T3_DQS_16 Sch=fmc_la_n[23]
|
||||
#set_property -dict { PACKAGE_PIN B21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[23] }]; #IO_L21P_T3_DQS_16 Sch=fmc_la_p[23]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[24] }]; #IO_L7N_T1_16 Sch=fmc_la_n[24]
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[24] }]; #IO_L7P_T1_16 Sch=fmc_la_p[24]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[25] }]; #IO_L2N_T0_16 Sch=fmc_la_n[25]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[25] }]; #IO_L2P_T0_16 Sch=fmc_la_p[25]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[26] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[26]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[26] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[26]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[27] }]; #IO_L16N_T2_16 Sch=fmc_la_n[27]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[27] }]; #IO_L16P_T2_16 Sch=fmc_la_p[27]
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[28] }]; #IO_L8N_T1_16 Sch=fmc_la_n[28]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[28] }]; #IO_L8P_T1_16 Sch=fmc_la_p[28]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[29] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[29]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[29] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[29]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[30] }]; #IO_L10N_T1_16 Sch=fmc_la_n[30]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[30] }]; #IO_L10P_T1_16 Sch=fmc_la_p[30]
|
||||
#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[31] }]; #IO_L4N_T0_16 Sch=fmc_la_n[31]
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[31] }]; #IO_L4P_T0_16 Sch=fmc_la_p[31]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[32] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[32]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[32] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[32]
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[33] }]; #IO_L1N_T0_16 Sch=fmc_la_n[33]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[33] }]; #IO_L1P_T0_16 Sch=fmc_la_p[33]
|
||||
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
@@ -0,0 +1,4 @@
|
||||
# digilent-xdc
|
||||
A collection of Master XDC files for Digilent FPGA and Zynq boards.
|
||||
|
||||
Documentation for these boards, including schematics and reference manuals, can be found through the [Programmable Logic](https://digilent.com/reference/programmable-logic/start) landing page on the Digilent Reference site.
|
||||
@@ -0,0 +1,521 @@
|
||||
## This file is a general .xdc for the Sword Rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## 200MHz Differential Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { clk_p }]; #IO_L12P_T1_MRCC_33 Sch=fpga_sysclk_p
|
||||
#set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { clk_n }]; #IO_L12N_T1_MRCC_33 Sch=fpga_sysclk_n
|
||||
#create_clock -add -name sys_clk_pin -period 5.00 -waveform {0 2.5} [get_ports clk_p]
|
||||
|
||||
## User Reset Button
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS15 } [get_ports { rst }]; #IO_0_VRN_33 Sch=user_rst
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN AG19 IOSTANDARD LVCMOS18 } [get_ports { sw[0] }]; #IO_L8P_T1_32 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN AH19 IOSTANDARD LVCMOS18 } [get_ports { sw[1] }]; #IO_L8N_T1_32 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN AH17 IOSTANDARD LVCMOS18 } [get_ports { sw[2] }]; #IO_L5P_T0_32 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN AF16 IOSTANDARD LVCMOS18 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_32 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN AH16 IOSTANDARD LVCMOS18 } [get_ports { sw[4] }]; #IO_L3P_T0_DQS_32 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN AE16 IOSTANDARD LVCMOS18 } [get_ports { sw[5] }]; #IO_L6P_T0_32 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN AJ19 IOSTANDARD LVCMOS18 } [get_ports { sw[6] }]; #IO_L7P_T1_32 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN AK19 IOSTANDARD LVCMOS18 } [get_ports { sw[7] }]; #IO_L7N_T1_32 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN AJ17 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L5N_T0_32 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN AJ16 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_L3N_T0_DQS_32 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { sw[10] }]; #IO_L1P_T0_32 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { sw[11] }]; #IO_L1N_T0_32 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN AG15 IOSTANDARD LVCMOS18 } [get_ports { sw[12] }]; #IO_L2P_T0_32 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN AH15 IOSTANDARD LVCMOS18 } [get_ports { sw[13] }]; #IO_L2N_T0_32 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN AG14 IOSTANDARD LVCMOS18 } [get_ports { sw[14] }]; #IO_L4N_T0_32 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN AF15 IOSTANDARD LVCMOS18 } [get_ports { sw[15] }]; #IO_L4P_T0_32 Sch=sw[15]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L19P_T3_18 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L20P_T3_18 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L19N_T3_VREF_18 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L20N_T3_18 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_L21N_T3_DQS_18 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L21P_T3_DQS_18 Sch=led17_r
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L9P_T1_DQS_18 Sch=ld[0]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L9N_T1_DQS_18 Sch=ld[1]
|
||||
#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L10P_T1_18 Sch=ld[2]
|
||||
#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L10N_T1_18 Sch=ld[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L11P_T1_SRCC_18 Sch=ld[4]
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L11N_T1_SRCC_18 Sch=ld[5]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L12P_T1_MRCC_18 Sch=ld[6]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L12N_T1_MRCC_18 Sch=ld[7]
|
||||
#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L14P_T2_SRCC_18 Sch=ld[8]
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_18 Sch=ld[9]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L15P_T2_DQS_18 Sch=ld[10]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_18 Sch=ld[11]
|
||||
#set_property -dict { PACKAGE_PIN F11 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_18 Sch=ld[12]
|
||||
#set_property -dict { PACKAGE_PIN AB27 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L12P_T1_MRCC_13 Sch=ld[13]
|
||||
#set_property -dict { PACKAGE_PIN AC27 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L12N_T1_MRCC_13 Sch=ld[14]
|
||||
#set_property -dict { PACKAGE_PIN G30 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L24N_T3_16 Sch=ld[15]
|
||||
|
||||
## Twenty-Five Button Keypad
|
||||
#set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS15 } [get_ports { btn_c[0] }]; #IO_L19P_T3_33 Sch=btn_c[0]
|
||||
#set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { btn_c[1] }]; #IO_L21N_T3_DQS_33 Sch=btn_c[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { btn_c[2] }]; #IO_L22P_T3_33 Sch=btn_c[2]
|
||||
#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { btn_c[3] }]; #IO_L21P_T3_DQS_33 Sch=btn_c[3]
|
||||
#set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { btn_c[4] }]; #IO_L23N_T3_33 Sch=btn_c[4]
|
||||
#set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { btn_r[0] }]; #IO_L20P_T3_33 Sch=btn_r[0]
|
||||
#set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { btn_r[1] }]; #IO_L20N_T3_33 Sch=btn_r[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { btn_r[2] }]; #IO_L22N_T3_33 Sch=btn_r[2]
|
||||
#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { btn_r[3] }]; #IO_L23P_T3_33 Sch=btn_r[3]
|
||||
#set_property -dict { PACKAGE_PIN AH10 IOSTANDARD LVCMOS15 } [get_ports { btn_r[4] }]; #IO_L13N_T2_MRCC_33 Sch=btn_r[4]
|
||||
|
||||
## Seven Segment Display
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { sseg_clk }]; #IO_L17P_T2_18 Sch=7seg_clk
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS33 } [get_ports { sseg_en }]; #IO_L17N_T2_18 Sch=7seg_en
|
||||
#set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS33 } [get_ports { sseg_sdo }]; #IO_L16N_T2_18 Sch=7seg_sdo
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN E24 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L4P_T0_16 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN D24 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L4N_T0_16 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN G23 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L6P_T0_16 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN G24 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L6N_T0_VREF_16 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN F26 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L5P_T0_16 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN E26 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L5N_T0_16 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B27 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L7P_T1_16 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN A27 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L7N_T1_16 Sch=ja_n[4]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN B28 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L9P_T1_DQS_16 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A28 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L9N_T1_DQS_16 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A25 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L10P_T1_16 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN A26 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L10N_T1_16 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN D26 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L11P_T1_SRCC_16 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN C26 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L11N_T1_SRCC_16 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN C25 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L12P_T1_MRCC_16 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN B25 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L12N_T1_MRCC_16 Sch=jb_n[4]
|
||||
|
||||
## Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN E28 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L14P_T2_SRCC_16 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN D28 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L14N_T2_SRCC_16 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN C29 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L15P_T2_DQS_16 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN B29 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15N_T2_DQS_16 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L16P_T2_16 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L16N_T2_16 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN B30 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L17P_T2_16 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN A30 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L17N_T2_16 Sch=jc[10]
|
||||
|
||||
## Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN E29 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L18P_T2_16 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN E30 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L18N_T2_16 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L19P_T3_16 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN H25 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L19N_T3_VREF_16 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN G28 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L20P_T3_16 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN F28 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20N_T3_16 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_16 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F27 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_16 Sch=jd[10]
|
||||
|
||||
## USB-UART Interface
|
||||
## NOTE:
|
||||
#set_property -dict { PACKAGE_PIN F30 IOSTANDARD LVCMOS33 } [get_ports { uart_tx }]; #IO_L22N_T3_16 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN G29 IOSTANDARD LVCMOS33 } [get_ports { uart_rx }]; #IO_L22P_T3_16 Sch=uart_txd_in
|
||||
|
||||
## USB-HID PS/2 Interface for Keyboard
|
||||
#set_property -dict { PACKAGE_PIN AF23 IOSTANDARD LVCMOS33 } [get_ports { ps2_keyboard_clk }]; #IO_L11N_T1_SRCC_12 Sch=ps2_clk[0]
|
||||
#set_property -dict { PACKAGE_PIN AD23 IOSTANDARD LVCMOS33 } [get_ports { ps2_keyboard_data }]; #IO_L12P_T1_MRCC_12 Sch=ps2_data[0]
|
||||
|
||||
## USB-HID PS/2 Interface for Mouse
|
||||
#set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { ps2_mouse_clk }]; #IO_L12N_T1_MRCC_12 Sch=ps2_clk[1]
|
||||
#set_property -dict { PACKAGE_PIN AF22 IOSTANDARD LVCMOS33 } [get_ports { ps2_mouse_data }]; #IO_L13P_T2_MRCC_12 Sch=ps2_data[1]
|
||||
|
||||
## Audio Codec
|
||||
#set_property -dict { PACKAGE_PIN AJ18 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L9P_T1_DQS_32 Sch=aud_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN AF18 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[0] }]; #IO_L11P_T1_SRCC_32 Sch=aud_adr[0]
|
||||
#set_property -dict { PACKAGE_PIN AG18 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[1] }]; #IO_L11N_T1_SRCC_32 Sch=aud_adr[1]
|
||||
#set_property -dict { PACKAGE_PIN AD19 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L10P_T1_32 Sch=aud_bclk
|
||||
#set_property -dict { PACKAGE_PIN AK18 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L9N_T1_DQS_32 Sch=aud_dac_sdata
|
||||
#set_property -dict { PACKAGE_PIN AE19 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_T1_32 Sch=aud_lrclk
|
||||
#set_property -dict { PACKAGE_PIN AF17 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L12P_T1_MRCC_32 Sch=aud_mclk
|
||||
#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_25_VRP_32 Sch=aud_scl
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS18 } [get_ports { aud_sda }]; #IO_0_VRN_32 Sch=aud_sda
|
||||
|
||||
## Dedicated Analog Inputs
|
||||
#set_property -dict { PACKAGE_PIN R15 } [get_ports { v_p }]; #VP_0 Sch=v_p
|
||||
#set_property -dict { PACKAGE_PIN T14 } [get_ports { v_n }]; #VN_0 Sch=v_n
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L20N_T3_A19_15 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN N25 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A24_15 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L22N_T3_A16_15 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_25_16 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN L25 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN M25 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L23N_T3_FWE_B_15 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN L26 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN K29 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L13N_T2_MRCC_15 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN M29 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L15P_T2_DQS_15 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN M30 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=ck_io[9]
|
||||
|
||||
## ChipKit SPI Header
|
||||
## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13
|
||||
#set_property -dict { PACKAGE_PIN L28 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L14N_T2_SRCC_15 Sch=ck_io10_ss
|
||||
#set_property -dict { PACKAGE_PIN M27 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L16N_T2_A27_15 Sch=ck_io11_mosi
|
||||
#set_property -dict { PACKAGE_PIN N29 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L17P_T2_A26_15 Sch=ck_io12_miso
|
||||
#set_property -dict { PACKAGE_PIN N30 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L17N_T2_A25_15 Sch=ck_io13_sck
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L6P_T0_15 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN N24 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L21N_T3_DQS_A18_15 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN P23 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L21P_T3_DQS_15 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_0_15 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L22P_T3_A17_15 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L19N_T3_A21_VREF_15 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN F23 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_0_16 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN K28 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_15 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN L27 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L19P_T3_A22_15 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_25_15 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN M28 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L14P_T2_SRCC_15 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L24P_T3_RS1_15 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN M23 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L24N_T3_RS0_15 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN N27 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16P_T2_A28_15 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN N26 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L18N_T2_A23_15 Sch=ck_io[41]
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN J29 IOSTANDARD LVCMOS33 } [get_ports { vaux10_p }]; #IO_L7P_T1_AD10P_15 Sch=ck_an_p[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN H29 IOSTANDARD LVCMOS33 } [get_ports { vaux10_n }]; #IO_L7N_T1_AD10N_15 Sch=ck_an_n[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_15 Sch=ck_an_p[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN L23 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_15 Sch=ck_an_n[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN J23 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN J24 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN K23 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN K24 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L4P_T0_AD9P_15 Sch=ck_an_p[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L4N_T0_AD9N_15 Sch=ck_an_n[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS33 } [get_ports { vaux2_p }]; #IO_L5P_T0_AD2P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS33 } [get_ports { vaux2_n }]; #IO_L5N_T0_AD2N_15 Sch=ck_an_n[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B23 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L1P_T0_16 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN A23 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L1N_T0_16 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN E23 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L2P_T0_16 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN D23 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L2N_T0_16 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN F25 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L3P_T0_DQS_16 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN E25 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L3N_T0_DQS_16 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN J27 IOSTANDARD LVCMOS33 } [get_ports { vaux3_p }]; #IO_L8P_T1_AD3P_15 Sch=fpga_ad_p[3] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN J28 IOSTANDARD LVCMOS33 } [get_ports { vaux3_n }]; #IO_L8N_T1_AD3N_15 Sch=fpga_ad_n[3] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN L30 IOSTANDARD LVCMOS33 } [get_ports { vaux11_p }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fpga_ad_p[11] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN K30 IOSTANDARD LVCMOS33 } [get_ports { vaux11_n }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fpga_ad_n[11] ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L10P_T1_AD4P_15 Sch=fpga_ad_p[4] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L10N_T1_AD4N_15 Sch=fpga_ad_n[4] ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN J28 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L8N_T1_AD3N_15 Sch=fpga_ad_n[3]
|
||||
#set_property -dict { PACKAGE_PIN J27 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L8P_T1_AD3P_15 Sch=fpga_ad_p[3]
|
||||
#set_property -dict { PACKAGE_PIN K30 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fpga_ad_n[11]
|
||||
#set_property -dict { PACKAGE_PIN L30 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fpga_ad_p[11]
|
||||
#set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L10N_T1_AD4N_15 Sch=fpga_ad_n[4]
|
||||
#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L10P_T1_AD4P_15 Sch=fpga_ad_p[4]
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN K25 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN N21 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L20P_T3_A20_15 Sch=ck_sda
|
||||
|
||||
## Misc. ChipKit signals
|
||||
#set_property -dict { PACKAGE_PIN M24 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L23P_T3_FOE_B_15 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L6N_T0_VREF_15 Sch=ck_rst
|
||||
|
||||
## Fan Control
|
||||
#set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS33 } [get_ports { fan_pwm }]; #IO_L23N_T3_16 Sch=fan_pwm
|
||||
#set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS33 } [get_ports { fan_tach }]; #IO_L23P_T3_16 Sch=fan_tach
|
||||
|
||||
## USB Host Port
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { usbh_gpx }]; #IO_L22P_T3_18 Sch=usbh_gpx
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { usbh_int }]; #IO_L22N_T3_18 Sch=usbh_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { usbh_miso }]; #IO_L24P_T3_18 Sch=usbh_miso
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { usbh_mosi }]; #IO_L24N_T3_18 Sch=usbh_mosi
|
||||
#set_property -dict { PACKAGE_PIN AD13 IOSTANDARD LVCMOS15 } [get_ports { usbh_rst }]; #IO_25_VRP_33 Sch=usbh_rst
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { usbh_sclk }]; #IO_L23P_T3_18 Sch=usbh_sclk
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { usbh_ss }]; #IO_L23N_T3_18 Sch=usbh_ss
|
||||
|
||||
## RS232 Connector
|
||||
#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS33 } [get_ports { rs232_rxd }]; #IO_L18P_T2_18 Sch=uart1_rxd
|
||||
#set_property -dict { PACKAGE_PIN G12 IOSTANDARD LVCMOS33 } [get_ports { rs232_txd }]; #IO_0_18 Sch=uart1_txd
|
||||
|
||||
# 3-Pin UART Connector (TTL-Compliant)
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ttl_rxd }]; #IO_L18N_T2_18 Sch=uart2_rxd
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ttl_txd }]; #IO_25_18 Sch=uart2_txd
|
||||
|
||||
## VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN AA23 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L4N_T0_12 Sch=vga_b[3]
|
||||
#set_property -dict { PACKAGE_PIN AC24 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L9P_T1_DQS_12 Sch=vga_b[4]
|
||||
#set_property -dict { PACKAGE_PIN AD24 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L9N_T1_DQS_12 Sch=vga_b[5]
|
||||
#set_property -dict { PACKAGE_PIN AB23 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L3N_T0_DQS_12 Sch=vga_b[6]
|
||||
#set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L3P_T0_DQS_12 Sch=vga_b[7]
|
||||
#set_property -dict { PACKAGE_PIN AA22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L4P_T0_12 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN AC21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L5N_T0_12 Sch=vga_g[3]
|
||||
#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2P_T0_12 Sch=vga_g[4]
|
||||
#set_property -dict { PACKAGE_PIN AC20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L5P_T0_12 Sch=vga_g[5]
|
||||
#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L6N_T0_VREF_12 Sch=vga_g[6]
|
||||
#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L6P_T0_12 Sch=vga_g[7]
|
||||
#set_property -dict { PACKAGE_PIN AC25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7N_T1_12 Sch=vga_r[3]
|
||||
#set_property -dict { PACKAGE_PIN AB24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7P_T1_12 Sch=vga_r[4]
|
||||
#set_property -dict { PACKAGE_PIN Y24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_12 Sch=vga_r[5]
|
||||
#set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L1P_T0_12 Sch=vga_r[6]
|
||||
#set_property -dict { PACKAGE_PIN AD22 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L8N_T1_12 Sch=vga_r[7]
|
||||
#set_property -dict { PACKAGE_PIN AD21 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L10P_T1_12 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN AE23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L11P_T1_SRCC_12 Sch=vga_vs
|
||||
#set_property -dict { PACKAGE_PIN AC22 IOSTANDARD LVCMOS33 } [get_ports { vga_scl }]; #IO_L8P_T1_12 Sch=vga_scl
|
||||
#set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { vga_sda }]; #IO_L2N_T0_12 Sch=vga_sda
|
||||
|
||||
## HDMI Input
|
||||
#set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L19N_T3_VREF_12 Sch=hdmi_rx_cec
|
||||
#set_property -dict { PACKAGE_PIN AH29 IOSTANDARD LVDS } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_13 Sch=hdmi_rx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AG29 IOSTANDARD LVDS } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_13 Sch=hdmi_rx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpa }]; #IO_L19P_T3_12 Sch=hdmi_rx_hpa
|
||||
#set_property -dict { PACKAGE_PIN AK26 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[0] }]; #IO_L24N_T3_13 Sch=hdmi_rx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AJ26 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[0] }]; #IO_L24P_T3_13 Sch=hdmi_rx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AH27 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[1] }]; #IO_L22N_T3_13 Sch=hdmi_rx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AH26 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[1] }]; #IO_L22P_T3_13 Sch=hdmi_rx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AF27 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[2] }]; #IO_L23N_T3_13 Sch=hdmi_rx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AF26 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[2] }]; #IO_L23P_T3_13 Sch=hdmi_rx_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L17N_T2_12 Sch=hdmi_rx_scl
|
||||
#set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17P_T2_12 Sch=hdmi_rx_sda
|
||||
|
||||
## HDMI Output
|
||||
#set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L18N_T2_12 Sch=hdmi_tx_cec
|
||||
#set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVDS } [get_ports { hdmi_tx_clk_n }]; #IO_L22N_T3_12 Sch=hdmi_tx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVDS } [get_ports { hdmi_tx_clk_p }]; #IO_L22P_T3_12 Sch=hdmi_tx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L18P_T2_12 Sch=hdmi_tx_hpd
|
||||
#set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[0] }]; #IO_L23N_T3_12 Sch=hdmi_tx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AH21 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[0] }]; #IO_L23P_T3_12 Sch=hdmi_tx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[1] }]; #IO_L21N_T3_DQS_12 Sch=hdmi_tx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[1] }]; #IO_L21P_T3_DQS_12 Sch=hdmi_tx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[2] }]; #IO_L20N_T3_12 Sch=hdmi_tx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[2] }]; #IO_L20P_T3_12 Sch=hdmi_tx_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L24P_T3_12 Sch=hdmi_tx_scl
|
||||
#set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L24N_T3_12 Sch=hdmi_tx_sda
|
||||
|
||||
## Ethernet
|
||||
#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS18 } [get_ports { eth_intb }]; #IO_L16N_T2_32 Sch=eth_intb
|
||||
#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 } [get_ports { eth_mdc }]; #IO_L16P_T2_32 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS18 } [get_ports { eth_mdio }]; #IO_L15N_T2_DQS_32 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS18 } [get_ports { eth_phyrst }]; #IO_L15P_T2_DQS_32 Sch=eth_phyrst
|
||||
#set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS18 } [get_ports { eth_pmeb }]; #IO_L17P_T2_32 Sch=eth_pmeb
|
||||
#set_property -dict { PACKAGE_PIN AD18 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_clk }]; #IO_L13P_T2_MRCC_32 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_ctl }]; #IO_L19N_T3_VREF_32 Sch=eth_rx_ctl
|
||||
#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[0] }]; #IO_L19P_T3_32 Sch=eth_rx_d[0]
|
||||
#set_property -dict { PACKAGE_PIN AE18 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[1] }]; #IO_L13N_T2_MRCC_32 Sch=eth_rx_d[1]
|
||||
#set_property -dict { PACKAGE_PIN AD16 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[2] }]; #IO_L14N_T2_SRCC_32 Sch=eth_rx_d[2]
|
||||
#set_property -dict { PACKAGE_PIN AC19 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[3] }]; #IO_L17N_T2_32 Sch=eth_rx_d[3]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_clk }]; #IO_L20N_T3_32 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[0] }]; #IO_L20P_T3_32 Sch=eth_tx_d[0]
|
||||
#set_property -dict { PACKAGE_PIN AD17 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[1] }]; #IO_L14P_T2_SRCC_32 Sch=eth_tx_d[1]
|
||||
#set_property -dict { PACKAGE_PIN AG17 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[2] }]; #IO_L12N_T1_MRCC_32 Sch=eth_tx_d[2]
|
||||
#set_property -dict { PACKAGE_PIN AC17 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[3] }]; #IO_L18N_T2_32 Sch=eth_tx_d[3]
|
||||
#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_en }]; #IO_L18P_T2_32 Sch=eth_tx_en
|
||||
|
||||
## SFP+ Clock Multiplier / FPGA GTX Transceiver Clock Source
|
||||
#set_property -dict { PACKAGE_PIN AC16 IOSTANDARD LVCMOS18 } [get_ports { sfp_clk_alarm_b }]; #IO_L21P_T3_DQS_32 Sch=sfp_clk_alarm_b
|
||||
#set_property -dict { PACKAGE_PIN AC15 IOSTANDARD LVCMOS18 } [get_ports { sfp_clk_rst }]; #IO_L21N_T3_DQS_32 Sch=sfp_clk_rst
|
||||
#set_property -dict { PACKAGE_PIN AE20 IOSTANDARD LVCMOS33 } [get_ports { sfp_clk_scl }]; #IO_25_12 Sch=sfp_clk_scl
|
||||
#set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { sfp_clk_sda }]; #IO_0_12 Sch=sfp_clk_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVDS } [get_ports { sfp_rec_clk_n }]; #IO_L13N_T2_MRCC_18 Sch=sfp_rec_clk_n
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVDS } [get_ports { sfp_rec_clk_p }]; #IO_L13P_T2_MRCC_18 Sch=sfp_rec_clk_p
|
||||
|
||||
## SFP+ Connector 1
|
||||
#set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS18 } [get_ports { sfp1_mod_detect }]; #IO_L23P_T3_32 Sch=sfp1_mod_detect
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS18 } [get_ports { sfp1_rs[0] }]; #IO_L24P_T3_32 Sch=sfp1_rs[0]
|
||||
#set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 } [get_ports { sfp1_rs[1] }]; #IO_L24N_T3_32 Sch=sfp1_rs[1]
|
||||
#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS18 } [get_ports { sfp1_rx_los }]; #IO_L23N_T3_32 Sch=sfp1_rx_los
|
||||
#set_property -dict { PACKAGE_PIN AD14 IOSTANDARD LVCMOS18 } [get_ports { sfp1_tx_disable }]; #IO_L22N_T3_32 Sch=sfp1_tx_disable
|
||||
#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS18 } [get_ports { sfp1_tx_fault }]; #IO_L22P_T3_32 Sch=sfp1_tx_fault
|
||||
#set_property -dict { PACKAGE_PIN C27 IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp1_scl }]; #IO_L13N_T2_MRCC_16 Sch=i2c_sfp1_scl
|
||||
#set_property -dict { PACKAGE_PIN D27 IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp1_sda }]; #IO_L13P_T2_MRCC_16 Sch=i2c_sfp1_sda
|
||||
|
||||
## SFP+ Connector 2
|
||||
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { sfp2_mod_detect }]; #IO_L18P_T2_33 Sch=sfp2_mod_detect
|
||||
#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { sfp2_rs[0] }]; #IO_L14P_T2_SRCC_33 Sch=sfp2_rs[0]
|
||||
#set_property -dict { PACKAGE_PIN AF10 IOSTANDARD LVCMOS15 } [get_ports { sfp2_rs[1] }]; #IO_L14N_T2_SRCC_33 Sch=sfp2_rs[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { sfp2_rx_los }]; #IO_L18N_T2_33 Sch=sfp2_rx_los
|
||||
#set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { sfp2_tx_disable }]; #IO_L17N_T2_33 Sch=sfp2_tx_disable
|
||||
#set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { sfp2_tx_fault }]; #IO_L17P_T2_33 Sch=sfp2_tx_fault
|
||||
#set_property -dict { PACKAGE_PIN B24 IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp2_scl }]; #IO_L8N_T1_16 Sch=i2c_sfp2_scl
|
||||
#set_property -dict { PACKAGE_PIN C24 IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp2_sda }]; #IO_L8P_T1_16 Sch=i2c_sfp2_sda
|
||||
|
||||
## Quad-SPI Flash
|
||||
## NOTE: the SCK clock signal can be driven using the STARTUPE2 primitive
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
#set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { qspi_d[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0]
|
||||
#set_property -dict { PACKAGE_PIN R25 IOSTANDARD LVCMOS33 } [get_ports { qspi_d[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1]
|
||||
#set_property -dict { PACKAGE_PIN R20 IOSTANDARD LVCMOS33 } [get_ports { qspi_d[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2]
|
||||
#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { qspi_d[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3]
|
||||
|
||||
## SD Card Slot
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_25_14 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L15P_T2_DQS_12 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN AE25 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_12 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN AF25 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L16N_T2_12 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN AG24 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L14P_T2_SRCC_12 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_12 Sch=sd_dat[3]
|
||||
#set_property -dict { PACKAGE_PIN AE21 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L10N_T1_12 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { sd_sclk }]; #IO_L15N_T2_DQS_12 Sch=sd_sclk
|
||||
|
||||
## Parallel Flash Memory
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { flash_byte }]; #IO_L19P_T3_17 Sch=flash_byte
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { flash_ce[0] }]; #IO_L18P_T2_17 Sch=flash_ce[1]
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { flash_ce[1] }]; #IO_L15P_T2_DQS_17 Sch=flash_ce[2]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { flash_oe }]; #IO_L15N_T2_DQS_17 Sch=flash_oe
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { flash_rst }]; #IO_L16N_T2_17 Sch=flash_rst
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { flash_ryby[0] }]; #IO_L16P_T2_17 Sch=flash_ryby[1]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { flash_ryby[1] }]; #IO_L24N_T3_17 Sch=flash_ryby[2]
|
||||
#set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33 } [get_ports { flash_we }]; #IO_L9P_T1_DQS_17 Sch=flash_we
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { flash_a[0] }]; #IO_L13P_T2_MRCC_17 Sch=flash_a[0]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { flash_a[1] }]; #IO_L22N_T3_17 Sch=flash_a[1]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { flash_a[2] }]; #IO_L17N_T2_17 Sch=flash_a[2]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { flash_a[3] }]; #IO_L20P_T3_17 Sch=flash_a[3]
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { flash_a[4] }]; #IO_L20N_T3_17 Sch=flash_a[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { flash_a[5] }]; #IO_L22P_T3_17 Sch=flash_a[5]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { flash_a[6] }]; #IO_L17P_T2_17 Sch=flash_a[6]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { flash_a[7] }]; #IO_L14N_T2_SRCC_17 Sch=flash_a[7]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { flash_a[8] }]; #IO_L12P_T1_MRCC_17 Sch=flash_a[8]
|
||||
#set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 } [get_ports { flash_a[9] }]; #IO_L9N_T1_DQS_17 Sch=flash_a[9]
|
||||
#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS33 } [get_ports { flash_a[10] }]; #IO_L24P_T3_17 Sch=flash_a[10]
|
||||
#set_property -dict { PACKAGE_PIN E20 IOSTANDARD LVCMOS33 } [get_ports { flash_a[11] }]; #IO_L12N_T1_MRCC_17 Sch=flash_a[11]
|
||||
#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS33 } [get_ports { flash_a[12] }]; #IO_L10P_T1_17 Sch=flash_a[12]
|
||||
#set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33 } [get_ports { flash_a[13] }]; #IO_L11P_T1_SRCC_17 Sch=flash_a[13]
|
||||
#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS33 } [get_ports { flash_a[14] }]; #IO_L10N_T1_17 Sch=flash_a[14]
|
||||
#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS33 } [get_ports { flash_a[15] }]; #IO_L11N_T1_SRCC_17 Sch=flash_a[15]
|
||||
#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS33 } [get_ports { flash_a[16] }]; #IO_L21N_T3_DQS_17 Sch=flash_a[16]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { flash_a[17] }]; #IO_L13N_T2_MRCC_17 Sch=flash_a[17]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { flash_a[18] }]; #IO_25_17 Sch=flash_a[18]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { flash_a[19] }]; #IO_L14P_T2_SRCC_17 Sch=flash_a[19]
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { flash_a[20] }]; #IO_L18N_T2_17 Sch=flash_a[20]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { flash_a[21] }]; #IO_0_17 Sch=flash_a[21]
|
||||
#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS33 } [get_ports { flash_a[22] }]; #IO_L23P_T3_17 Sch=flash_a[22]
|
||||
#set_property -dict { PACKAGE_PIN A22 IOSTANDARD LVCMOS33 } [get_ports { flash_a[23] }]; #IO_L23N_T3_17 Sch=flash_a[23]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { flash_a[24] }]; #IO_L19N_T3_VREF_17 Sch=flash_a[24]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { flash_a[25] }]; #IO_L21P_T3_DQS_17 Sch=flash_a[25]
|
||||
#set_property -dict { PACKAGE_PIN L11 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[0] }]; #IO_L6P_T0_18 Sch=flash_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[1] }]; #IO_L4P_T0_18 Sch=flash_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L12 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[2] }]; #IO_L3P_T0_DQS_18 Sch=flash_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[3] }]; #IO_L5N_T0_18 Sch=flash_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[4] }]; #IO_L2P_T0_18 Sch=flash_dq[4]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[5] }]; #IO_L2N_T0_18 Sch=flash_dq[5]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[6] }]; #IO_L1P_T0_18 Sch=flash_dq[6]
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[7] }]; #IO_L7N_T1_18 Sch=flash_dq[7]
|
||||
#set_property -dict { PACKAGE_PIN K11 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[8] }]; #IO_L6N_T0_VREF_18 Sch=flash_dq[8]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[9] }]; #IO_L3N_T0_DQS_18 Sch=flash_dq[9]
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[10] }]; #IO_L8P_T1_18 Sch=flash_dq[10]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[11] }]; #IO_L5P_T0_18 Sch=flash_dq[11]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[12] }]; #IO_L8N_T1_18 Sch=flash_dq[12]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[13] }]; #IO_L7P_T1_18 Sch=flash_dq[13]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[14] }]; #IO_L4N_T0_18 Sch=flash_dq[14]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[15] }]; #IO_L1N_T0_18 Sch=flash_dq[15]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[16] }]; #IO_L3P_T0_DQS_17 Sch=flash_dq[16]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[17] }]; #IO_L3N_T0_DQS_17 Sch=flash_dq[17]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[18] }]; #IO_L6P_T0_17 Sch=flash_dq[18]
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[19] }]; #IO_L4N_T0_17 Sch=flash_dq[19]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[20] }]; #IO_L2N_T0_17 Sch=flash_dq[20]
|
||||
#set_property -dict { PACKAGE_PIN K20 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[21] }]; #IO_L6N_T0_VREF_17 Sch=flash_dq[21]
|
||||
#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[22] }]; #IO_L8P_T1_17 Sch=flash_dq[22]
|
||||
#set_property -dict { PACKAGE_PIN C21 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[23] }]; #IO_L8N_T1_17 Sch=flash_dq[23]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[24] }]; #IO_L5P_T0_17 Sch=flash_dq[24]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[25] }]; #IO_L1N_T0_17 Sch=flash_dq[25]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[26] }]; #IO_L1P_T0_17 Sch=flash_dq[26]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[27] }]; #IO_L4P_T0_17 Sch=flash_dq[27]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[28] }]; #IO_L2P_T0_17 Sch=flash_dq[28]
|
||||
#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[29] }]; #IO_L7N_T1_17 Sch=flash_dq[29]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[30] }]; #IO_L5N_T0_17 Sch=flash_dq[30]
|
||||
#set_property -dict { PACKAGE_PIN H21 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[31] }]; #IO_L7P_T1_17 Sch=flash_dq[31]
|
||||
|
||||
## SRAM Memories
|
||||
#set_property -dict { PACKAGE_PIN U24 IOSTANDARD LVCMOS33 } [get_ports { sram1_bhe }]; #IO_L23P_T3_A03_D19_14 Sch=sram1-bhe
|
||||
#set_property -dict { PACKAGE_PIN AG30 IOSTANDARD LVCMOS33 } [get_ports { sram1_ble }]; #IO_L18P_T2_13 Sch=sram1-ble
|
||||
#set_property -dict { PACKAGE_PIN T25 IOSTANDARD LVCMOS33 } [get_ports { sram1_ce }]; #IO_L14P_T2_SRCC_14 Sch=sram1-ce
|
||||
#set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { sram1_oe }]; #IO_L16N_T2_13 Sch=sram1-oe
|
||||
#set_property -dict { PACKAGE_PIN AE28 IOSTANDARD LVCMOS33 } [get_ports { sram1_we }]; #IO_L14P_T2_SRCC_13 Sch=sram1-we
|
||||
#set_property -dict { PACKAGE_PIN AC29 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[0] }]; #IO_L7P_T1_13 Sch=sram1-io[0]
|
||||
#set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[1] }]; #IO_L5N_T0_D07_14 Sch=sram1-io[1]
|
||||
#set_property -dict { PACKAGE_PIN AC30 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[2] }]; #IO_L7N_T1_13 Sch=sram1-io[2]
|
||||
#set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[3] }]; #IO_L5P_T0_D06_14 Sch=sram1-io[3]
|
||||
#set_property -dict { PACKAGE_PIN AD26 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[4] }]; #IO_L19N_T3_VREF_13 Sch=sram1-io[4]
|
||||
#set_property -dict { PACKAGE_PIN AF28 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[5] }]; #IO_L14N_T2_SRCC_13 Sch=sram1-io[5]
|
||||
#set_property -dict { PACKAGE_PIN AB29 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[6] }]; #IO_L10P_T1_13 Sch=sram1-io[6]
|
||||
#set_property -dict { PACKAGE_PIN AB30 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[7] }]; #IO_L10N_T1_13 Sch=sram1-io[7]
|
||||
#set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[8] }]; #IO_L18N_T2_13 Sch=sram1-io[8]
|
||||
#set_property -dict { PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[9] }]; #IO_L17N_T2_13 Sch=sram1-io[9]
|
||||
#set_property -dict { PACKAGE_PIN V25 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[10] }]; #IO_L18P_T2_A12_D28_14 Sch=sram1-io[10]
|
||||
#set_property -dict { PACKAGE_PIN V24 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[11] }]; #IO_L23N_T3_A02_D18_14 Sch=sram1-io[11]
|
||||
#set_property -dict { PACKAGE_PIN U23 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[12] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram1-io[12]
|
||||
#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[13] }]; #IO_L22N_T3_A04_D20_14 Sch=sram1-io[13]
|
||||
#set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[14] }]; #IO_L15N_T2_DQS_13 Sch=sram1-io[14]
|
||||
#set_property -dict { PACKAGE_PIN AK29 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[15] }]; #IO_L15P_T2_DQS_13 Sch=sram1-io[15]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN AB28 IOSTANDARD LVCMOS33 } [get_ports { sram2_bhe[0] }]; #IO_L5N_T0_13 Sch=sram2-bhe[1]
|
||||
#set_property -dict { PACKAGE_PIN V26 IOSTANDARD LVCMOS33 } [get_ports { sram2_bhe[1] }]; #IO_L16P_T2_CSI_B_14 Sch=sram2-bhe[2]
|
||||
#set_property -dict { PACKAGE_PIN AC26 IOSTANDARD LVCMOS33 } [get_ports { sram2_ble[0] }]; #IO_L19P_T3_13 Sch=sram2-ble[1]
|
||||
#set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { sram2_ble[1] }]; #IO_L2P_T0_13 Sch=sram2-ble[2]
|
||||
#set_property -dict { PACKAGE_PIN Y28 IOSTANDARD LVCMOS33 } [get_ports { sram2_ce[0] }]; #IO_L3P_T0_DQS_13 Sch=sram2-ce[1]
|
||||
#set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sram2_ce[1] }]; #IO_L8N_T1_D12_14 Sch=sram2-ce[2]
|
||||
#set_property -dict { PACKAGE_PIN AB25 IOSTANDARD LVCMOS33 } [get_ports { sram2_oe[0] }]; #IO_L6N_T0_VREF_13 Sch=sram2-oe[1]
|
||||
#set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { sram2_oe[1] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram2-oe[2]
|
||||
#set_property -dict { PACKAGE_PIN W23 IOSTANDARD LVCMOS33 } [get_ports { sram2_we[0] }]; #IO_L20P_T3_A08_D24_14 Sch=sram2-we[1]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { sram2_we[1] }]; #IO_L4P_T0_D04_14 Sch=sram2-we[2]
|
||||
#set_property -dict { PACKAGE_PIN Y26 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[0] }]; #IO_L1P_T0_13 Sch=sram2-io[0]
|
||||
#set_property -dict { PACKAGE_PIN AA26 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[1] }]; #IO_L1N_T0_13 Sch=sram2-io[1]
|
||||
#set_property -dict { PACKAGE_PIN U27 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[2] }]; #IO_L13P_T2_MRCC_14 Sch=sram2-io[2]
|
||||
#set_property -dict { PACKAGE_PIN AA28 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[3] }]; #IO_L3N_T0_DQS_13 Sch=sram2-io[3]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sram2-io[4]
|
||||
#set_property -dict { PACKAGE_PIN W26 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[5] }]; #IO_L18N_T2_A11_D27_14 Sch=sram2-io[5]
|
||||
#set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[6] }]; #IO_L21P_T3_DQS_14 Sch=sram2-io[6]
|
||||
#set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[7] }]; #IO_L10P_T1_D14_14 Sch=sram2-io[7]
|
||||
#set_property -dict { PACKAGE_PIN Y25 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[8] }]; #IO_0_13 Sch=sram2-io[8]
|
||||
#set_property -dict { PACKAGE_PIN AA25 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[9] }]; #IO_L6P_T0_13 Sch=sram2-io[9]
|
||||
#set_property -dict { PACKAGE_PIN AA27 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[10] }]; #IO_L5P_T0_13 Sch=sram2-io[10]
|
||||
#set_property -dict { PACKAGE_PIN W24 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[11] }]; #IO_L20N_T3_A07_D23_14 Sch=sram2-io[11]
|
||||
#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[12] }]; #IO_L24N_T3_A00_D16_14 Sch=sram2-io[12]
|
||||
#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[13] }]; #IO_L24P_T3_A01_D17_14 Sch=sram2-io[13]
|
||||
#set_property -dict { PACKAGE_PIN AD28 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[14] }]; #IO_L11N_T1_SRCC_13 Sch=sram2-io[14]
|
||||
#set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[15] }]; #IO_L11P_T1_SRCC_13 Sch=sram2-io[15]
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[16] }]; #IO_0_14 Sch=sram2-io[16]
|
||||
#set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[17] }]; #IO_L10N_T1_D15_14 Sch=sram2-io[17]
|
||||
#set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[18] }]; #IO_L9P_T1_DQS_14 Sch=sram2-io[18]
|
||||
#set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[19] }]; #IO_L9N_T1_DQS_D13_14 Sch=sram2-io[19]
|
||||
#set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[20] }]; #IO_L7N_T1_D10_14 Sch=sram2-io[20]
|
||||
#set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[21] }]; #IO_L11P_T1_SRCC_14 Sch=sram2-io[21]
|
||||
#set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[22] }]; #IO_L7P_T1_D09_14 Sch=sram2-io[22]
|
||||
#set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[23] }]; #IO_L8P_T1_D11_14 Sch=sram2-io[23]
|
||||
#set_property -dict { PACKAGE_PIN U29 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[24] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram2-io[24]
|
||||
#set_property -dict { PACKAGE_PIN V30 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[25] }]; #IO_L17N_T2_A13_D29_14 Sch=sram2-io[25]
|
||||
#set_property -dict { PACKAGE_PIN U28 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[26] }]; #IO_L13N_T2_MRCC_14 Sch=sram2-io[26]
|
||||
#set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[27] }]; #IO_L2N_T0_13 Sch=sram2-io[27]
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[28] }]; #IO_L6N_T0_D08_VREF_14 Sch=sram2-io[28]
|
||||
#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[29] }]; #IO_L4N_T0_D05_14 Sch=sram2-io[29]
|
||||
#set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[30] }]; #IO_L17P_T2_A14_D30_14 Sch=sram2-io[30]
|
||||
#set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[31] }]; #IO_L4P_T0_13 Sch=sram2-io[31]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN AE29 IOSTANDARD LVCMOS33 } [get_ports { sram_a[0] }]; #IO_L9N_T1_DQS_13 Sch=sram-a[0]
|
||||
#set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { sram_a[1] }]; #IO_L16P_T2_13 Sch=sram-a[1]
|
||||
#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { sram_a[2] }]; #IO_L9P_T1_DQS_13 Sch=sram-a[2]
|
||||
#set_property -dict { PACKAGE_PIN V27 IOSTANDARD LVCMOS33 } [get_ports { sram_a[3] }]; #IO_L16N_T2_A15_D31_14 Sch=sram-a[3]
|
||||
#set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 } [get_ports { sram_a[4] }]; #IO_L12P_T1_MRCC_14 Sch=sram-a[4]
|
||||
#set_property -dict { PACKAGE_PIN U25 IOSTANDARD LVCMOS33 } [get_ports { sram_a[5] }]; #IO_L14N_T2_SRCC_14 Sch=sram-a[5]
|
||||
#set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { sram_a[6] }]; #IO_L11N_T1_SRCC_14 Sch=sram-a[6]
|
||||
#set_property -dict { PACKAGE_PIN R24 IOSTANDARD LVCMOS33 } [get_ports { sram_a[7] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sram-a[7]
|
||||
#set_property -dict { PACKAGE_PIN AK28 IOSTANDARD LVCMOS33 } [get_ports { sram_a[8] }]; #IO_L20N_T3_13 Sch=sram-a[8]
|
||||
#set_property -dict { PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33 } [get_ports { sram_a[9] }]; #IO_L20P_T3_13 Sch=sram-a[9]
|
||||
#set_property -dict { PACKAGE_PIN Y30 IOSTANDARD LVCMOS33 } [get_ports { sram_a[10] }]; #IO_L8P_T1_13 Sch=sram-a[10]
|
||||
#set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { sram_a[11] }]; #IO_L4N_T0_13 Sch=sram-a[11]
|
||||
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { sram_a[12] }]; #IO_L19P_T3_A10_D26_14 Sch=sram-a[12]
|
||||
#set_property -dict { PACKAGE_PIN AG27 IOSTANDARD LVCMOS33 } [get_ports { sram_a[13] }]; #IO_L21P_T3_DQS_13 Sch=sram-a[13]
|
||||
#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { sram_a[14] }]; #IO_L22P_T3_A05_D21_14 Sch=sram-a[14]
|
||||
#set_property -dict { PACKAGE_PIN AG28 IOSTANDARD LVCMOS33 } [get_ports { sram_a[15] }]; #IO_L21N_T3_DQS_13 Sch=sram-a[15]
|
||||
#set_property -dict { PACKAGE_PIN AE26 IOSTANDARD LVCMOS33 } [get_ports { sram_a[16] }]; #IO_25_13 Sch=sram-a[16]
|
||||
#set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 } [get_ports { sram_a[17] }]; #IO_L12N_T1_MRCC_14 Sch=sram-a[17]
|
||||
#set_property -dict { PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33 } [get_ports { sram_a[18] }]; #IO_L17P_T2_13 Sch=sram-a[18]
|
||||
#set_property -dict { PACKAGE_PIN AA30 IOSTANDARD LVCMOS33 } [get_ports { sram_a[19] }]; #IO_L8N_T1_13 Sch=sram-a[19]
|
||||
@@ -0,0 +1,186 @@
|
||||
## This file is a general .xdc for the USB104 A7-100T Rev. B.2
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## 100MHz Clock
|
||||
#set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]; #IO_L12P_T1_MRCC Sch=GCLK100
|
||||
#create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L16N_T2_A15_D31_14 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L17P_T2_A14_D30_14 Sch=btn[1]
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_14 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_14 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L13N_T2_MRCC_14 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L14P_T2_SRCC_14 Sch=led[3]
|
||||
|
||||
## USB UART
|
||||
## Note: Port names are from the perspective of the FPGA.
|
||||
#set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports { uart_rx }]; #IO_L20P_T3_A08_D24_14 Sch=uart_txd_in
|
||||
#set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports { uart_tx }]; #IO_L20N_T3_A07_D23_14 Sch=uart_rxd_out
|
||||
|
||||
## DPTI/DSPI
|
||||
#set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports { prog_spien }]; #IO_L4P_T0_D04_14 Sch=prog_spien
|
||||
#set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports { prog_d[0] }]; #IO_L4N_T0_D05_14 Sch=prog_d[0]/sck
|
||||
#set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports { prog_d[1] }]; #IO_L5P_T0_D06_14 Sch=prog_d[1]/mosi
|
||||
#set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports { prog_d[2] }]; #IO_L5N_T0_D07_14 Sch=prog_d[2]/miso
|
||||
#set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports { prog_d[3] }]; #IO_L6N_T0_D08_14 Sch=prog_d[3]/ss
|
||||
#set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports { prog_d[4] }]; #IO_L7P_T1_D09_14 Sch=prog_d[4]
|
||||
#set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports { prog_d[5] }]; #IO_L7N_T1_D10_14 Sch=prog_d[5]
|
||||
#set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports { prog_d[6] }]; #IO_L8P_T1_D11_14 Sch=prog_d[6]
|
||||
#set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports { prog_d[7] }]; #IO_L8N_T1_D12_14 Sch=prog_d[7]
|
||||
#set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports { prog_oen }]; #IO_L9P_T1_DQS_14 Sch=prog_oen
|
||||
#set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports { prog_siwun }]; #IO_L9N_T1_DQS_D13_14 Sch=prog_siwun
|
||||
#set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports { prog_rxen }]; #IO_L10P_T1_D14_14 Sch=prog_rxen
|
||||
#set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports { prog_txen }]; #IO_L10N_T1_D15_14 Sch=prog_txen
|
||||
#set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports { prog_rdn }]; #IO_L11P_T1_SRCC_14 Sch=prog_rdn
|
||||
#set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports { prog_wrn }]; #IO_L11N_T1_SRCC_14 Sch=prog_wrn
|
||||
#set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports { prog_clko }]; #IO_L12P_T1_MRCC_14 Sch=prog_clko
|
||||
|
||||
## Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }}]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { qspi_sck }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=qspi_sck
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L13P_T2_MRCC_35 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L13N_T2_MRCC_35 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L14P_T2_SRCC_35 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L14N_T2_SRCC_35 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L15P_T2_DQS_35 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L15N_T2_DQS_35 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L16P_T2_35 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L16N_T2_35 Sch=ja[10]
|
||||
|
||||
### Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L7P_T1_AD6P_35 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L10N_T1_AD15N_35 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L10P_T1_AD15P_35 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L7N_T1_AD6N_35 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L8N_T1_AD14N_35 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L8P_T1_AD14P_35 Sch=jb[10]
|
||||
|
||||
### Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L1N_T0_AD4N_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L1P_T0_AD4P_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L2N_T0_AD12N_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L4N_T0_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_AD12P_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L4P_T0_35 Sch=jc[10]
|
||||
|
||||
## SYZYGY Port
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=syzygy_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=syzygy_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[1] }]; #IO_L7P_T1_AD2P_15 Sch=syzygy_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[1] }]; #IO_L7N_T1_AD2N_15 Sch=syzygy_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[2] }]; #IO_L8P_T1_AD10P_15 Sch=syzygy_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[2] }]; #IO_L8N_T1_AD10N_15 Sch=syzygy_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=syzygy_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=syzygy_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[4] }]; #IO_L11P_T1_SRCC_15 Sch=syzygy_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[4] }]; #IO_L11N_T1_SRCC_15 Sch=syzygy_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[5] }]; #IO_L12P_T1_MRCC_15 Sch=syzygy_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[5] }]; #IO_L12N_T1_MRCC_15 Sch=syzygy_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[6] }]; #IO_L20P_T3_A20_15 Sch=syzygy_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[6] }]; #IO_L20N_T3_A19_15 Sch=syzygy_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[7] }]; #IO_L21P_T3_DQS_15 Sch=syzygy_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[7] }]; #IO_L21N_T3_DQS_A18_15 Sch=syzygy_d_n[7]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L19P_T3_A22_15 Sch=syzygy_s[16]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L19N_T3_A21_VREF_15 Sch=syzygy_s[17]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L22P_T3_A17_15 Sch=syzygy_s[18]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L22N_T3_A16_15 Sch=syzygy_s[19]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L23P_T3_FOE_B_15 Sch=syzygy_s[20]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L23N_T3_FWE_B_15 Sch=syzygy_s[21]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L24P_T3_RS1_15 Sch=syzygy_s[22]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L24N_T3_RS0_15 Sch=syzygy_s[23]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L15P_T2_DQS_15 Sch=syzygy_s[24]
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=syzygy_s[25]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L16P_T2_A28_15 Sch=syzygy_s[26]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L16N_T2_A27_15 Sch=syzygy_s[27]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_p2c_clk_p }]; #IO_L13P_T2_MRCC_15 Sch=syzygy_p2c_clk_p
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_p2c_clk_n }]; #IO_L13N_T2_MRCC_15 Sch=syzygy_p2c_clk_n
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_c2p_clk_p }]; #IO_L14P_T2_SRCC_15 Sch=syzygy_c2p_clk_p
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_c2p_clk_n }]; #IO_L14N_T2_SRCC_15 Sch=syzygy_c2p_clk_n
|
||||
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { syzygy_scl }]; #IO_L18P_T2_A12_D28_14 Sch=syzygy_scl
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { syzygy_sda }]; #IO_L18N_T2_A11_D27_14 Sch=syzygy_sda
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { syzygy_det }]; #IO_L19P_T3_A10_D26_14 Sch=syzygy_det
|
||||
|
||||
## Encryption Chip
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L18P_T2_35 Sch=crypto_sda
|
||||
|
||||
# Platform MCU Firmware Reprogramming
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { mcu_rstn }]; #IO_25_14 Sch=mcu_nrst_fpga
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { mcu_cs }]; #IO_L22N_T3_A04_D20_14 Sch=mcu_cs
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { mcu_mosi }]; #IO_L23P_T3_A03_D19_14 Sch=mcu_mosi
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { mcu_miso }]; #IO_L23N_T3_A02_D18_14 Sch=mcu_miso
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { mcu_sck }]; #IO_L24P_T3_A01_D17_14 Sch=mcu_sck
|
||||
|
||||
## Miscellaneous
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[1] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=mcu_rsvd[1]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[2] }]; #IO_L22P_T3_A05_D21_14 Sch=mcu_rsvd[2]
|
||||
|
||||
## DDR3
|
||||
#set_property -dict { PACKAGE_PIN R6 } [get_ports { ddr3_a[0] }]; #IO_L19P_T3_34 Sch=ddr3_a[0]
|
||||
#set_property -dict { PACKAGE_PIN R7 } [get_ports { ddr3_a[1] }]; #IO_L23P_T3_34 Sch=ddr3_a[1]
|
||||
#set_property -dict { PACKAGE_PIN P2 } [get_ports { ddr3_a[10] }]; #IO_L15P_T2_DQS_34 Sch=ddr3_a[10]
|
||||
#set_property -dict { PACKAGE_PIN P5 } [get_ports { ddr3_a[11] }]; #IO_L13N_T2_MRCC_34 Sch=ddr3_a[11]
|
||||
#set_property -dict { PACKAGE_PIN R1 } [get_ports { ddr3_a[12] }]; #IO_L17P_T2_34 Sch=ddr3_a[12]
|
||||
#set_property -dict { PACKAGE_PIN U8 } [get_ports { ddr3_a[13] }]; #IO_25_34 Sch=ddr3_a[13]
|
||||
#set_property -dict { PACKAGE_PIN N6 } [get_ports { ddr3_a[14] }]; #IO_L18N_T2_34 Sch=ddr3_a[14]
|
||||
#set_property -dict { PACKAGE_PIN T6 } [get_ports { ddr3_a[2] }]; #IO_L23N_T3_34 Sch=ddr3_a[2]
|
||||
#set_property -dict { PACKAGE_PIN U7 } [get_ports { ddr3_a[3] }]; #IO_L22P_T3_34 Sch=ddr3_a[3]
|
||||
#set_property -dict { PACKAGE_PIN T1 } [get_ports { ddr3_a[4] }]; #IO_L17N_T2_34 Sch=ddr3_a[4]
|
||||
#set_property -dict { PACKAGE_PIN V7 } [get_ports { ddr3_a[5] }]; #IO_L20P_T3_34 Sch=ddr3_a[5]
|
||||
#set_property -dict { PACKAGE_PIN P3 } [get_ports { ddr3_a[6] }]; #IO_L14N_T2_SRCC_34 Sch=ddr3_a[6]
|
||||
#set_property -dict { PACKAGE_PIN T8 } [get_ports { ddr3_a[7] }]; #IO_L24N_T3_34 Sch=ddr3_a[7]
|
||||
#set_property -dict { PACKAGE_PIN M6 } [get_ports { ddr3_a[8] }]; #IO_L18P_T2_34 Sch=ddr3_a[8]
|
||||
#set_property -dict { PACKAGE_PIN R8 } [get_ports { ddr3_a[9] }]; #IO_L24P_T3_34 Sch=ddr3_a[9]
|
||||
#set_property -dict { PACKAGE_PIN V6 } [get_ports { ddr3_ba[0] }]; #IO_L20N_T3_34 Sch=ddr3_ba[0]
|
||||
#set_property -dict { PACKAGE_PIN R2 } [get_ports { ddr3_ba[1] }]; #IO_L15N_T2_DQS_34 Sch=ddr3_ba[1]
|
||||
#set_property -dict { PACKAGE_PIN R5 } [get_ports { ddr3_ba[2] }]; #IO_L19N_T3_VREF_34 Sch=ddr3_ba[2]
|
||||
#set_property -dict { PACKAGE_PIN N4 } [get_ports { ddr3_cas }]; #IO_L16N_T2_34 Sch=ddr3_cas
|
||||
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVDS } [get_ports { ddr3_ck_n }]; #IO_L21N_T3_DQS_34 Sch=ddr3_ck_n
|
||||
#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVDS } [get_ports { ddr3_ck_p }]; #IO_L21P_T3_DQS_34 Sch=ddr3_ck_p
|
||||
#set_property -dict { PACKAGE_PIN N5 } [get_ports { ddr3_cke[0] }]; #IO_L13P_T2_MRCC_34 Sch=ddr3_cke[0]
|
||||
#set_property -dict { PACKAGE_PIN R3 } [get_ports { ddr3_d[0] }]; #IO_L11P_T1_SRCC_34 Sch=ddr3_d[0]
|
||||
#set_property -dict { PACKAGE_PIN V1 } [get_ports { ddr3_d[1] }]; #IO_L7N_T1_34 Sch=ddr3_d[1]
|
||||
#set_property -dict { PACKAGE_PIN M2 } [get_ports { ddr3_d[10] }]; #IO_L4N_T0_34 Sch=ddr3_d[10]
|
||||
#set_property -dict { PACKAGE_PIN L4 } [get_ports { ddr3_d[11] }]; #IO_L5N_T0_34 Sch=ddr3_d[11]
|
||||
#set_property -dict { PACKAGE_PIN L6 } [get_ports { ddr3_d[12] }]; #IO_L6P_T0_34 Sch=ddr3_d[12]
|
||||
#set_property -dict { PACKAGE_PIN K3 } [get_ports { ddr3_d[13] }]; #IO_L2P_T0_34 Sch=ddr3_d[13]
|
||||
#set_property -dict { PACKAGE_PIN M1 } [get_ports { ddr3_d[14] }]; #IO_L1N_T0_34 Sch=ddr3_d[14]
|
||||
#set_property -dict { PACKAGE_PIN K5 } [get_ports { ddr3_d[15] }]; #IO_L5P_T0_34 Sch=ddr3_d[15]
|
||||
#set_property -dict { PACKAGE_PIN T3 } [get_ports { ddr3_d[2] }]; #IO_L11N_T1_SRCC_34 Sch=ddr3_d[2]
|
||||
#set_property -dict { PACKAGE_PIN U4 } [get_ports { ddr3_d[3] }]; #IO_L8P_T1_34 Sch=ddr3_d[3]
|
||||
#set_property -dict { PACKAGE_PIN U3 } [get_ports { ddr3_d[4] }]; #IO_L8N_T1_34 Sch=ddr3_d[4]
|
||||
#set_property -dict { PACKAGE_PIN V5 } [get_ports { ddr3_d[5] }]; #IO_L10P_T1_34 Sch=ddr3_d[5]
|
||||
#set_property -dict { PACKAGE_PIN T5 } [get_ports { ddr3_d[6] }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_d[6]
|
||||
#set_property -dict { PACKAGE_PIN V4 } [get_ports { ddr3_d[7] }]; #IO_L10N_T1_34 Sch=ddr3_d[7]
|
||||
#set_property -dict { PACKAGE_PIN M3 } [get_ports { ddr3_d[8] }]; #IO_L4P_T0_34 Sch=ddr3_d[8]
|
||||
#set_property -dict { PACKAGE_PIN L3 } [get_ports { ddr3_d[9] }]; #IO_L2N_T0_34 Sch=ddr3_d[9]
|
||||
#set_property -dict { PACKAGE_PIN U1 } [get_ports { ddr3_dm[0] }]; #IO_L7P_T1_34 Sch=ddr3_dm[0]
|
||||
#set_property -dict { PACKAGE_PIN L1 } [get_ports { ddr3_dm[1] }]; #IO_L1P_T0_34 Sch=ddr3_dm[1]
|
||||
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVDS } [get_ports { ddr3_dqs_n[0] }]; #IO_L9N_T1_DQS_34 Sch=ddr3_dqs_n[0]
|
||||
#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVDS } [get_ports { ddr3_dqs_p[0] }]; #IO_L9P_T1_DQS_34 Sch=ddr3_dqs_p[0]
|
||||
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVDS } [get_ports { ddr3_dqs_n[1] }]; #IO_L3N_T0_DQS_34 Sch=ddr3_dqs_n[1]
|
||||
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVDS } [get_ports { ddr3_dqs_p[1] }]; #IO_L3P_T0_DQS_34 Sch=ddr3_dqs_p[1]
|
||||
#set_property -dict { PACKAGE_PIN P4 } [get_ports { ddr3_odt }]; #IO_L14P_T2_SRCC_34 Sch=ddr3_odt
|
||||
#set_property -dict { PACKAGE_PIN M4 } [get_ports { ddr3_ras }]; #IO_L16P_T2_34 Sch=ddr3_ras
|
||||
#set_property -dict { PACKAGE_PIN K6 } [get_ports { ddr3_reset }]; #IO_0_34 Sch=ddr3_reset
|
||||
#set_property -dict { PACKAGE_PIN U6 } [get_ports { ddr3_we }]; #IO_L22N_T3_34 Sch=ddr3_we
|
||||
|
||||
## Bitstream Settings
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
@@ -0,0 +1,375 @@
|
||||
# ----------------------------------------------------------------------------
|
||||
# _____
|
||||
# / \
|
||||
# /____ \____
|
||||
# / \===\ \==/
|
||||
# /___\===\___\/ AVNET Design Resource Center
|
||||
# \======/ www.em.avnet.com/drc
|
||||
# \====/
|
||||
# ----------------------------------------------------------------------------
|
||||
#
|
||||
# Created With Avnet UCF Generator V0.4.0
|
||||
# Date: Saturday, June 30, 2012
|
||||
# Time: 12:18:55 AM
|
||||
#
|
||||
# This design is the property of Avnet. Publication of this
|
||||
# design is not authorized without written consent from Avnet.
|
||||
#
|
||||
# Please direct any questions to:
|
||||
# ZedBoard.org Community Forums
|
||||
# http://www.zedboard.org
|
||||
#
|
||||
# Disclaimer:
|
||||
# Avnet, Inc. makes no warranty for the use of this code or design.
|
||||
# This code is provided "As Is". Avnet, Inc assumes no responsibility for
|
||||
# any errors, which may appear in this code, nor does it make a commitment
|
||||
# to update the information contained herein. Avnet, Inc specifically
|
||||
# disclaims any implied warranties of fitness for a particular purpose.
|
||||
# Copyright(c) 2012 Avnet, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 10 August 2012
|
||||
# IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V,
|
||||
# 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings.
|
||||
# By default, Vadj is expected to be set to 1.8V but if a different
|
||||
# voltage is used for a particular design, then the corresponding IO
|
||||
# standard within this UCF should also be updated to reflect the actual
|
||||
# Vadj jumper selection.
|
||||
#
|
||||
# 09 September 2012
|
||||
# Net names are not allowed to contain hyphen characters '-' since this
|
||||
# is not a legal VHDL87 or Verilog character within an identifier.
|
||||
# HDL net names are adjusted to contain no hyphen characters '-' but
|
||||
# rather use underscore '_' characters. Comment net name with the hyphen
|
||||
# characters will remain in place since these are intended to match the
|
||||
# schematic net names in order to better enable schematic search.
|
||||
#
|
||||
# 17 April 2014
|
||||
# Pin constraint for toggle switch SW7 was corrected to M15 location.
|
||||
#
|
||||
# 16 April 2015
|
||||
# Corrected the way that entire banks are assigned to a particular IO
|
||||
# standard so that it works with more recent versions of Vivado Design
|
||||
# Suite and moved the IO standard constraints to the end of the file
|
||||
# along with some better organization and notes like we do with our SOMs.
|
||||
#
|
||||
# 6 June 2016
|
||||
# Corrected error in signal name for package pin N19 (FMC Expansion Connector)
|
||||
#
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Audio Codec - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}]; # "AC-ADR0"
|
||||
#set_property PACKAGE_PIN Y5 [get_ports {AC_ADR1}]; # "AC-ADR1"
|
||||
#set_property PACKAGE_PIN Y8 [get_ports {SDATA_O}]; # "AC-GPIO0"
|
||||
#set_property PACKAGE_PIN AA7 [get_ports {SDATA_I}]; # "AC-GPIO1"
|
||||
#set_property PACKAGE_PIN AA6 [get_ports {BCLK_O}]; # "AC-GPIO2"
|
||||
#set_property PACKAGE_PIN Y6 [get_ports {LRCLK_O}]; # "AC-GPIO3"
|
||||
#set_property PACKAGE_PIN AB2 [get_ports {MCLK_O}]; # "AC-MCLK"
|
||||
#set_property PACKAGE_PIN AB4 [get_ports {iic_rtl_scl_io}]; # "AC-SCK"
|
||||
#set_property PACKAGE_PIN AB5 [get_ports {iic_rtl_sda_io}]; # "AC-SDA"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Clock Source - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN Y9 [get_ports {GCLK}]; # "GCLK"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JA Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN Y11 [get_ports {JA1}]; # "JA1"
|
||||
#set_property PACKAGE_PIN AA8 [get_ports {JA10}]; # "JA10"
|
||||
#set_property PACKAGE_PIN AA11 [get_ports {JA2}]; # "JA2"
|
||||
#set_property PACKAGE_PIN Y10 [get_ports {JA3}]; # "JA3"
|
||||
#set_property PACKAGE_PIN AA9 [get_ports {JA4}]; # "JA4"
|
||||
#set_property PACKAGE_PIN AB11 [get_ports {JA7}]; # "JA7"
|
||||
#set_property PACKAGE_PIN AB10 [get_ports {JA8}]; # "JA8"
|
||||
#set_property PACKAGE_PIN AB9 [get_ports {JA9}]; # "JA9"
|
||||
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JB Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN W12 [get_ports {JB1}]; # "JB1"
|
||||
#set_property PACKAGE_PIN W11 [get_ports {JB2}]; # "JB2"
|
||||
#set_property PACKAGE_PIN V10 [get_ports {JB3}]; # "JB3"
|
||||
#set_property PACKAGE_PIN W8 [get_ports {JB4}]; # "JB4"
|
||||
#set_property PACKAGE_PIN V12 [get_ports {JB7}]; # "JB7"
|
||||
#set_property PACKAGE_PIN W10 [get_ports {JB8}]; # "JB8"
|
||||
#set_property PACKAGE_PIN V9 [get_ports {JB9}]; # "JB9"
|
||||
#set_property PACKAGE_PIN V8 [get_ports {JB10}]; # "JB10"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JC Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN AB6 [get_ports {JC1_N}]; # "JC1_N"
|
||||
#set_property PACKAGE_PIN AB7 [get_ports {JC1_P}]; # "JC1_P"
|
||||
#set_property PACKAGE_PIN AA4 [get_ports {JC2_N}]; # "JC2_N"
|
||||
#set_property PACKAGE_PIN Y4 [get_ports {JC2_P}]; # "JC2_P"
|
||||
#set_property PACKAGE_PIN T6 [get_ports {JC3_N}]; # "JC3_N"
|
||||
#set_property PACKAGE_PIN R6 [get_ports {JC3_P}]; # "JC3_P"
|
||||
#set_property PACKAGE_PIN U4 [get_ports {JC4_N}]; # "JC4_N"
|
||||
#set_property PACKAGE_PIN T4 [get_ports {JC4_P}]; # "JC4_P"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JD Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN W7 [get_ports {JD1_N}]; # "JD1_N"
|
||||
#set_property PACKAGE_PIN V7 [get_ports {JD1_P}]; # "JD1_P"
|
||||
#set_property PACKAGE_PIN V4 [get_ports {JD2_N}]; # "JD2_N"
|
||||
#set_property PACKAGE_PIN V5 [get_ports {JD2_P}]; # "JD2_P"
|
||||
#set_property PACKAGE_PIN W5 [get_ports {JD3_N}]; # "JD3_N"
|
||||
#set_property PACKAGE_PIN W6 [get_ports {JD3_P}]; # "JD3_P"
|
||||
#set_property PACKAGE_PIN U5 [get_ports {JD4_N}]; # "JD4_N"
|
||||
#set_property PACKAGE_PIN U6 [get_ports {JD4_P}]; # "JD4_P"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# OLED Display - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN U10 [get_ports {OLED_DC}]; # "OLED-DC"
|
||||
#set_property PACKAGE_PIN U9 [get_ports {OLED_RES}]; # "OLED-RES"
|
||||
#set_property PACKAGE_PIN AB12 [get_ports {OLED_SCLK}]; # "OLED-SCLK"
|
||||
#set_property PACKAGE_PIN AA12 [get_ports {OLED_SDIN}]; # "OLED-SDIN"
|
||||
#set_property PACKAGE_PIN U11 [get_ports {OLED_VBAT}]; # "OLED-VBAT"
|
||||
#set_property PACKAGE_PIN U12 [get_ports {OLED_VDD}]; # "OLED-VDD"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# HDMI Output - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN W18 [get_ports {HD_CLK}]; # "HD-CLK"
|
||||
#set_property PACKAGE_PIN Y13 [get_ports {HD_D0}]; # "HD-D0"
|
||||
#set_property PACKAGE_PIN AA13 [get_ports {HD_D1}]; # "HD-D1"
|
||||
#set_property PACKAGE_PIN W13 [get_ports {HD_D10}]; # "HD-D10"
|
||||
#set_property PACKAGE_PIN W15 [get_ports {HD_D11}]; # "HD-D11"
|
||||
#set_property PACKAGE_PIN V15 [get_ports {HD_D12}]; # "HD-D12"
|
||||
#set_property PACKAGE_PIN U17 [get_ports {HD_D13}]; # "HD-D13"
|
||||
#set_property PACKAGE_PIN V14 [get_ports {HD_D14}]; # "HD-D14"
|
||||
#set_property PACKAGE_PIN V13 [get_ports {HS_D15}]; # "HD-D15"
|
||||
#set_property PACKAGE_PIN AA14 [get_ports {HD_D2}]; # "HD-D2"
|
||||
#set_property PACKAGE_PIN Y14 [get_ports {HD_D3}]; # "HD-D3"
|
||||
#set_property PACKAGE_PIN AB15 [get_ports {HD_D4}]; # "HD-D4"
|
||||
#set_property PACKAGE_PIN AB16 [get_ports {HD_D5}]; # "HD-D5"
|
||||
#set_property PACKAGE_PIN AA16 [get_ports {HD_D6}]; # "HD-D6"
|
||||
#set_property PACKAGE_PIN AB17 [get_ports {HD_D7}]; # "HD-D7"
|
||||
#set_property PACKAGE_PIN AA17 [get_ports {HD_D8}]; # "HD-D8"
|
||||
#set_property PACKAGE_PIN Y15 [get_ports {HD_D9}]; # "HD-D9"
|
||||
#set_property PACKAGE_PIN U16 [get_ports {HD_DE}]; # "HD-DE"
|
||||
#set_property PACKAGE_PIN V17 [get_ports {HD_HSYNC}]; # "HD-HSYNC"
|
||||
#set_property PACKAGE_PIN W16 [get_ports {HD_INT}]; # "HD-INT"
|
||||
#set_property PACKAGE_PIN AA18 [get_ports {HD_SCL}]; # "HD-SCL"
|
||||
#set_property PACKAGE_PIN Y16 [get_ports {HD_SDA}]; # "HD-SDA"
|
||||
#set_property PACKAGE_PIN U15 [get_ports {HD_SPDIF}]; # "HD-SPDIF"
|
||||
#set_property PACKAGE_PIN Y18 [get_ports {HD_SPDIFO}]; # "HD-SPDIFO"
|
||||
#set_property PACKAGE_PIN W17 [get_ports {HD_VSYNC}]; # "HD-VSYNC"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# User LEDs - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN T22 [get_ports {LD0}]; # "LD0"
|
||||
#set_property PACKAGE_PIN T21 [get_ports {LD1}]; # "LD1"
|
||||
#set_property PACKAGE_PIN U22 [get_ports {LD2}]; # "LD2"
|
||||
#set_property PACKAGE_PIN U21 [get_ports {LD3}]; # "LD3"
|
||||
#set_property PACKAGE_PIN V22 [get_ports {LD4}]; # "LD4"
|
||||
#set_property PACKAGE_PIN W22 [get_ports {LD5}]; # "LD5"
|
||||
#set_property PACKAGE_PIN U19 [get_ports {LD6}]; # "LD6"
|
||||
#set_property PACKAGE_PIN U14 [get_ports {LD7}]; # "LD7"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# VGA Output - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN Y21 [get_ports {VGA_B1}]; # "VGA-B1"
|
||||
#set_property PACKAGE_PIN Y20 [get_ports {VGA_B2}]; # "VGA-B2"
|
||||
#set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}]; # "VGA-B3"
|
||||
#set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}]; # "VGA-B4"
|
||||
#set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}]; # "VGA-G1"
|
||||
#set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}]; # "VGA-G2"
|
||||
#set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}]; # "VGA-G3"
|
||||
#set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}]; # "VGA-G4"
|
||||
#set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}]; # "VGA-HS"
|
||||
#set_property PACKAGE_PIN V20 [get_ports {VGA_R1}]; # "VGA-R1"
|
||||
#set_property PACKAGE_PIN U20 [get_ports {VGA_R2}]; # "VGA-R2"
|
||||
#set_property PACKAGE_PIN V19 [get_ports {VGA_R3}]; # "VGA-R3"
|
||||
#set_property PACKAGE_PIN V18 [get_ports {VGA_R4}]; # "VGA-R4"
|
||||
#set_property PACKAGE_PIN Y19 [get_ports {VGA_VS}]; # "VGA-VS"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# User Push Buttons - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN P16 [get_ports {BTNC}]; # "BTNC"
|
||||
#set_property PACKAGE_PIN R16 [get_ports {BTND}]; # "BTND"
|
||||
#set_property PACKAGE_PIN N15 [get_ports {BTNL}]; # "BTNL"
|
||||
#set_property PACKAGE_PIN R18 [get_ports {BTNR}]; # "BTNR"
|
||||
#set_property PACKAGE_PIN T18 [get_ports {BTNU}]; # "BTNU"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# USB OTG Reset - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN L16 [get_ports {OTG_VBUSOC}]; # "OTG-VBUSOC"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# XADC GIO - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN H15 [get_ports {XADC_GIO0}]; # "XADC-GIO0"
|
||||
#set_property PACKAGE_PIN R15 [get_ports {XADC_GIO1}]; # "XADC-GIO1"
|
||||
#set_property PACKAGE_PIN K15 [get_ports {XADC_GIO2}]; # "XADC-GIO2"
|
||||
#set_property PACKAGE_PIN J15 [get_ports {XADC_GIO3}]; # "XADC-GIO3"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Miscellaneous - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN K16 [get_ports {PUDC_B}]; # "PUDC_B"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## USB OTG Reset - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN G17 [get_ports {OTG_RESETN}]; # "OTG-RESETN"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## User DIP Switches - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN F22 [get_ports {SW0}]; # "SW0"
|
||||
#set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1"
|
||||
#set_property PACKAGE_PIN H22 [get_ports {SW2}]; # "SW2"
|
||||
#set_property PACKAGE_PIN F21 [get_ports {SW3}]; # "SW3"
|
||||
#set_property PACKAGE_PIN H19 [get_ports {SW4}]; # "SW4"
|
||||
#set_property PACKAGE_PIN H18 [get_ports {SW5}]; # "SW5"
|
||||
#set_property PACKAGE_PIN H17 [get_ports {SW6}]; # "SW6"
|
||||
#set_property PACKAGE_PIN M15 [get_ports {SW7}]; # "SW7"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## XADC AD Channels - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN E16 [get_ports {AD0N_R}]; # "XADC-AD0N-R"
|
||||
#set_property PACKAGE_PIN F16 [get_ports {AD0P_R}]; # "XADC-AD0P-R"
|
||||
#set_property PACKAGE_PIN D17 [get_ports {AD8N_N}]; # "XADC-AD8N-R"
|
||||
#set_property PACKAGE_PIN D16 [get_ports {AD8P_R}]; # "XADC-AD8P-R"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 13
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN R7 [get_ports {FMC_SCL}]; # "FMC-SCL"
|
||||
#set_property PACKAGE_PIN U7 [get_ports {FMC_SDA}]; # "FMC-SDA"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 33
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN AB14 [get_ports {FMC_PRSNT}]; # "FMC-PRSNT"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 34
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN L19 [get_ports {FMC_CLK0_N}]; # "FMC-CLK0_N"
|
||||
#set_property PACKAGE_PIN L18 [get_ports {FMC_CLK0_P}]; # "FMC-CLK0_P"
|
||||
#set_property PACKAGE_PIN M20 [get_ports {FMC_LA00_CC_N}]; # "FMC-LA00_CC_N"
|
||||
#set_property PACKAGE_PIN M19 [get_ports {FMC_LA00_CC_P}]; # "FMC-LA00_CC_P"
|
||||
#set_property PACKAGE_PIN N20 [get_ports {FMC_LA01_CC_N}]; # "FMC-LA01_CC_N"
|
||||
#set_property PACKAGE_PIN N19 [get_ports {FMC_LA01_CC_P}]; # "FMC-LA01_CC_P" - corrected 6/6/16 GE
|
||||
#set_property PACKAGE_PIN P18 [get_ports {FMC_LA02_N}]; # "FMC-LA02_N"
|
||||
#set_property PACKAGE_PIN P17 [get_ports {FMC_LA02_P}]; # "FMC-LA02_P"
|
||||
#set_property PACKAGE_PIN P22 [get_ports {FMC_LA03_N}]; # "FMC-LA03_N"
|
||||
#set_property PACKAGE_PIN N22 [get_ports {FMC_LA03_P}]; # "FMC-LA03_P"
|
||||
#set_property PACKAGE_PIN M22 [get_ports {FMC_LA04_N}]; # "FMC-LA04_N"
|
||||
#set_property PACKAGE_PIN M21 [get_ports {FMC_LA04_P}]; # "FMC-LA04_P"
|
||||
#set_property PACKAGE_PIN K18 [get_ports {FMC_LA05_N}]; # "FMC-LA05_N"
|
||||
#set_property PACKAGE_PIN J18 [get_ports {FMC_LA05_P}]; # "FMC-LA05_P"
|
||||
#set_property PACKAGE_PIN L22 [get_ports {FMC_LA06_N}]; # "FMC-LA06_N"
|
||||
#set_property PACKAGE_PIN L21 [get_ports {FMC_LA06_P}]; # "FMC-LA06_P"
|
||||
#set_property PACKAGE_PIN T17 [get_ports {FMC_LA07_N}]; # "FMC-LA07_N"
|
||||
#set_property PACKAGE_PIN T16 [get_ports {FMC_LA07_P}]; # "FMC-LA07_P"
|
||||
#set_property PACKAGE_PIN J22 [get_ports {FMC_LA08_N}]; # "FMC-LA08_N"
|
||||
#set_property PACKAGE_PIN J21 [get_ports {FMC_LA08_P}]; # "FMC-LA08_P"
|
||||
#set_property PACKAGE_PIN R21 [get_ports {FMC_LA09_N}]; # "FMC-LA09_N"
|
||||
#set_property PACKAGE_PIN R20 [get_ports {FMC_LA09_P}]; # "FMC-LA09_P"
|
||||
#set_property PACKAGE_PIN T19 [get_ports {FMC_LA10_N}]; # "FMC-LA10_N"
|
||||
#set_property PACKAGE_PIN R19 [get_ports {FMC_LA10_P}]; # "FMC-LA10_P"
|
||||
#set_property PACKAGE_PIN N18 [get_ports {FMC_LA11_N}]; # "FMC-LA11_N"
|
||||
#set_property PACKAGE_PIN N17 [get_ports {FMC_LA11_P}]; # "FMC-LA11_P"
|
||||
#set_property PACKAGE_PIN P21 [get_ports {FMC_LA12_N}]; # "FMC-LA12_N"
|
||||
#set_property PACKAGE_PIN P20 [get_ports {FMC_LA12_P}]; # "FMC-LA12_P"
|
||||
#set_property PACKAGE_PIN M17 [get_ports {FMC_LA13_N}]; # "FMC-LA13_N"
|
||||
#set_property PACKAGE_PIN L17 [get_ports {FMC_LA13_P}]; # "FMC-LA13_P"
|
||||
#set_property PACKAGE_PIN K20 [get_ports {FMC_LA14_N}]; # "FMC-LA14_N"
|
||||
#set_property PACKAGE_PIN K19 [get_ports {FMC_LA14_P}]; # "FMC-LA14_P"
|
||||
#set_property PACKAGE_PIN J17 [get_ports {FMC_LA15_N}]; # "FMC-LA15_N"
|
||||
#set_property PACKAGE_PIN J16 [get_ports {FMC_LA15_P}]; # "FMC-LA15_P"
|
||||
#set_property PACKAGE_PIN K21 [get_ports {FMC_LA16_N}]; # "FMC-LA16_N"
|
||||
#set_property PACKAGE_PIN J20 [get_ports {FMC_LA16_P}]; # "FMC-LA16_P"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN C19 [get_ports {FMC_CLK1_N}]; # "FMC-CLK1_N"
|
||||
#set_property PACKAGE_PIN D18 [get_ports {FMC_CLK1_P}]; # "FMC-CLK1_P"
|
||||
#set_property PACKAGE_PIN B20 [get_ports {FMC_LA17_CC_N}]; # "FMC-LA17_CC_N"
|
||||
#set_property PACKAGE_PIN B19 [get_ports {FMC_LA17_CC_P}]; # "FMC-LA17_CC_P"
|
||||
#set_property PACKAGE_PIN C20 [get_ports {FMC_LA18_CC_N}]; # "FMC-LA18_CC_N"
|
||||
#set_property PACKAGE_PIN D20 [get_ports {FMC_LA18_CC_P}]; # "FMC-LA18_CC_P"
|
||||
#set_property PACKAGE_PIN G16 [get_ports {FMC_LA19_N}]; # "FMC-LA19_N"
|
||||
#set_property PACKAGE_PIN G15 [get_ports {FMC_LA19_P}]; # "FMC-LA19_P"
|
||||
#set_property PACKAGE_PIN G21 [get_ports {FMC_LA20_N}]; # "FMC-LA20_N"
|
||||
#set_property PACKAGE_PIN G20 [get_ports {FMC_LA20_P}]; # "FMC-LA20_P"
|
||||
#set_property PACKAGE_PIN E20 [get_ports {FMC_LA21_N}]; # "FMC-LA21_N"
|
||||
#set_property PACKAGE_PIN E19 [get_ports {FMC_LA21_P}]; # "FMC-LA21_P"
|
||||
#set_property PACKAGE_PIN F19 [get_ports {FMC_LA22_N}]; # "FMC-LA22_N"
|
||||
#set_property PACKAGE_PIN G19 [get_ports {FMC_LA22_P}]; # "FMC-LA22_P"
|
||||
#set_property PACKAGE_PIN D15 [get_ports {FMC_LA23_N}]; # "FMC-LA23_N"
|
||||
#set_property PACKAGE_PIN E15 [get_ports {FMC_LA23_P}]; # "FMC-LA23_P"
|
||||
#set_property PACKAGE_PIN A19 [get_ports {FMC_LA24_N}]; # "FMC-LA24_N"
|
||||
#set_property PACKAGE_PIN A18 [get_ports {FMC_LA24_P}]; # "FMC-LA24_P"
|
||||
#set_property PACKAGE_PIN C22 [get_ports {FMC_LA25_N}]; # "FMC-LA25_N"
|
||||
#set_property PACKAGE_PIN D22 [get_ports {FMC_LA25_P}]; # "FMC-LA25_P"
|
||||
#set_property PACKAGE_PIN E18 [get_ports {FMC_LA26_N}]; # "FMC-LA26_N"
|
||||
#set_property PACKAGE_PIN F18 [get_ports {FMC_LA26_P}]; # "FMC-LA26_P"
|
||||
#set_property PACKAGE_PIN D21 [get_ports {FMC_LA27_N}]; # "FMC-LA27_N"
|
||||
#set_property PACKAGE_PIN E21 [get_ports {FMC_LA27_P}]; # "FMC-LA27_P"
|
||||
#set_property PACKAGE_PIN A17 [get_ports {FMC_LA28_N}]; # "FMC-LA28_N"
|
||||
#set_property PACKAGE_PIN A16 [get_ports {FMC_LA28_P}]; # "FMC-LA28_P"
|
||||
#set_property PACKAGE_PIN C18 [get_ports {FMC_LA29_N}]; # "FMC-LA29_N"
|
||||
#set_property PACKAGE_PIN C17 [get_ports {FMC_LA29_P}]; # "FMC-LA29_P"
|
||||
#set_property PACKAGE_PIN B15 [get_ports {FMC_LA30_N}]; # "FMC-LA30_N"
|
||||
#set_property PACKAGE_PIN C15 [get_ports {FMC_LA30_P}]; # "FMC-LA30_P"
|
||||
#set_property PACKAGE_PIN B17 [get_ports {FMC_LA31_N}]; # "FMC-LA31_N"
|
||||
#set_property PACKAGE_PIN B16 [get_ports {FMC_LA31_P}]; # "FMC-LA31_P"
|
||||
#set_property PACKAGE_PIN A22 [get_ports {FMC_LA32_N}]; # "FMC-LA32_N"
|
||||
#set_property PACKAGE_PIN A21 [get_ports {FMC_LA32_P}]; # "FMC-LA32_P"
|
||||
#set_property PACKAGE_PIN B22 [get_ports {FMC_LA33_N}]; # "FMC-LA33_N"
|
||||
#set_property PACKAGE_PIN B21 [get_ports {FMC_LA33_P}]; # "FMC-LA33_P"
|
||||
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# IOSTANDARD Constraints
|
||||
#
|
||||
# Note that these IOSTANDARD constraints are applied to all IOs currently
|
||||
# assigned within an I/O bank. If these IOSTANDARD constraints are
|
||||
# evaluated prior to other PACKAGE_PIN constraints being applied, then
|
||||
# the IOSTANDARD specified will likely not be applied properly to those
|
||||
# pins. Therefore, bank wide IOSTANDARD constraints should be placed
|
||||
# within the XDC file in a location that is evaluated AFTER all
|
||||
# PACKAGE_PIN constraints within the target bank have been evaluated.
|
||||
#
|
||||
# Un-comment one or more of the following IOSTANDARD constraints according to
|
||||
# the bank pin assignments that are required within a design.
|
||||
# ----------------------------------------------------------------------------
|
||||
|
||||
# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard.
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
|
||||
|
||||
# Set the bank voltage for IO Bank 34 to 1.8V by default.
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
|
||||
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 34]];
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
|
||||
|
||||
# Set the bank voltage for IO Bank 35 to 1.8V by default.
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
|
||||
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 35]];
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
|
||||
|
||||
# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
|
||||
@@ -0,0 +1,146 @@
|
||||
## This file is a general .xdc for the ZYBO Rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used signals according to the project
|
||||
|
||||
|
||||
##Clock signal
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
|
||||
|
||||
|
||||
##Switches
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3
|
||||
|
||||
|
||||
##Buttons
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3
|
||||
|
||||
|
||||
##LEDs
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3
|
||||
|
||||
|
||||
##I2S Audio Codec
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC
|
||||
|
||||
|
||||
##Audio Codec/external EEPROM IIC bus
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA
|
||||
|
||||
|
||||
##Additional Ethernet signals
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B
|
||||
|
||||
|
||||
##HDMI Signals
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA
|
||||
|
||||
|
||||
##Pmod Header JA (XADC)
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N
|
||||
|
||||
|
||||
##Pmod Header JE
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10
|
||||
|
||||
|
||||
##USB-OTG overcurrent detect pin
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC
|
||||
|
||||
|
||||
##VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS
|
||||
@@ -0,0 +1,198 @@
|
||||
## This file is a general .xdc for the Zybo Z7 Rev. B
|
||||
## It is compatible with the Zybo Z7-20 and Zybo Z7-10
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
##Clock signal
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
|
||||
|
||||
|
||||
##Switches
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
|
||||
|
||||
|
||||
##Buttons
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
|
||||
|
||||
|
||||
##LEDs
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
|
||||
|
||||
|
||||
##RGB LED 5 (Zybo Z7-20 only)
|
||||
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
|
||||
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
|
||||
|
||||
##RGB LED 6
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
|
||||
|
||||
|
||||
##Audio Codec
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
|
||||
|
||||
|
||||
##Additional Ethernet signals
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
|
||||
|
||||
|
||||
##USB-OTG over-current detect pin
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
|
||||
|
||||
|
||||
##Fan (Zybo Z7-20 only)
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
|
||||
|
||||
|
||||
##HDMI RX
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
|
||||
|
||||
##HDMI RX CEC (Zybo Z7-20 only)
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
|
||||
|
||||
|
||||
##HDMI TX
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
|
||||
|
||||
##HDMI TX CEC
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
|
||||
|
||||
|
||||
##Pmod Header JA (XADC)
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
|
||||
|
||||
|
||||
##Pmod Header JB (Zybo Z7-20 only)
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
|
||||
|
||||
|
||||
##Pmod Header JE
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
|
||||
|
||||
|
||||
##Pcam MIPI CSI-2 Connector
|
||||
## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
|
||||
#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
|
||||
#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
|
||||
|
||||
|
||||
##Unloaded Crypto Chip SWI (for future use)
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
|
||||
|
||||
|
||||
##Unconnected Pins (Zybo Z7-20 only)
|
||||
#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
|
||||
#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
|
||||
#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
|
||||
#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
|
||||
#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
|
||||
#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
|
||||
#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
|
||||
#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
|
||||
#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
|
||||
#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
|
||||
#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
|
||||
#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13
|
||||
|
||||
|
||||
Reference in New Issue
Block a user