logic[9:0] Data; | logic[9:0] Data; | ||||
logic SendData; | logic SendData; | ||||
logic TimerMeas; | logic TimerMeas; | ||||
logic Clk; | |||||
logic DataValid; | logic DataValid; | ||||
logic AlarmAmpel; | logic AlarmAmpel; | ||||
logic TasteAktiv; | logic TasteAktiv; | ||||
output SendData, | output SendData, | ||||
output TimerEN | output TimerEN | ||||
); | ); | ||||
modport timer ( | |||||
input clk, | |||||
input Taste, | |||||
input TimerEN, | |||||
output ReadTemp, | |||||
output TasteAktiv | |||||
); | |||||
/* | |||||
module parallelport wird in top level design | |||||
ohne modport verbunden, da inEndOfConv nicht | |||||
Teil des Bus_if ist. | |||||
*/ | |||||
endinterface //Bus | endinterface //Bus |