kuntzschcl/ESY1_Projekt_2023
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spi aenderungen

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hans
2023-06-15 14:52:43 +02:00
parent 8e3fb73bb0
commit 24a79c2647
25 changed files with 299 additions and 389 deletions
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uebung_projekt/transcript
+72 -188
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@@ -12,16 +12,18 @@
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
#
# create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work
# Modifying modelsim.ini
#
# Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# Start time: 14:45:50 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if
# -- Compiling interface dip_if
@@ -30,19 +32,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
#
# Top level modules:
# --none--
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# Start time: 14:45:50 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli
#
# Top level modules:
# stimuli
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# Start time: 14:45:50 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top
# -- Compiling interface bus
@@ -51,66 +53,66 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
#
# Top level modules:
# top
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# Start time: 14:45:50 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb
#
# Top level modules:
# top_tb
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# Start time: 14:45:51 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer
#
# Top level modules:
# timer
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# Start time: 14:45:51 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master
#
# Top level modules:
# SPI_Master
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# Start time: 14:45:51 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS
#
# Top level modules:
# SPI_Master_With_Single_CS
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# Start time: 14:45:51 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM
#
# Top level modules:
# FRAM
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# Start time: 14:45:51 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi
#
# Top level modules:
# spi
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# Run Simulation
# vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:04:53 on Jun 15,2023
# Start time: 14:45:51 on Jun 15,2023
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)".
# Loading sv_std.std
@@ -129,10 +131,11 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# Loading work.SPI_Master(fast)
# Loading work.parallelport(fast)
# Loading work.stimuli(fast)
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
#
# create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work
@@ -140,7 +143,7 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
#
# Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if
# -- Compiling interface dip_if
@@ -149,19 +152,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
#
# Top level modules:
# --none--
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli
#
# Top level modules:
# stimuli
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top
# -- Compiling interface bus
@@ -170,68 +173,68 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
#
# Top level modules:
# top
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb
#
# Top level modules:
# top_tb
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer
#
# Top level modules:
# timer
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master
#
# Top level modules:
# SPI_Master
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS
#
# Top level modules:
# SPI_Master_With_Single_CS
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM
#
# Top level modules:
# FRAM
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi
#
# Top level modules:
# spi
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# Run Simulation
# End time: 14:11:55 on Jun 15,2023, Elapsed time: 0:07:02
# Errors: 12, Warnings: 1
# End time: 14:48:18 on Jun 15,2023, Elapsed time: 0:02:27
# Errors: 3, Warnings: 2
# vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:11:55 on Jun 15,2023
# Start time: 14:48:18 on Jun 15,2023
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading sv_std.std
# Loading work.top_tb(fast)
@@ -249,14 +252,13 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# Loading work.SPI_Master(fast)
# Loading work.parallelport(fast)
# Loading work.stimuli(fast)
# Can't move the Now cursor.
# Can't move the Now cursor.
add wave -position insertpoint \
sim:/top_tb/t1/f/mosi
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
sim:/top_tb/t1/fpga_bus/spi_read
do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
#
# create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work
@@ -264,7 +266,7 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
#
# Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023
# Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if
# -- Compiling interface dip_if
@@ -273,19 +275,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
#
# Top level modules:
# --none--
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023
# Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli
#
# Top level modules:
# stimuli
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023
# Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top
# -- Compiling interface bus
@@ -294,189 +296,69 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
#
# Top level modules:
# top
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023
# Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb
#
# Top level modules:
# top_tb
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023
# Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer
#
# Top level modules:
# timer
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023
# Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master
#
# Top level modules:
# SPI_Master
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023
# Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS
#
# Top level modules:
# SPI_Master_With_Single_CS
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023
# Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM
#
# Top level modules:
# FRAM
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023
# Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi
#
# Top level modules:
# spi
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# Run Simulation
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:07:06
# Errors: 12, Warnings: 1
# End time: 14:51:07 on Jun 15,2023, Elapsed time: 0:02:49
# Errors: 1, Warnings: 2
# vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:19:01 on Jun 15,2023
# ** Note: (vsim-8009) Loading existing optimized design _opt
# Loading sv_std.std
# Loading work.top_tb(fast)
# Loading work.led_if(fast)
# Loading work.dip_if(fast)
# Loading work.fram_if(fast)
# Loading work.clock_if(fast)
# Loading work.top(fast)
# Loading work.bus(fast)
# Loading work.timer(fast)
# Loading work.steuerung(fast)
# Loading work.spi(fast)
# Loading work.FRAM(fast)
# Loading work.SPI_Master_With_Single_CS(fast)
# Loading work.SPI_Master(fast)
# Loading work.parallelport(fast)
# Loading work.stimuli(fast)
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
#
# create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work
# Modifying modelsim.ini
#
# Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if
# -- Compiling interface dip_if
# -- Compiling interface fram_if
# -- Compiling interface clock_if
#
# Top level modules:
# --none--
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli
#
# Top level modules:
# stimuli
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top
# -- Compiling interface bus
# -- Compiling module parallelport
# -- Compiling module steuerung
#
# Top level modules:
# top
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb
#
# Top level modules:
# top_tb
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer
#
# Top level modules:
# timer
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master
#
# Top level modules:
# SPI_Master
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS
#
# Top level modules:
# SPI_Master_With_Single_CS
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM
#
# Top level modules:
# FRAM
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:08 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi
#
# Top level modules:
# spi
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# Run Simulation
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:03:07
# Errors: 5, Warnings: 1
# vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:22:08 on Jun 15,2023
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Start time: 14:51:07 on Jun 15,2023
# ** Note: (vsim-8009) Loading existing optimized design _opt1
# Loading sv_std.std
# Loading work.top_tb(fast)
# Loading work.led_if(fast)
@@ -493,3 +375,5 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# Loading work.SPI_Master(fast)
# Loading work.parallelport(fast)
# Loading work.stimuli(fast)
# End time: 14:52:23 on Jun 15,2023, Elapsed time: 0:01:16
# Errors: 3, Warnings: 0