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Author SHA1 Message Date
hans 0fb43a40c1 Merge branch 'master' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2023 2023-06-15 14:53:31 +02:00
hans 24a79c2647 spi aenderungen 2023-06-15 14:52:43 +02:00
boeseni82626 4e14cf9bf6 Dateien hochladen nach „Ampelansteuerung“ 2023-06-15 12:47:05 +00:00
boeseni82626 0fc4fee4b3 „Ampelansteuerung/testbench.sv“ löschen 2023-06-15 12:46:37 +00:00
boeseni82626 6f34badb25 „Ampelansteuerung/LED_control.sv“ löschen 2023-06-15 12:46:33 +00:00
boeseni82626 11608814fb „Ampelansteuerung/rgb_led_top.sv“ löschen 2023-06-15 12:46:26 +00:00
hans 8e3fb73bb0 neue aenderung in interface wegen rgbn 2023-06-15 14:42:40 +02:00
30 changed files with 377 additions and 603 deletions
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Ampelansteuerung/LED_control.sv
+12 -12
View File
@@ -64,13 +64,13 @@
module LED_control1 ( module LED_control1 (
// inputs // inputs
input wire clk12M, // 12M clock input wire clk12M, // 12M clock
input wire rst, //Asynchronous reset input wire rst, // Asynchronous reset
input wire [1:0] color_sel, // for selecting color using switches input wire [1:0] color_sel, // for selecting color using switches
input wire RGB_Blink_En, //Enabling Blink input wire rw, // read or write select switch
//outputs //outputs
output reg red_pwm, // Red output reg red_pwm, // Red
output reg blu_pwm, // Blue output reg blu_pwm, // Blue
output reg grn_pwm // Green output reg grn_pwm // Green
); );
@@ -160,16 +160,16 @@ always @ (posedge clk24M or posedge rst)
Brightness_s <= 4'b0111; Brightness_s <= 4'b0111;
BreatheRamp_s <= 4'b0000; BreatheRamp_s <= 4'b0000;
BlinkRate_s <= 4'b0101; BlinkRate_s <= 4'b0101;
end else if(!RGB_Blink_En) begin //end else if(!RGB_Blink_En) begin //TODO ReadWrite Difference
RGB_color_s <= RGB_color ; //RGB_color_s <= RGB_color ;
Brightness_s <= Brightness ; //Brightness_s <= Brightness ;
BreatheRamp_s <= 4'b0000 ; //BreatheRamp_s <= 4'b0000 ;
BlinkRate_s <= 4'b0000 ; //BlinkRate_s <= 4'b0000 ;
end else begin end else begin
RGB_color_s <= RGB_color ; RGB_color_s <= RGB_color ;
Brightness_s <= Brightness ; Brightness_s <= Brightness ;
BreatheRamp_s <= BreatheRamp ; BreatheRamp_s <= 4'b0000 ;
BlinkRate_s <= BlinkRate ; BlinkRate_s <= 4'b0000 ;
end end
Ampelansteuerung/rgb_led_top.sv
-70
View File
@@ -1,70 +0,0 @@
module led_top (
input wire clk12M,
input wire rst,
input wire [1:0] color_sel,
input wire RGB_Blink_En,
output reg REDn,
output reg BLUn,
output reg GRNn,
output reg RED,
output reg BLU,
output reg GRN
);
wire red_pwm;
wire grn_pwm;
wire blu_pwm;
//parameter on_hi = 2'b10;
//parameter on_lo = 2'b01;
//parameter off = 2'b00;
//parameter LED_OFF = 2'b00;
//parameter RAMP_UP = 2'b01;
//parameter LED_ON = 2'b10;
//parameter RAMP_DOWN = 2'b11;
//parameter on_max_cnt = 28'h16E35ED; // 1 sec steady
//parameter [3:0] Brightness=4'b0111; //50% Brightness
//parameter [3:0] BreatheRamp=4'b0110; //2x
//parameter [3:0] BlinkRate=4'b0101; //1sec
//parameter string RGB0_CURRENT = "0b111111";
//parameter string RGB1_CURRENT = "0b111111";
//parameter string RGB2_CURRENT = "0b111111";
defparam U1.on_hi = 2'b10;
defparam U1.on_lo = 2'b01;
defparam U1.off = 2'b00;
defparam U1.LED_OFF = 2'b00;
defparam U1.RAMP_UP = 2'b01;
defparam U1.LED_ON = 2'b10;
defparam U1.RAMP_DOWN = 2'b11;
defparam U1.on_max_cnt = 28'h16E35ED; // 1 sec steady
defparam U1.Brightness = 4'b0111; // 50% Brightness
defparam U1.BreatheRamp = 4'b0110; // 2x
defparam U1.BlinkRate = 4'b0101; // 1 sec
defparam U2.RGB0_CURRENT = "0b111111";
defparam U2.RGB1_CURRENT = "0b111111";
defparam U2.RGB2_CURRENT = "0b111111";
LED_control1 U1 (.clk12M(clk12M),.rst(rst),.color_sel(color_sel),.RGB_Blink_En(RGB_Blink_En),.red_pwm(red_pwm),.blu_pwm(blu_pwm),.grn_pwm(grn_pwm));
RGB U2 (.CURREN('b1),.RGB0PWM(blu_pwm),.RGB1PWM(grn_pwm),.RGB2PWM(red_pwm),.RGBLEDEN('b1),.RGB0(BLUn),.RGB1(GRNn),.RGB2(REDn));
assign RED = red_pwm;
assign GRN = grn_pwm;
assign BLU = blu_pwm;
endmodule
Ampelansteuerung/steuerung.sv
+63
View File
@@ -0,0 +1,63 @@
module steuerung (
bus.steuerung_port b, //b.dip[3:0], b.timer, b.clk, b.spi_read[1:0]
led_if.led_port_top i //i.rgb[2:0], i.rgbn[2:0]
);
//dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
//input wire clk12M, -> b.clk
//input wire rst, -> b.dip[0]
//input wire [1:0] color_sel, -> b.dip[3:2]
//input wire rw, -> b.dip[1]
//output reg REDn, -> i.rgbn[0]
//output reg BLUn, -> i.rgbn[1]
//output reg GRNn, -> i.rgbn[2]
//output reg RED, -> i.rgb[0]
//output reg BLU, -> i.rgb[1]
//output reg GRN -> i.rgb[2]
wire red_pwm;
wire grn_pwm;
wire blu_pwm;
defparam U1.on_hi = 2'b10;
defparam U1.on_lo = 2'b01;
defparam U1.off = 2'b00;
defparam U1.LED_OFF = 2'b00;
defparam U1.RAMP_UP = 2'b01;
defparam U1.LED_ON = 2'b10;
defparam U1.RAMP_DOWN = 2'b11;
defparam U1.on_max_cnt = 28'h16E35ED; // 1 sec steady
defparam U1.Brightness = 4'b0111; // 50% Brightness
defparam U1.BreatheRamp = 4'b0110; // 2x
defparam U1.BlinkRate = 4'b0101; // 1 sec
defparam U2.RGB0_CURRENT = "0b111111";
defparam U2.RGB1_CURRENT = "0b111111";
defparam U2.RGB2_CURRENT = "0b111111";
LED_control1 U1 (.clk12M(b.clk),.rst(b.dip[0]),.color_sel(b.dip[3:2]),.rw(b.dip[1]),.red_pwm(red_pwm),.blu_pwm(blu_pwm),.grn_pwm(grn_pwm));
RGB U2 (.CURREN('b1),.RGB0PWM(blu_pwm),.RGB1PWM(grn_pwm),.RGB2PWM(red_pwm),.RGBLEDEN('b1),.RGB0(i.rgbn[1]),.RGB1(i.rgbn[2]),.RGB2(rgbn[0]));
assign i.rgb[0] = red_pwm;
assign i.rgb[2] = grn_pwm;
assign i.rgb[1] = blu_pwm;
endmodule
Ampelansteuerung/testbench.sv
-130
View File
@@ -1,130 +0,0 @@
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2017 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// Permission:
//
// Lattice SG Pte. Ltd. grants permission to use this code
// pursuant to the terms of the Lattice Reference Design License Agreement.
//
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Lattice provides no warranty
// regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//
// Lattice SG Pte. Lt++++++++++++++++d.
// 101 Thomson Road, United Square #07-02
// Singapore 307591
//
//
// TEL: 1-800-Lattice (USA and Canada)
// +65-6631-2000 (Singapore)
// +1-503-268-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: techsupport@latticesemi.com
//
// --------------------------------------------------------------------
//
// Project: iCE5UP 5K RGB LED Tutorial
// File: testbench.v
// Title: LED PWM control
// Description: Creates RGB PWM per control inputs
//
//
// --------------------------------------------------------------------
//
//------------------------------------------------------------
// Notes:
//
//
//------------------------------------------------------------
// Development History:
//
// __DATE__ _BY_ _REV_ _DESCRIPTION___________________________
// 04/05/17 RK 1.0 Initial tutorial design for Lattice Radiant
//
//------------------------------------------------------------
// Dependencies:
//
//
//
//------------------------------------------------------------
//------------------------------------------------------------
//
//
// Testbench
//
//------------------------------------------------------------
`timescale 1ns/1ps
module tb;
//GSR GSR_INST ( .GSR(1));
//PUR PUR_INST ( .PUR(1));
reg clk12M;
reg rst;
reg [1:0]color_sel;
reg RGB_Blink_En;
wire REDn;
wire BLUn;
wire GRNn;
wire RED;
wire BLU;
wire GRN;
led_top dut(.clk12M(clk12M),
.rst(rst),
.color_sel(color_sel),
.RGB_Blink_En(RGB_Blink_En),
.REDn(REDn),
.BLUn(BLUn),
.GRNn(GRNn),
.RED(RED),
.BLU(BLU),
.GRN(GRN)
);
initial
begin
clk12M=1'b0;
end
always
#41.666666 clk12M=~clk12M; //clock generation
initial
begin
rst=1'b1;
color_sel=2'b01;
RGB_Blink_En=1'b0;
#1000
rst=1'b0;
#3000000
color_sel=2'b11;
#3000000
$stop;
end
initial
begin
$monitor("time=%t,RGB_Blink_En=%d,rst=%d,color_sel=%2d, REDn=%d, BLUn=%d, GRNn=%d",$time,RGB_Blink_En,rst,color_sel,REDn,BLUn,GRNn);
end
endmodule
transcript
+14
View File
@@ -0,0 +1,14 @@
# // Questa Sim-64
# // Version 2019.4 linux_x86_64 Oct 15 2019
# //
# // Copyright 1991-2019 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
uebung_projekt/hdl_src/sv/fram.sv
+2 -2
View File
@@ -53,13 +53,13 @@ module spi(bus.spi_port b, fram_if.fram_port_top i);
if(FRAM_go == 1) if(FRAM_go == 1)
clk_cntr <= clk_cntr + 1; clk_cntr <= clk_cntr + 1;
if(clk_cntr > 50 && FRAM_RW == 1'h1) begin if(clk_cntr > 250 && FRAM_RW == 1'h1) begin
b.spi_read <= FRAM_DATA_OUT[1:0]; b.spi_read <= FRAM_DATA_OUT[1:0];
FRAM_go <= 1'h0; FRAM_go <= 1'h0;
FRAM_RW <= 1'h0; FRAM_RW <= 1'h0;
clk_cntr <= 0; clk_cntr <= 0;
end end
else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin else if(clk_cntr > 250 && FRAM_RW == 1'h0) begin
FRAM_go <= 1'h0; FRAM_go <= 1'h0;
clk_cntr <= 0; clk_cntr <= 0;
end end
uebung_projekt/hdl_src/sv/interface.sv
+3 -2
View File
@@ -21,9 +21,10 @@
interface led_if(); interface led_if();
logic [2:0]rgb; logic [2:0]rgb;
logic [2:0]rgbn;
modport led_port_stim(input rgb); modport led_port_stim(input rgb, rgbn);
modport led_port_top(output rgb); modport led_port_top(output rgb, rgbn);
endinterface : led_if endinterface : led_if
uebung_projekt/simulationsscripts/wave.do
+4 -3
View File
@@ -5,12 +5,13 @@ add wave -noupdate -radix binary /top_tb/t1/fpga_bus/dip
add wave -noupdate -radix binary /top_tb/stim_clock_if/clk add wave -noupdate -radix binary /top_tb/stim_clock_if/clk
add wave -noupdate -radix binary /top_tb/t1/fpga_bus/clk add wave -noupdate -radix binary /top_tb/t1/fpga_bus/clk
add wave -noupdate -radix binary /top_tb/t1/fpga_bus/timer add wave -noupdate -radix binary /top_tb/t1/fpga_bus/timer
add wave -noupdate -radix binary /top_tb/t1/s/FRAM_Adr add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_Adr
add wave -noupdate -radix binary /top_tb/t1/s/clk_cntr add wave -noupdate -radix binary /top_tb/t1/s/clk_cntr
add wave -noupdate -radix binary /top_tb/t1/s/FRAM_DATA_IN add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_DATA_IN
add wave -noupdate -radix binary /top_tb/t1/s/FRAM_DATA_OUT add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_DATA_OUT
add wave -noupdate -radix binary /top_tb/t1/f/mosi add wave -noupdate -radix binary /top_tb/t1/f/mosi
add wave -noupdate -radix binary /top_tb/t1/f/sclk add wave -noupdate -radix binary /top_tb/t1/f/sclk
add wave -noupdate -radix binary /top_tb/t1/fpga_bus/spi_read
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ns} 0} WaveRestoreCursors {{Cursor 1} {0 ns} 0}
quietly wave cursor active 0 quietly wave cursor active 0
uebung_projekt/transcript
+72 -188
View File
@@ -12,16 +12,18 @@
# // is prohibited from disclosure under the Trade Secrets Act, # // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905. # // 18 U.S.C. Section 1905.
# // # //
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
# #
# create workspace # create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019 # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work # vmap work ./work
# Modifying modelsim.ini # Modifying modelsim.ini
# #
# Compile sv-Designfiles # Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023 # Start time: 14:45:50 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if # -- Compiling interface led_if
# -- Compiling interface dip_if # -- Compiling interface dip_if
@@ -30,19 +32,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# #
# Top level modules: # Top level modules:
# --none-- # --none--
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023 # Start time: 14:45:50 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli # -- Compiling module stimuli
# #
# Top level modules: # Top level modules:
# stimuli # stimuli
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023 # Start time: 14:45:50 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top # -- Compiling module top
# -- Compiling interface bus # -- Compiling interface bus
@@ -51,66 +53,66 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# #
# Top level modules: # Top level modules:
# top # top
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023 # Start time: 14:45:50 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb # -- Compiling module top_tb
# #
# Top level modules: # Top level modules:
# top_tb # top_tb
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023 # Start time: 14:45:51 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer # -- Compiling module timer
# #
# Top level modules: # Top level modules:
# timer # timer
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023 # Start time: 14:45:51 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master # -- Compiling module SPI_Master
# #
# Top level modules: # Top level modules:
# SPI_Master # SPI_Master
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023 # Start time: 14:45:51 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS # -- Compiling module SPI_Master_With_Single_CS
# #
# Top level modules: # Top level modules:
# SPI_Master_With_Single_CS # SPI_Master_With_Single_CS
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023 # Start time: 14:45:51 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM # -- Compiling module FRAM
# #
# Top level modules: # Top level modules:
# FRAM # FRAM
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023 # Start time: 14:45:51 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi # -- Compiling module spi
# #
# Top level modules: # Top level modules:
# spi # spi
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# #
# Run Simulation # Run Simulation
# vsim -cvg63 -voptargs=""+acc"" top_tb # vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:04:53 on Jun 15,2023 # Start time: 14:45:51 on Jun 15,2023
# ** Note: (vsim-3812) Design is being optimized... # ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)". # ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)".
# Loading sv_std.std # Loading sv_std.std
@@ -129,10 +131,11 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# Loading work.SPI_Master(fast) # Loading work.SPI_Master(fast)
# Loading work.parallelport(fast) # Loading work.parallelport(fast)
# Loading work.stimuli(fast) # Loading work.stimuli(fast)
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
# #
# create workspace # create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work". # ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019 # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work # vmap work ./work
@@ -140,7 +143,7 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# #
# Compile sv-Designfiles # Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023 # Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if # -- Compiling interface led_if
# -- Compiling interface dip_if # -- Compiling interface dip_if
@@ -149,19 +152,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# #
# Top level modules: # Top level modules:
# --none-- # --none--
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023 # Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli # -- Compiling module stimuli
# #
# Top level modules: # Top level modules:
# stimuli # stimuli
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023 # Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top # -- Compiling module top
# -- Compiling interface bus # -- Compiling interface bus
@@ -170,68 +173,68 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# #
# Top level modules: # Top level modules:
# top # top
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023 # Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb # -- Compiling module top_tb
# #
# Top level modules: # Top level modules:
# top_tb # top_tb
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023 # Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer # -- Compiling module timer
# #
# Top level modules: # Top level modules:
# timer # timer
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023 # Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master # -- Compiling module SPI_Master
# #
# Top level modules: # Top level modules:
# SPI_Master # SPI_Master
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023 # Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS # -- Compiling module SPI_Master_With_Single_CS
# #
# Top level modules: # Top level modules:
# SPI_Master_With_Single_CS # SPI_Master_With_Single_CS
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023 # Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM # -- Compiling module FRAM
# #
# Top level modules: # Top level modules:
# FRAM # FRAM
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023 # Start time: 14:48:17 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi # -- Compiling module spi
# #
# Top level modules: # Top level modules:
# spi # spi
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# #
# Run Simulation # Run Simulation
# End time: 14:11:55 on Jun 15,2023, Elapsed time: 0:07:02 # End time: 14:48:18 on Jun 15,2023, Elapsed time: 0:02:27
# Errors: 12, Warnings: 1 # Errors: 3, Warnings: 2
# vsim -cvg63 -voptargs=""+acc"" top_tb # vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:11:55 on Jun 15,2023 # Start time: 14:48:18 on Jun 15,2023
# ** Note: (vsim-3813) Design is being optimized due to module recompilation... # ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading sv_std.std # Loading sv_std.std
# Loading work.top_tb(fast) # Loading work.top_tb(fast)
@@ -249,14 +252,13 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# Loading work.SPI_Master(fast) # Loading work.SPI_Master(fast)
# Loading work.parallelport(fast) # Loading work.parallelport(fast)
# Loading work.stimuli(fast) # Loading work.stimuli(fast)
# Can't move the Now cursor.
# Can't move the Now cursor.
add wave -position insertpoint \ add wave -position insertpoint \
sim:/top_tb/t1/f/mosi sim:/top_tb/t1/fpga_bus/spi_read
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
# #
# create workspace # create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work". # ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019 # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work # vmap work ./work
@@ -264,7 +266,7 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# #
# Compile sv-Designfiles # Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023 # Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if # -- Compiling interface led_if
# -- Compiling interface dip_if # -- Compiling interface dip_if
@@ -273,19 +275,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# #
# Top level modules: # Top level modules:
# --none-- # --none--
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023 # Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli # -- Compiling module stimuli
# #
# Top level modules: # Top level modules:
# stimuli # stimuli
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023 # Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top # -- Compiling module top
# -- Compiling interface bus # -- Compiling interface bus
@@ -294,189 +296,69 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# #
# Top level modules: # Top level modules:
# top # top
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023 # Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb # -- Compiling module top_tb
# #
# Top level modules: # Top level modules:
# top_tb # top_tb
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023 # Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer # -- Compiling module timer
# #
# Top level modules: # Top level modules:
# timer # timer
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023 # Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master # -- Compiling module SPI_Master
# #
# Top level modules: # Top level modules:
# SPI_Master # SPI_Master
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023 # Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS # -- Compiling module SPI_Master_With_Single_CS
# #
# Top level modules: # Top level modules:
# SPI_Master_With_Single_CS # SPI_Master_With_Single_CS
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023 # Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM # -- Compiling module FRAM
# #
# Top level modules: # Top level modules:
# FRAM # FRAM
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023 # Start time: 14:51:02 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi # -- Compiling module spi
# #
# Top level modules: # Top level modules:
# spi # spi
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00 # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0 # Errors: 0, Warnings: 0
# #
# Run Simulation # Run Simulation
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:07:06 # End time: 14:51:07 on Jun 15,2023, Elapsed time: 0:02:49
# Errors: 12, Warnings: 1 # Errors: 1, Warnings: 2
# vsim -cvg63 -voptargs=""+acc"" top_tb # vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:19:01 on Jun 15,2023 # Start time: 14:51:07 on Jun 15,2023
# ** Note: (vsim-8009) Loading existing optimized design _opt # ** Note: (vsim-8009) Loading existing optimized design _opt1
# Loading sv_std.std
# Loading work.top_tb(fast)
# Loading work.led_if(fast)
# Loading work.dip_if(fast)
# Loading work.fram_if(fast)
# Loading work.clock_if(fast)
# Loading work.top(fast)
# Loading work.bus(fast)
# Loading work.timer(fast)
# Loading work.steuerung(fast)
# Loading work.spi(fast)
# Loading work.FRAM(fast)
# Loading work.SPI_Master_With_Single_CS(fast)
# Loading work.SPI_Master(fast)
# Loading work.parallelport(fast)
# Loading work.stimuli(fast)
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
#
# create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work
# Modifying modelsim.ini
#
# Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if
# -- Compiling interface dip_if
# -- Compiling interface fram_if
# -- Compiling interface clock_if
#
# Top level modules:
# --none--
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli
#
# Top level modules:
# stimuli
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top
# -- Compiling interface bus
# -- Compiling module parallelport
# -- Compiling module steuerung
#
# Top level modules:
# top
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb
#
# Top level modules:
# top_tb
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer
#
# Top level modules:
# timer
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master
#
# Top level modules:
# SPI_Master
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS
#
# Top level modules:
# SPI_Master_With_Single_CS
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM
#
# Top level modules:
# FRAM
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:08 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi
#
# Top level modules:
# spi
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# Run Simulation
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:03:07
# Errors: 5, Warnings: 1
# vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:22:08 on Jun 15,2023
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading sv_std.std # Loading sv_std.std
# Loading work.top_tb(fast) # Loading work.top_tb(fast)
# Loading work.led_if(fast) # Loading work.led_if(fast)
@@ -493,3 +375,5 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
# Loading work.SPI_Master(fast) # Loading work.SPI_Master(fast)
# Loading work.parallelport(fast) # Loading work.parallelport(fast)
# Loading work.stimuli(fast) # Loading work.stimuli(fast)
# End time: 14:52:23 on Jun 15,2023, Elapsed time: 0:01:16
# Errors: 3, Warnings: 0
uebung_projekt/vsim.wlf
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uebung_projekt/work/@_opt1/_lib.qdb
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uebung_projekt/work/@_opt1/_lib1_0.qdb
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uebung_projekt/work/@_opt1/_lib1_0.qpg
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uebung_projekt/work/@_opt1/_lib1_0.qtl
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uebung_projekt/work/@_opt1/_lib2_0.qdb
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uebung_projekt/work/@_opt1/_lib2_0.qpg
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uebung_projekt/work/@_opt1/_lib3_0.qdb
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uebung_projekt/work/@_opt1/_lib4_0.qdb
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uebung_projekt/work/@_opt1/_lib4_0.qpg
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@@ -10,389 +10,400 @@ z2
cModel Technology cModel Technology
Z0 d/users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt Z0 d/users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt
T_opt T_opt
Z1 !s110 1686831728 !s110 1686831728
V2L38BN@acDd:OB=HL_FC32 V2L38BN@acDd:OB=HL_FC32
04 6 4 work top_tb fast 0 Z1 04 6 4 work top_tb fast 0
=1-005056b42dc6-648b0270-7d119-559d =1-005056b42dc6-648b0270-7d119-559d
o-quiet -auto_acc_if_foreign -work work +acc Z2 o-quiet -auto_acc_if_foreign -work work +acc
Z2 tCvgOpt 0 Z3 tCvgOpt 0
n@_opt n@_opt
OL;O;2019.4;69 Z4 OL;O;2019.4;69
R0
T_opt1
!s110 1686833298
V4N01Y?dc<]WhdSf73Ue?91
R1
=1-005056b42dc6-648b0892-563db-611e
R2
R3
n@_opt1
R4
R0
Ybus Ybus
Z3 DXx6 sv_std 3 std 0 22 9oUSJO;AeEaW`l:M@^WG92 Z5 DXx6 sv_std 3 std 0 22 9oUSJO;AeEaW`l:M@^WG92
Z4 !s110 1686831727 Z6 !s110 1686833462
!i10b 1 !i10b 1
!s100 T;581z6K]3OXG=KOJdK4G2 !s100 T;581z6K]3OXG=KOJdK4G2
!s11b Dj[TOJX9onk[mCamXbz9c3 !s11b Dj[TOJX9onk[mCamXbz9c3
I<3_5F:_4Ri@f;?1:3BJf=2 I<3_5F:_4Ri@f;?1:3BJf=2
Z5 VDg1SIo80bB@j0V0VzS_@n1 Z7 VDg1SIo80bB@j0V0VzS_@n1
S1 S1
R0 Z8 d/users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt
Z6 w1686830281 Z9 w1686832439
Z7 8./hdl_src/sv/top_level.sv Z10 8./hdl_src/sv/top_level.sv
Z8 F./hdl_src/sv/top_level.sv Z11 F./hdl_src/sv/top_level.sv
!i122 -1 !i122 -1
L0 15 L0 15
Z9 OL;L;2019.4;69 Z12 OL;L;2019.4;69
r1 r1
!s85 0 !s85 0
31 31
Z10 !s108 1686831727.000000 Z13 !s108 1686833462.000000
Z11 !s107 ./hdl_src/sv/top_level.sv| Z14 !s107 ./hdl_src/sv/top_level.sv|
Z12 !s90 -reportprogress|300|-work|work|./hdl_src/sv/top_level.sv| Z15 !s90 -reportprogress|300|-work|work|./hdl_src/sv/top_level.sv|
!i113 0 !i113 0
Z13 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact Z16 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
R2 R3
Yclock_if Yclock_if
R3 R5
R4 R6
!i10b 1 !i10b 1
!s100 iND9Vz2l5W=c=U<U<OKbg0 !s100 heLOC37I>@m@mlh@>YnK82
!s11b oJPC4U0:1B^QG:cZC>8A:1 !s11b oJPC4U0:1B^QG:cZC>8A:1
IOQJeZ`mU<Z1m4K_[FIhfS2 IzF198zIQF2djPZ;867:>83
R5 R7
S1 S1
R0 R8
Z14 w1686314964 Z17 w1686832912
Z15 8./hdl_src/sv/interface.sv Z18 8./hdl_src/sv/interface.sv
Z16 F./hdl_src/sv/interface.sv Z19 F./hdl_src/sv/interface.sv
!i122 -1 !i122 -1
L0 60 L0 61
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10
Z17 !s107 ./hdl_src/sv/interface.sv|
Z18 !s90 -reportprogress|300|-work|work|./hdl_src/sv/interface.sv|
!i113 0
R13 R13
R2 Z20 !s107 ./hdl_src/sv/interface.sv|
Ydip_if Z21 !s90 -reportprogress|300|-work|work|./hdl_src/sv/interface.sv|
R3 !i113 0
R4
!i10b 1
!s100 lPioFG@0T7j3gKFQYYe8W0
!s11b @Hfo8VJnf;PXXPSgXE44V1
I@=49][3E;]nafb=5@ka:a0
R5
S1
R0
R14
R15
R16 R16
!i122 -1 R3
L0 33 Ydip_if
R9 R5
r1 R6
!s85 0 !i10b 1
31 !s100 <PVf]bVPeKdaLDk`m:i?Y0
R10 !s11b @Hfo8VJnf;PXXPSgXE44V1
I@P@no8JU[7ajE4d1Y<M;E2
R7
S1
R8
R17 R17
R18 R18
!i113 0 R19
!i122 -1
Z22 L0 34
R12
r1
!s85 0
31
R13 R13
R2 R20
vFRAM R21
!i113 0
R16
R3 R3
R1 vFRAM
R5
R6
!i10b 1 !i10b 1
!s100 6GgRzC`3J8EKCo2KAh]SA3 !s100 6GgRzC`3J8EKCo2KAh]SA3
!s11b 48o?`kIzT=WRNj@`=ICgH0 !s11b 48o?`kIzT=WRNj@`=ICgH0
Id_KQzKR^jG]NNATEeL[F]1 Id_KQzKR^jG]NNATEeL[F]1
R5 R7
S1 S1
R0 R8
w1686826733 R9
8./hdl_src/sv/FRAM_Controller.sv 8./hdl_src/sv/FRAM_Controller.sv
F./hdl_src/sv/FRAM_Controller.sv F./hdl_src/sv/FRAM_Controller.sv
!i122 -1 !i122 -1
L0 1 L0 1
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10 R13
!s107 ./hdl_src/sv/FRAM_Controller.sv| !s107 ./hdl_src/sv/FRAM_Controller.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/FRAM_Controller.sv| !s90 -reportprogress|300|-work|work|./hdl_src/sv/FRAM_Controller.sv|
!i113 0 !i113 0
R13 R16
R2 R3
n@f@r@a@m n@f@r@a@m
Yfram_if Yfram_if
R3
R4
!i10b 1
!s100 FG9WSXZ0h`ZNCKFUfVEI;0
!s11b TH@FFRQ[NJF5WXda=V[<H1
IM[7bzae]_QlkaTl;QldDo3
R5 R5
R6
!i10b 1
!s100 ;Pz<e0OVOd241SzfjUmAh0
!s11b TH@FFRQ[NJF5WXda=V[<H1
Il7_QcI82L^C5SjV==1o`V1
R7
S1 S1
R0 R8
R14 R17
R15 R18
R16 R19
!i122 -1 !i122 -1
L0 47 L0 48
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10 R13
R20
R21
!i113 0
R16
R3
Yled_if
R5
R6
!i10b 1
!s100 AW>Ho3QlAW4UmzOWF^R8D3
!s11b JgIFT<E122eWGg7n1X`z=3
IlJ8kZ^KF?8@@UY4nOo0OX2
R7
S1
R8
R17 R17
R18 R18
!i113 0 R19
R13
R2
Yled_if
R3
R4
!i10b 1
!s100 NHE2==?Gh0C?o>9[W_4_O1
!s11b djVBMKk[@Wh5FXIDGlUF[2
I`agi[9j3c9e5gcFWSVSH51
R5
S1
R0
R14
R15
R16
!i122 -1 !i122 -1
L0 21 L0 21
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10
R17
R18
!i113 0
R13 R13
R2 R20
vparallelport R21
!i113 0
R16
R3 R3
R4 vparallelport
R5
R6
!i10b 1 !i10b 1
!s100 Oh9lLSH=`_Q:=@41ZzlcY2 !s100 Oh9lLSH=`_Q:=@41ZzlcY2
!s11b k21ML[34E18n]@g]EG:g02 !s11b k21ML[34E18n]@g]EG:g02
I;1_EJNiVm[nDB?57=nXOD3 I;1_EJNiVm[nDB?57=nXOD3
R5
S1
R0
R6
R7 R7
S1
R8 R8
R9
R10
R11
!i122 -1 !i122 -1
L0 30 L0 30
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10
R11
R12
!i113 0
R13 R13
R2 R14
vspi R15
!i113 0
R16
R3 R3
R1 vspi
!i10b 1
!s100 FWg;A^hM6Xk;TFJMgza]m2
!s11b NBC7eT]a7]iC:n6DXhW[e0
Ilbh>SdZV4bSDzE22EQIiC3
R5 R5
R6
!i10b 1
!s100 GPbXMO8=ajXa5d]lGaVmH2
!s11b <niOgj]Bz2TKD=0Y:F^jW2
IJ^b4_ZQUY=Ddi7N>AgHIb1
R7
S1 S1
R0 R8
w1686830667 w1686833271
8./hdl_src/sv/fram.sv 8./hdl_src/sv/fram.sv
F./hdl_src/sv/fram.sv F./hdl_src/sv/fram.sv
!i122 -1 !i122 -1
L0 4 L0 4
R9 R12
r1 r1
!s85 0 !s85 0
31 31
!s108 1686831728.000000 R13
!s107 ./hdl_src/sv/fram.sv| !s107 ./hdl_src/sv/fram.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/fram.sv| !s90 -reportprogress|300|-work|work|./hdl_src/sv/fram.sv|
!i113 0 !i113 0
R13 R16
R2
vSPI_Master
R3 R3
R4 vSPI_Master
R5
R6
!i10b 1 !i10b 1
!s100 LNaIK]EJb:HMhCL_bcUOT2 !s100 LNaIK]EJb:HMhCL_bcUOT2
!s11b RZ[UYHW;Fa4LhmckzB[<X2 !s11b RZ[UYHW;Fa4LhmckzB[<X2
IFYo`G3DmU9[M^WeGMdfi73 IFYo`G3DmU9[M^WeGMdfi73
R5 R7
S1 S1
R0 R8
w1686826806 R9
8./hdl_src/sv/SPI_Master_Control.sv 8./hdl_src/sv/SPI_Master_Control.sv
F./hdl_src/sv/SPI_Master_Control.sv F./hdl_src/sv/SPI_Master_Control.sv
!i122 -1 !i122 -1
Z19 L0 34 R22
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10 R13
!s107 ./hdl_src/sv/SPI_Master_Control.sv| !s107 ./hdl_src/sv/SPI_Master_Control.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/SPI_Master_Control.sv| !s90 -reportprogress|300|-work|work|./hdl_src/sv/SPI_Master_Control.sv|
!i113 0 !i113 0
R13 R16
R2 R3
n@s@p@i_@master n@s@p@i_@master
vSPI_Master_With_Single_CS vSPI_Master_With_Single_CS
R3 R5
R4 R6
!i10b 1 !i10b 1
!s100 15??SlXF;4=1UHZHFcb4D2 !s100 15??SlXF;4=1UHZHFcb4D2
!s11b iXFhD1[A]RQ:BgzgT;=fY3 !s11b iXFhD1[A]RQ:BgzgT;=fY3
ID5Z=T=j@LdzO_?_@1UFZC3 ID5Z=T=j@LdzO_?_@1UFZC3
R5 R7
S1 S1
R0 R8
w1686826875 R9
8./hdl_src/sv/SPI_Master.sv 8./hdl_src/sv/SPI_Master.sv
F./hdl_src/sv/SPI_Master.sv F./hdl_src/sv/SPI_Master.sv
!i122 -1 !i122 -1
Z20 L0 38 Z23 L0 38
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10 R13
!s107 ./hdl_src/sv/SPI_Master.sv| !s107 ./hdl_src/sv/SPI_Master.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/SPI_Master.sv| !s90 -reportprogress|300|-work|work|./hdl_src/sv/SPI_Master.sv|
!i113 0 !i113 0
R13 R16
R2 R3
n@s@p@i_@master_@with_@single_@c@s n@s@p@i_@master_@with_@single_@c@s
vsteuerung vsteuerung
R3 R5
R4 R6
!i10b 1 !i10b 1
!s100 >DGbebG_Mk0W]hI8XCQ?k0 !s100 >DGbebG_Mk0W]hI8XCQ?k0
!s11b WKleG=JcKL4FgO@TP[IO[1 !s11b WKleG=JcKL4FgO@TP[IO[1
IE`WCa5G2QlghM9EX[<1dS3 IE`WCa5G2QlghM9EX[<1dS3
R5
S1
R0
R6
R7 R7
S1
R8 R8
!i122 -1
R20
R9 R9
R10
R11
!i122 -1
R23
R12
r1 r1
!s85 0 !s85 0
31 31
R10
R11
R12
!i113 0
R13 R13
R2 R14
vstimuli R15
!i113 0
R16
R3 R3
R4 vstimuli
R5
R6
!i10b 1 !i10b 1
!s100 ?c<R_8azXOe4?MR6PN9lb1 !s100 ?c<R_8azXOe4?MR6PN9lb1
!s11b f7UOC6iFO:78SRcz4Ojgc1 !s11b f7UOC6iFO:78SRcz4Ojgc1
IFCieJ4l88EVc2aVF84efc1 IFCieJ4l88EVc2aVF84efc1
R5 R7
S1 S1
R0 R8
w1686831722 R9
8./hdl_src/sv/stimuli.sv 8./hdl_src/sv/stimuli.sv
F./hdl_src/sv/stimuli.sv F./hdl_src/sv/stimuli.sv
!i122 -1 !i122 -1
L0 37 L0 37
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10 R13
!s107 ./hdl_src/sv/stimuli.sv| !s107 ./hdl_src/sv/stimuli.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/stimuli.sv| !s90 -reportprogress|300|-work|work|./hdl_src/sv/stimuli.sv|
!i113 0 !i113 0
R13 R16
R2
vtimer
R3 R3
R4 vtimer
R5
R6
!i10b 1 !i10b 1
!s100 ^LgdMGMo^z_E<7OKUmDz:0 !s100 ^LgdMGMo^z_E<7OKUmDz:0
!s11b [5XV:J9W^QFe>5GG;9B8k3 !s11b [5XV:J9W^QFe>5GG;9B8k3
IEenLI0W00diXD61Ele2;U0 IEenLI0W00diXD61Ele2;U0
R5 R7
S1 S1
R0 R8
w1686831703 R9
8./hdl_src/sv/timer.sv 8./hdl_src/sv/timer.sv
F./hdl_src/sv/timer.sv F./hdl_src/sv/timer.sv
!i122 -1 !i122 -1
L0 19 L0 19
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10 R13
!s107 ./hdl_src/sv/timer.sv| !s107 ./hdl_src/sv/timer.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/timer.sv| !s90 -reportprogress|300|-work|work|./hdl_src/sv/timer.sv|
!i113 0 !i113 0
R13 R16
R2
vtop
R3 R3
R4 vtop
R5
R6
!i10b 1 !i10b 1
!s100 6?3aiGY1NTOnA[jU;ZnEa3 !s100 6?3aiGY1NTOnA[jU;ZnEa3
!s11b =zPVnM;Zm1L1Ig2finB;E2 !s11b =zPVnM;Zm1L1Ig2finB;E2
I^g60QFGiK:2<OB;dYJIk23 I^g60QFGiK:2<OB;dYJIk23
R5
S1
R0
R6
R7 R7
S1
R8 R8
R9
R10
R11
!i122 -1 !i122 -1
L0 2 L0 2
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10
R11
R12
!i113 0
R13 R13
R2 R14
vtop_tb R15
!i113 0
R16
R3 R3
R4 vtop_tb
R5
R6
!i10b 1 !i10b 1
!s100 MLz@z6Rj=WV;42>b=KZhX2 !s100 MLz@z6Rj=WV;42>b=KZhX2
!s11b jcE]a:O3cJ<=CdGZ:MgQ62 !s11b jcE]a:O3cJ<=CdGZ:MgQ62
IbRb[2DAWSb2IUOHB[hFz:2 IbRb[2DAWSb2IUOHB[hFz:2
R5 R7
S1 S1
R0 R8
w1686315659 R9
8./hdl_src/sv/top_tb.sv 8./hdl_src/sv/top_tb.sv
F./hdl_src/sv/top_tb.sv F./hdl_src/sv/top_tb.sv
!i122 -1 !i122 -1
R19 R22
R9 R12
r1 r1
!s85 0 !s85 0
31 31
R10 R13
!s107 ./hdl_src/sv/top_tb.sv| !s107 ./hdl_src/sv/top_tb.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/top_tb.sv| !s90 -reportprogress|300|-work|work|./hdl_src/sv/top_tb.sv|
!i113 0 !i113 0
R13 R16
R2 R3
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