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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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Simon Schmidt e71d8eb717 changed gitignore 3 years ago
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4-bit-counter-cocotb correct makefile error 3 years ago
4-bit-counter-myhdl changed gitignore 3 years ago
7Segment_Lattice_ice40_UltraPlus @ d567bd258c initial commit 3 years ago
digitaler-filter-cocotb added and changed gitignores 3 years ago
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README.md initial commit 3 years ago

README.md

ESY1B Verifikation mit SystemVerilog und Python

Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema “Verifikation mit SystemVerilog und Python”