added LCD seminararbeit

2021-07-12 00:30:42 +02:00
parent b3637d6d76
commit 28af588549
28 changed files with 11253 additions and 0 deletions
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+VA_FILE = demo.va
+TOP_LEVEL_MODULE = demo
+
+CMD_FILE = demo.cmd
+DO_FILE = run.do
+OUT_FILE = demo.wdb
+
+
+
+sim:
+	valog $(VA_FILE) 
+	vasim -c -cmd $(CMD_FILE) -do $(DO_FILE) $(TOP_LEVEL_MODULE) 
+
+ezwave:
+	ezwave -now -loc 10 10 -width 2400 -height 1200 -tcl create_plots.tcl
+
+clean:
+	rm DefaultVlogALib -rf
+	rm *.chi *.log *.id *.reuse *.wdb -rf
+	rm simcommand transcript* dok_code* -rf
+
+
+
@@ -0,0 +1,26 @@
+############################################################
+## EZwave - Saved Window File
+## Tuesday, June 15, 2021 at 1:00:12 AM CEST
+##
+## Note: This is an auto-generated file.
+##
+## In case of modification, Do not remove this comment
+############################################################
+
+onerror {resume}
+
+# ===== Open required Database =====
+dataset open /users/ads1/schmidtsi76327/linux/esy1a/LCD_EPD_Simulation_VerilogA/lcd/reflection_vs_input_voltage_lcd_cap/demo.wdb demo
+
+# ====== Create the expressions =====
+
+
+
+# ===== Open the window =====
+wave addwindow -x 0  -y 0 -width 767  -height 558 -divider 0.85
+
+# ===== Create row #1 =====
+add wave  -versus V(:demo:lcc:(a,b)) VAR(:demo:lcc:trans)
+
+
+# ====== Create the cursors, markers and measurements =====
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+* demo.cmd
+
+.tran 1u 10m
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+
+`include "disciplines.vams"
+`include "constants.vams"
+
+module myfet(d, g, s);
+  inout electrical d, g, s;
+  parameter real kp = 1m;
+  parameter real vt = 1;
+  real vgst;
+  real cur;
+  analog begin
+   vgst = V(g,s)-vt;
+   cur = 0.0;
+   if (vgst > 0)
+    if (vgst > V(d,s))
+     cur = (vgst-0.5*V(d,s))*V(d,s);
+    else
+     cur = 0.5*pow(vgst, 2);
+     I(d,s) <+ kp*cur;
+   end
+endmodule
+
+
+module lccap(a,b);
+  inout a,b; //Interface ports
+  electrical a,b;
+  electrical force_node; //Internal node
+
+  real vext=0;
+  real vv=0;
+  real vforce=0;
+
+  parameter real rforce=1;            // Rd
+  parameter real cforce=0.001;        // Cd 
+  parameter real tau = rforce*cforce; // tau=Rd*Cd
+
+  real vcontrol= 0;  // RMS Voltage to control the angle 
+
+  // capacitance 
+  real cap = 0; 
+  real qlc = 0;
+  parameter real cmin=2.5e-15; // C  
+  parameter real cmax=8.0e-15; // Cparallel
+
+  real alpha = 0;
+  parameter real delta_sq = 0.1;
+  parameter real vtc = 2;
+  parameter real vmc = 0.1;
+ 
+  // transmittance / reflectance 
+  real beta = 0; 
+  real trans=0;
+  
+  parameter real tmin = 0.01;
+  parameter real eta_sq = 0.1;
+  parameter real vmo = 0.9;
+  parameter real vto = 2;
+
+  analog
+  begin
+    @(initial_step)
+    begin
+      //Initial voltage for internal node
+      vforce = 0;
+    end
+
+    begin
+      //Probing terminal voltage
+      vext = V(a,b);
+      vv = vext * vext;
+
+      // Calculation of Internal node voltage
+      I(force_node) <+ ddt(cforce * V(force_node)); // current into Cd 
+      I(force_node) <+ (V(force_node)-vv) / rforce; // current from Rd     
+      vforce = V(force_node);  
+      vcontrol = sqrt(vforce); 			    // calculate RMS Voltage
+
+      // C-V calculation
+      alpha = (vcontrol - vtc) / vmc;
+      cap = cmin + (2/`M_PI) * (cmax-cmin) * atan( (alpha + sqrt(alpha * alpha + delta_sq ))/2);
+      qlc = cap * vext;   // delta Q
+      I(a,b) <+ ddt(qlc); // dQ / dt
+
+      // T-V calculation
+      beta = (vcontrol - vto)/ vmo;
+      trans = 1 - (1-tmin)*tanh( (beta+sqrt(beta*beta + eta_sq)) / 2 );
+
+    end
+  end
+endmodule
+
+
+module demo;
+  electrical src_out, gate, out, gnd;
+  ground gnd;
+
+  analog begin
+    V(out) <+ idt(6.0 * 100, 0, 0); // ramp 0-6V in 10ms
+    $bound_step(10u/100);           // bessere Aufloesung
+  end
+  
+  lccap lcc(out, gnd);
+endmodule
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+add wave -r *
+add wave -i -r *
+run -all
+quit -f
@@ -0,0 +1,23 @@
+VA_FILE = demo.va
+TOP_LEVEL_MODULE = demo
+
+CMD_FILE = demo.cmd
+DO_FILE = run.do
+OUT_FILE = demo.wdb
+
+
+
+sim:
+	valog $(VA_FILE) 
+	vasim -c -cmd $(CMD_FILE) -do $(DO_FILE) $(TOP_LEVEL_MODULE) 
+
+ezwave:
+	ezwave -now -loc 10 10 -width 2400 -height 1200 -tcl create_plots.tcl
+
+clean:
+	rm DefaultVlogALib -rf
+	rm *.chi *.log *.id *.reuse *.wdb -rf
+	rm simcommand transcript* -rf
+
+
+
@@ -0,0 +1,30 @@
+############################################################
+## EZwave - Saved Window File
+## Tuesday, June 15, 2021 at 12:44:25 AM CEST
+##
+## Note: This is an auto-generated file.
+##
+## In case of modification, Do not remove this comment
+############################################################
+
+onerror {resume}
+
+# ===== Open required Database =====
+dataset open /users/ads1/schmidtsi76327/linux/esy1a/LCD_EPD_Simulation_VerilogA/lcd/transient_response_lcd_cap/demo.wdb demo
+
+# ===== Open the window =====
+wave addwindow -x 0  -y 0 -width 1490  -height 1075 -divider 0.82
+
+# ===== Create row #1 =====
+add wave -overlay    -show TRAN.v -color -16711936 -separator : -terminals  :demo:lcc:(a,b) -show TRAN.var -color -256 -separator : -signals  :demo:lcc:vcontrol
+
+
+# ===== Create row #2 =====
+add wave  -show TRAN.var -color -16744193 -separator : -signals  :demo:lcc:cap
+
+
+# ===== Create row #3 =====
+add wave  -show TRAN.v -color -32768 -separator : -terminals  :demo:gate
+
+
+# ====== Create the cursors, markers and measurements =====
@@ -0,0 +1,3 @@
+* demo.cmd
+
+.tran 1u 5m
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+
+`include "disciplines.vams"
+`include "constants.vams"
+
+module myfet(d, g, s);
+  inout electrical d, g, s;
+  parameter real kp = 1m;
+  parameter real vt = 1;
+  real vgst;
+  real cur;
+  analog begin
+   vgst = V(g,s)-vt;
+   cur = 0.0;
+   if (vgst > 0)
+    if (vgst > V(d,s))
+     cur = (vgst-0.5*V(d,s))*V(d,s);
+    else
+     cur = 0.5*pow(vgst, 2);
+     I(d,s) <+ kp*cur;
+   end
+endmodule
+
+
+module lccap(a,b);
+  inout a,b; //Interface ports
+  electrical a,b;
+  electrical force_node; //Internal node
+
+  real vext=0;
+  real vv=0;
+  real vforce=0;
+
+  parameter real rforce=1;            // Rd
+  parameter real cforce=0.001;        // Cd 
+  parameter real tau = rforce*cforce; // tau=Rd*Cd
+
+  real vcontrol= 0;  // RMS Voltage to control the angle 
+
+  // capacitance 
+  real cap = 0; 
+  real qlc = 0;
+  parameter real cmin=2.5e-15; // C  
+  parameter real cmax=8.0e-15; // Cparallel
+
+  real alpha = 0;
+  parameter real delta_sq = 0.1;
+  parameter real vtc = 2;
+  parameter real vmc = 0.1;
+ 
+  // transmittance / reflectance 
+  real beta = 0; 
+  real trans=0;
+  
+  parameter real tmin = 0.01;
+  parameter real eta_sq = 0.1;
+  parameter real vmo = 0.9;
+  parameter real vto = 2;
+
+  analog
+  begin
+    @(initial_step)
+    begin
+      //Initial voltage for internal node
+      vforce = 0;
+    end
+
+    begin
+      //Probing terminal voltage
+      vext = V(a,b);
+      vv = vext * vext;
+
+      // Calculation of Internal node voltage
+      I(force_node) <+ ddt(cforce * V(force_node)); // current into Cd 
+      I(force_node) <+ (V(force_node)-vv) / rforce; // current from Rd     
+      vforce = V(force_node);  
+      vcontrol = sqrt(vforce); 			    // calculate RMS Voltage
+
+      // C-V calculation
+      alpha = (vcontrol - vtc) / vmc;
+      cap = cmin + (2/`M_PI) * (cmax-cmin) * atan( (alpha + sqrt(alpha * alpha + delta_sq ))/2);
+      qlc = cap * vext;   // delta Q
+      I(a,b) <+ ddt(qlc); // dQ / dt
+
+      // T-V calculation
+      beta = (vcontrol - vto)/ vmo;
+      trans = 1 - (1-tmin)*tanh( (beta+sqrt(beta*beta + eta_sq)) / 2 );
+
+    end
+  end
+endmodule
+
+
+module demo;
+  electrical src_out, gate, out, gnd;
+  ground gnd;
+
+  parameter real on_V = 10.0;
+  parameter real off_V = -1;
+
+  parameter real on_T = 2m;         // on 1s
+  parameter real off_T = 0;
+  parameter real startDelay = 1m;   // switch to on_V on 2ms
+
+  analog begin
+    $bound_step(10u);           // bessere Aufloesung
+  end
+
+  // Puls-Quelle 
+  /*prameters expected for 'pulse' are '[dc] [mag [phase]] val0 val1 [td [rise [fall [width [period]]]]] */
+  vpulse #(.val0(off_V), .val1(on_V), .td(startDelay), .rise(1n), .fall(1n), .width(on_T)) PL(gate, gnd);
+  vdc #(.dc(3.2)) VDC (src_out, gnd);
+  
+  myfet #(.kp(1m)) FET1 (src_out, gate, out);
+ 
+  lccap lcc(out, gnd);
+endmodule
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+add wave -r *
+add wave -i -r *
+run -all
+quit -f