schmidtsi76327/ESY1A_B_Seminararbeiten
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correct makefile error

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This commit is contained in:
Simon Schmidt 2021-06-09 11:15:13 +02:00
parent ec65cf50cb
commit 3c2c09f0b9
1 changed files with 1 additions and 1 deletions
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4-bit-counter-cocotb/tests/Makefile
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@ -32,7 +32,7 @@ TOPLEVEL_LANG ?= verilog
PWD=$(shell pwd) PWD=$(shell pwd)
ifeq ($(TOPLEVEL_LANG),verilog) ifeq ($(TOPLEVEL_LANG),verilog)
VERILOG_SOURCES = $(PWD)/../hdl/counter.sv VERILOG_SOURCES = $(PWD)/../hdl/counter.v
else ifeq ($(TOPLEVEL_LANG),vhdl) else ifeq ($(TOPLEVEL_LANG),vhdl)
VHDL_SOURCES = $(PWD)/../hdl/counter.vhdl VHDL_SOURCES = $(PWD)/../hdl/counter.vhdl
else else