Merge branch 'master' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2023

Ampelansteuerung/LED_control.sv

@@ -0,0 +1,498 @@
+//   ==================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+//   ------------------------------------------------------------------
+//   Copyright (c) 2017 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED  
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   --------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+// --------------------------------------------------------------------
+//
+//  Project:           iCE5UP 5K RGB LED Tutorial 
+//  File:              LED_control.v
+//  Title:             LED PWM control
+//  Description:       Creates RGB PWM per control inputs
+//                 
+//
+// --------------------------------------------------------------------
+//
+//------------------------------------------------------------
+// Notes:
+//
+//
+//------------------------------------------------------------
+// Development History:
+//
+//   __DATE__ _BY_ _REV_ _DESCRIPTION___________________________
+//   04/05/17  RK  1.0    Initial tutorial design for Lattice Radiant
+//
+//------------------------------------------------------------
+// Dependencies:
+//
+// 
+//
+//------------------------------------------------------------
+
+
+module LED_control1 (
+        // inputs
+        input   wire    clk12M,           // 12M clock
+		input   wire    rst,              // Asynchronous reset
+        input   wire    [1:0] color_sel,  // for selecting color using switches
+		input   wire    rw,     		  // read or write select switch
+        //outputs
+        output  reg         red_pwm,      // Red
+        output  reg         blu_pwm,      // Blue
+        output  reg         grn_pwm       // Green
+        );
+
+
+//------------------------------
+// INTERNAL SIGNAL DECLARATIONS: 
+//------------------------------
+// parameters (constants)
+parameter     on_hi = 2'b10;
+parameter     on_lo = 2'b01;
+parameter     off   = 2'b00; 
+
+parameter     LED_OFF   = 2'b00;
+parameter     RAMP_UP   = 2'b01;
+parameter     LED_ON    = 2'b10;
+parameter     RAMP_DOWN = 2'b11;
+
+parameter     on_max_cnt  = 28'h16E35ED;  // 1 sec steady
+
+parameter Brightness=4'b0111; //50% Brightness
+parameter BreatheRamp=4'b0111; //4x
+parameter BlinkRate=4'b0101; //1sec
+
+
+// wires (assigns)
+wire [3:0]RGB_color;   
+wire   [4:0] red_intensity;
+wire   [4:0] grn_intensity;
+wire   [4:0] blu_intensity;
+wire clk24M;
+wire LOCK;
+
+// regs (always)
+reg     [1:0] clk_div_cnt;      // 
+
+reg     [3:0] RGB_color_s;    // sample values from SPI i/f      
+reg     [3:0] Brightness_s;        
+reg     [3:0] BreatheRamp_s;       
+reg     [3:0] BlinkRate_s;         
+
+reg     [1:0] red_set;		  // hi/lo/off
+reg     [1:0] grn_set;		  
+reg     [1:0] blu_set;		  
+
+reg    [31:0] red_peak;		  // LED 'on' peak intensity (high precision)
+reg    [31:0] grn_peak;
+reg    [31:0] blu_peak;
+
+reg    [27:0] off_max_cnt;  // LED off duration
+reg     [3:0] step_shift;      // scaling calculation aid
+
+reg    [27:0] ramp_max_cnt;			// LED ramp up/down duration
+reg    [31:0] red_intensity_step;	// LED intensity step when ramping
+reg    [31:0] grn_intensity_step;
+reg    [31:0] blu_intensity_step;
+
+reg     [1:0] blink_state;          // state variable
+reg    [27:0] ramp_count;			// counter for LED on/off duration
+reg    [27:0] steady_count;		    // counter for LED ramp up/down duration
+
+reg    [31:0] red_accum;			// intensity accumulator during ramp
+reg    [31:0] grn_accum;
+reg    [31:0] blu_accum;
+
+reg     [17:0] curr_red;				// current LED intensity ( /256 = PWM duty cycle)
+reg     [17:0] curr_grn;
+reg     [17:0] curr_blu;
+
+reg     [17:0] pwm_count;            // PWM counter
+
+reg [7:0] count = 8'b0;
+
+//------------------------------
+// PLL Instantiation
+//------------------------------
+//Block to reset the PLL initially
+
+pll_24M __(.ref_clk_i(clk12M ), .rst_n_i(~rst), .lock_o(LOCK), .outcore_o( ), .outglobal_o(clk24M));
+
+//Selecting color using "color_sel"
+assign RGB_color = {2'b0,color_sel};
+
+//   Capture stable parameters in local clock domain
+always @ (posedge clk24M or posedge rst)
+    if (rst) begin
+      RGB_color_s   <= 4'b0000;
+      Brightness_s  <= 4'b0111;
+      BreatheRamp_s <= 4'b0000;
+      BlinkRate_s   <= 4'b0101;
+    //end else if(!RGB_Blink_En) begin //TODO ReadWrite Difference
+      //RGB_color_s   <= RGB_color   ;
+      //Brightness_s  <= Brightness  ;
+      //BreatheRamp_s <= 4'b0000 ;
+      //BlinkRate_s   <= 4'b0000  ;
+    end else begin   
+      RGB_color_s   <= RGB_color   ;
+      Brightness_s  <= Brightness  ;
+      BreatheRamp_s <= 4'b0000 ;
+      BlinkRate_s   <= 4'b0000   ;
+      end
+
+
+// interpret 'brightness' setting
+assign red_intensity =  Brightness_s + 1'b1;
+assign grn_intensity = Brightness_s + 1'b1;
+assign blu_intensity = Brightness_s + 1'b1;
+
+
+// interpret 'color' setting
+always @ (RGB_color_s)	 
+  case (RGB_color_s)
+    4'b0000:   begin red_set   <= on_hi; grn_set   <= off;   blu_set   <= off;   end //Red
+    4'b0001:   begin red_set   <= on_hi; grn_set   <= on_lo; blu_set   <= off;   end //Orange
+    4'b0010:   begin red_set   <= off;   grn_set   <= on_hi; blu_set   <= off;   end //Green
+    4'b0011:   begin red_set   <= off;   grn_set   <= on_hi; blu_set   <= on_hi; end //Cyan
+    4'b0100:   begin red_set   <= off;   grn_set   <= on_hi; blu_set   <= on_lo; end //SpringGreen
+    4'b0101:   begin red_set   <= on_hi; grn_set   <= on_hi; blu_set   <= off;   end //Yellow
+    4'b0110:   begin red_set   <= on_lo; grn_set   <= on_hi; blu_set   <= off;   end //Chartreuse
+    4'b0111:   begin red_set   <= off;   grn_set   <= on_lo; blu_set   <= on_hi; end //Azure
+    4'b1000:   begin red_set   <= off;   grn_set   <= off;   blu_set   <= on_hi; end //Blue
+    4'b1001:   begin red_set   <= on_lo; grn_set   <= off;   blu_set   <= on_hi; end //Violet
+    4'b1010:   begin red_set   <= on_hi; grn_set   <= off;   blu_set   <= on_hi; end //Magenta
+    4'b1011:   begin red_set   <= on_hi; grn_set   <= off;   blu_set   <= on_lo; end //Rose
+    4'b1111:   begin red_set   <= on_hi; grn_set   <= on_hi; blu_set   <= on_hi; end //White
+    default: begin red_set   <= off;   grn_set   <= off;   blu_set   <= off;   end //2'b00
+  endcase
+
+// set peak values per 'brightness' and 'color'
+//   when color setting is 'on_lo', then peak intensity is divided by 2
+always @ (posedge clk24M or posedge rst)
+    if (rst) begin
+      red_peak <= 32'b0;
+    end else begin
+      case (red_set)
+        on_hi:  red_peak <= {red_intensity, 27'h000};       // 100%
+        on_lo:  red_peak <= {1'b0,red_intensity, 26'h000}; // 50%
+        default: red_peak <= 32'h00000;
+      endcase
+    end
+    
+always @ (posedge clk24M or posedge rst)
+    if (rst) begin
+      grn_peak <= 32'b0;
+    end else begin
+      case (grn_set)
+        on_hi:  grn_peak <= {grn_intensity, 27'h000};       // 100%
+        on_lo:  grn_peak <= {1'b0,grn_intensity, 26'h000}; // 50%
+        default: grn_peak <= 32'h00000;
+      endcase
+    end
+  
+always @ (posedge clk24M or posedge rst)
+    if (rst) begin
+      blu_peak <= 32'b0;
+    end else begin
+      case (blu_set)
+        on_hi:  blu_peak <= {blu_intensity, 27'h000};       // 100%
+        on_lo:  blu_peak <= {1'b0,blu_intensity, 26'h000}; // 50%
+        default: blu_peak <= 32'h00000;
+      endcase
+    end
+  
+// interpret 'Blink rate' setting
+//   'off_max_cnt' is time spent in 'LED_OFF' states
+//   'step_shift' is used to scale the intensity step size.
+//   Stated period is blink rate with no ramp.  Ramping adds to the period.
+always @ (posedge clk24M or posedge rst)
+    if (rst) begin
+      off_max_cnt <= 28'h0 - 1;
+      //step_shift     <=  4'b0;
+    end else begin
+      case (BlinkRate_s)
+        4'b0001:   begin off_max_cnt   <= 28'h016E35F; end // 1/16sec
+        4'b0010:   begin off_max_cnt   <= 28'h02DC6BE; end // 1/8 sec
+        4'b0011:   begin off_max_cnt   <= 28'h05B8D7B; end // 1/4 sec
+        4'b0100:   begin off_max_cnt   <= 28'h0B71AF6; end // 1/2 sec
+        4'b0101:   begin off_max_cnt   <= 28'h16E35ED; end // 1 sec
+        4'b0110:   begin off_max_cnt   <= 28'h2DC6BDA; end // 2 sec
+        4'b0111:   begin off_max_cnt   <= 28'h5B8D7B3; end // 4 sec
+
+
+        default: begin off_max_cnt   <= 28'h0; end //
+      endcase
+    end
+
+
+// interpret 'Breathe Ramp' setting
+//     'ramp_max_cnt' is time spent in 'RAMP_UP', RAMP_DOWN' states
+//     '***_intensity_step' is calculated to add to color accumulators each ramp step
+always @ (posedge clk24M or posedge rst)
+    if (rst) begin
+      ramp_max_cnt        <= 28'b0;
+      red_intensity_step  <= 28'b0;
+      grn_intensity_step  <= 28'b0;
+      blu_intensity_step  <= 28'b0;
+    end else begin
+      case (BreatheRamp_s)
+        4'b0001: begin
+                ramp_max_cnt   <= 28'h016E35F;  // 1/16sec
+                red_intensity_step  <= red_peak >> (21) ;
+                grn_intensity_step  <= grn_peak >> (21) ;
+                blu_intensity_step  <= blu_peak >> (21) ;
+              end                 
+        4'b0010: begin
+                ramp_max_cnt   <= 28'h02DC6BE;  // 1/8 sec
+               red_intensity_step  <= red_peak >> (22) ;
+                grn_intensity_step  <= grn_peak >> (22) ;
+                blu_intensity_step  <= blu_peak >> (22) ;                
+              end                 
+        4'b0011: begin
+                ramp_max_cnt   <= 28'h05B8D7B;  // 1/4 sec
+                red_intensity_step  <= red_peak >> (23) ;
+                grn_intensity_step  <= grn_peak >> (23) ;
+                blu_intensity_step  <= blu_peak >> (23) ;                 
+              end                 
+        4'b0100: begin
+		ramp_max_cnt   <=28'h0B71AF6;
+               red_intensity_step  <= red_peak >> (24) ;//1/2
+                grn_intensity_step  <= grn_peak >> (24) ;
+                blu_intensity_step  <= blu_peak >> (24) ;               
+              end                 
+        4'b0101: begin
+                ramp_max_cnt   <= 28'h16E35ED;     // 1 sec
+              red_intensity_step  <= red_peak >> (25) ;
+                grn_intensity_step  <= grn_peak >> (25) ;
+                blu_intensity_step  <= blu_peak >> (25) ;
+				              
+              end                 
+        4'b0110: begin
+	ramp_max_cnt   <= 28'h2DC6BDA;
+	      red_intensity_step  <= red_peak >> (26) ; //2 sec
+                grn_intensity_step  <= grn_peak >> (26) ;
+                blu_intensity_step  <= blu_peak >> (26) ;
+                                 
+              end                 
+        4'b0111: begin
+                ramp_max_cnt   <= 28'h5B8D7B3;  // 4 sec
+               red_intensity_step  <= red_peak >> (27) ;
+                grn_intensity_step  <= grn_peak >> (27) ;
+                blu_intensity_step  <= blu_peak >> (27) ;                 
+              end                 
+        default: begin
+                ramp_max_cnt        <= 28'd0; 
+                red_intensity_step  <= 28'b0;
+                grn_intensity_step  <= 28'b0;
+                blu_intensity_step  <= 28'b0;
+              end                 
+      endcase
+    end
+
+//  state machine to create LED ON/OFF/RAMP periods
+//   state machine is held (no cycles) if LED is steady state on/off
+//   state machine is reset to LED_ON state whenever parameters are updated.
+always @ (posedge clk24M or posedge rst)
+    if (rst) begin
+      blink_state <= LED_OFF;
+      ramp_count   <= 28'b0;
+      steady_count <= 28'b0;
+    end else begin
+      if(BlinkRate_s == 4'b0000) begin
+        blink_state <= LED_ON;
+        ramp_count   <= 0;
+        steady_count <= 0;
+      end else if (BlinkRate_s == 4'b1000) begin
+        blink_state <= LED_OFF;
+        ramp_count   <= 0;
+        steady_count <= 0;
+      end else begin
+        case (blink_state)
+          LED_OFF:  begin
+                      if(steady_count >= off_max_cnt) begin
+                        ramp_count   <= 0;
+                        steady_count <= 0;
+                        blink_state <= RAMP_UP;
+                      end else begin
+                        steady_count <= steady_count + 1;
+                      end
+                    end
+          RAMP_UP:  begin
+                      if(ramp_count >= ramp_max_cnt) begin
+                        ramp_count   <= 0;
+                        steady_count <= 0;
+                        blink_state <= LED_ON;
+                      end else begin
+                        ramp_count <= ramp_count + 1;
+                      end
+                    end
+          LED_ON:  begin
+                      if(steady_count >= on_max_cnt) begin
+                        ramp_count   <= 0;
+                        steady_count <= 0;
+                        blink_state <= RAMP_DOWN;
+                      end else begin
+                        steady_count <= steady_count + 1;
+                      end
+                    end
+          RAMP_DOWN:  begin
+                      if(ramp_count >= ramp_max_cnt) begin
+                        ramp_count   <= 0;
+                        steady_count <= 0;
+                        blink_state <= LED_OFF;
+                      end else begin
+                        ramp_count <= ramp_count + 1;
+                      end
+                    end
+          default:  begin
+                      blink_state <= LED_OFF;
+                      ramp_count   <= 28'b0;
+                      steady_count <= 28'b0;
+                    end
+        endcase
+      end
+    end
+
+
+// RampUP/DN accumulators
+always @ (posedge clk24M or posedge rst)
+    if (rst) begin
+      red_accum <= 32'b0;
+      grn_accum <= 32'b0;
+      blu_accum <= 32'b0;
+    end else begin
+      case (blink_state)
+        LED_OFF:  begin
+                    red_accum <= 0;
+                    grn_accum <= 0;
+                    blu_accum <= 0;
+                  end
+        LED_ON:   begin
+//                    red_accum <= red_accum;
+//                    grn_accum <= grn_accum;
+//                    blu_accum <= blu_accum;
+                    red_accum <= red_peak;
+                    grn_accum <= grn_peak;
+                    blu_accum <= blu_peak;
+                  end
+        RAMP_UP:  begin
+                    red_accum <= red_accum + red_intensity_step;
+                    grn_accum <= grn_accum + grn_intensity_step;
+                    blu_accum <= blu_accum + blu_intensity_step;
+                  end
+        RAMP_DOWN: begin
+                    red_accum <= red_accum - red_intensity_step;
+                    grn_accum <= grn_accum - grn_intensity_step;
+                    blu_accum <= blu_accum - blu_intensity_step;
+                  end
+        default: begin
+                    red_accum <= 0;
+                    grn_accum <= 0;
+                    blu_accum <= 0;
+                  end
+      endcase
+    end
+
+
+// set PWM duty cycle. 8-bit resolution 0x100 is 100% on
+always @ (posedge clk24M or posedge rst)
+    if (rst) begin
+	curr_red <= 18'b0;
+      curr_grn <= 18'b0;
+      curr_blu <= 18'b0;
+    end else begin
+      case (blink_state)
+        LED_ON: begin
+                    curr_red <= red_peak[31:14]; // there should be no discrepancy between _peak and _accum in this state
+                    curr_grn <= grn_peak[31:14];
+                    curr_blu <= blu_peak[31:14];
+                  end
+        RAMP_UP: begin
+                    curr_red <= red_accum[31:14];
+                    curr_grn <= grn_accum[31:14];
+                    curr_blu <= blu_accum[31:14];
+                  end
+        RAMP_DOWN: begin
+                    curr_red <= red_accum[31:14];
+                    curr_grn <= grn_accum[31:14];
+                    curr_blu <= blu_accum[31:14];
+                  end
+        LED_OFF: begin
+                    curr_red <= 0;
+                    curr_grn <= 0;
+                    curr_blu <= 0;
+                  end
+        default: begin
+                    curr_red <= 0;
+                    curr_grn <= 0;
+                    curr_blu <= 0;
+                  end
+      endcase
+    end
+
+// generate PWM outputs
+always @ (posedge clk24M or posedge rst)
+    if (rst) begin
+      pwm_count <= 18'b0;
+      red_pwm   <= 0;
+      grn_pwm   <= 0;
+      blu_pwm   <= 0;
+    end else begin
+      if(pwm_count < 131071)
+        pwm_count <= pwm_count + 1;
+      else
+        pwm_count <= 0;
+      
+      if(pwm_count < curr_red)       
+        red_pwm <= 1;
+      else
+        red_pwm <= 0;
+
+      if(pwm_count < curr_grn)
+        grn_pwm <= 1;
+      else
+        grn_pwm <= 0;
+
+      if(pwm_count < curr_blu)    
+        blu_pwm <= 1;
+      else
+        blu_pwm <= 0;  
+		
+    end
+
+
+endmodule // LED_control
+
+

Ampelansteuerung/steuerung.sv

@@ -0,0 +1,63 @@
+module steuerung (
+bus.steuerung_port b, 		//b.dip[3:0], b.timer, b.clk, b.spi_read[1:0] 
+led_if.led_port_top i		//i.rgb[2:0], i.rgbn[2:0]
+);       
+
+//dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
+
+//input wire clk12M,  				-> b.clk   
+//input wire rst,					-> b.dip[0]
+//input wire [1:0] color_sel,		-> b.dip[3:2]
+//input wire rw,					-> b.dip[1]
+//output reg REDn,					-> i.rgbn[0]
+//output reg BLUn,					-> i.rgbn[1]
+//output reg GRNn,					-> i.rgbn[2]
+//output reg RED,					-> i.rgb[0]
+//output reg BLU,					-> i.rgb[1]
+//output reg GRN					-> i.rgb[2]
+ 
+
+wire red_pwm;
+wire grn_pwm;
+wire blu_pwm;
+
+
+defparam U1.on_hi 			= 2'b10;
+defparam U1.on_lo 			= 2'b01;
+defparam U1.off   			= 2'b00; 
+defparam U1.LED_OFF   		= 2'b00;
+defparam U1.RAMP_UP   		= 2'b01;
+defparam U1.LED_ON    		= 2'b10;
+defparam U1.RAMP_DOWN 		= 2'b11;
+defparam U1.on_max_cnt 		= 28'h16E35ED;  // 	1 sec steady
+defparam U1.Brightness		= 4'b0111; 		//	50% Brightness
+defparam U1.BreatheRamp		= 4'b0110; 		//	2x
+defparam U1.BlinkRate		= 4'b0101; 		//	1 sec
+defparam U2.RGB0_CURRENT 	= "0b111111";
+defparam U2.RGB1_CURRENT 	= "0b111111";
+defparam U2.RGB2_CURRENT 	= "0b111111";
+
+LED_control1 U1 (.clk12M(b.clk),.rst(b.dip[0]),.color_sel(b.dip[3:2]),.rw(b.dip[1]),.red_pwm(red_pwm),.blu_pwm(blu_pwm),.grn_pwm(grn_pwm));
+
+
+RGB U2 (.CURREN('b1),.RGB0PWM(blu_pwm),.RGB1PWM(grn_pwm),.RGB2PWM(red_pwm),.RGBLEDEN('b1),.RGB0(i.rgbn[1]),.RGB1(i.rgbn[2]),.RGB2(rgbn[0]));
+
+assign i.rgb[0] = red_pwm;
+assign i.rgb[2] = grn_pwm;
+assign i.rgb[1] = blu_pwm;
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+

Timer.sv

@@ -0,0 +1,41 @@
+//------------------------------------------------------
+//                                                        
+//  File          :  Timer.sv
+//  Related Files :                                                     
+//  Author(s)     :                                
+//  Email         :      
+//  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
+//  Notes         :   
+//
+//------------------------------------------------------
+//                   History    
+//------------------------------------------------------
+//    Version| Author   | Mod. Date  | Changes Made:
+//    v1.00  |  		| 11.05.2023 | 
+//------------------------------------------------------
+//eoh
+
+
+module timer (bus_e bus); // (bus.timer b, clock_if.clock_port_top i)
+
+  integer counter = 0;	// internal count reg
+  integer reload_val;
+
+     
+  always @ (posedge bus.clk or bus.reset) begin	// b.dip[0]  <---- soll reset sein   i.clk <-- busclk
+    if (!bus.reset) begin
+      counter <= 0;
+	  bus.out_10s <= 0;  // b.timer <--- out_10s
+    end else begin
+  	  if(counter <= 100) begin  // zu testzwecken kürzer 1000000
+		counter++;
+		bus.out_10s <= 0;
+	  end else begin
+		counter <= 0;
+		bus.out_10s <= 1;
+      end
+	end
+
+  end
+
+endmodule : timer

fram_interface.sv

@@ -0,0 +1,84 @@
+`include "FRAM_Controller.sv"
+
+module spi(bus.spi_port b, fram_if.fram_port_top i);
+  parameter ringbuffer_size = 256;
+  
+  logic [19:0] FRAM_Adr;
+  logic [7:0] FRAM_DATA_OUT;
+  logic [7:0] FRAM_DATA_IN;
+  logic FRAM_RW;
+  logic FRAM_RSTATUS;
+  logic FRAM_hbn;
+  logic FRAM_go;
+  logic FRAM_busy;
+  
+  logic [7:0] clk_cntr;
+
+  initial begin    
+    FRAM_Adr <= 20'h0;
+    FRAM_DATA_IN <= 8'h0;
+  	FRAM_RW = 0;
+  	FRAM_RSTATUS = 0;
+  	FRAM_hbn = 0;
+  	FRAM_go = 0;
+    clk_cntr = 0;
+  end
+  
+  always @ (posedge b.timer) begin
+    if(b.dip[0] == 0) begin  //Reset
+      FRAM_Adr <= 20'h0;
+      FRAM_DATA_IN <= 8'h0;
+      FRAM_RW = 0;
+      FRAM_RSTATUS = 0;
+      FRAM_hbn = 0;
+      FRAM_go = 0;
+      clk_cntr = 0;
+    end
+    else if(b.dip[1] == 1) begin //Read
+      FRAM_Adr <= (FRAM_Adr - 1) % (ringbuffer_size - 1);
+      FRAM_RW <= 1'h1; //Read
+      FRAM_go <= 1'h1; //Go
+    end 
+    else if(b.dip[1] == 0) begin //Write
+      FRAM_Adr <= (FRAM_Adr + 1) % (ringbuffer_size - 1);
+      FRAM_DATA_IN <= {6'h0, b.dip[4:3]};
+      FRAM_RW <= 1'h0; //Write Operation
+      FRAM_go <= 1'h1; //Go
+    end      
+  end
+  
+  always @ (posedge b.oszi_clk) begin
+    if(FRAM_go == 1) 
+      clk_cntr <= clk_cntr + 1;
+    
+    if(clk_cntr > 50 && FRAM_RW == 1'h1) begin
+      b.spi_read <= FRAM_DATA_OUT[1:0];
+      FRAM_go <= 1'h0;
+      FRAM_RW <= 1'h0; 
+      clk_cntr <= 0;
+    end
+    else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin
+      FRAM_go <= 1'h0;
+      clk_cntr <= 0;
+    end
+  end
+  
+  
+    FRAM FRAM_ut(
+    .i_clk(b.oszi_clk),
+    .i_nreset(b.dip[0]),
+    .i_adr(FRAM_Adr),
+    .i_data(FRAM_DATA_IN),
+    .o_data(FRAM_DATA_OUT),
+    .i_rw(FRAM_RW),
+    .i_status(FRAM_RSTATUS),
+    .i_hbn(FRAM_hbn),
+    .i_cready(FRAM_go),
+    .o_busy(FRAM_busy),
+    .o_SPI_Clk(i.sclk),
+    .i_SPI_MISO(i.mosi),
+    .o_SPI_MOSI(i.mosi), 
+    .o_SPI_CS_n(i.ss)
+  );
+  
+endmodule

interface.sv

@@ -0,0 +1,70 @@
+//------------------------------------------------------
+//                                                        
+//  File          :  interface.sv
+//  Related Files :                                                     
+//  Author(s)     :  Mueller                              
+//  Email         :  muelleral82290@th-nuernberg.de       
+//  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
+//  Notes         :  Stimuli Modul 
+//
+//------------------------------------------------------
+//                   History    
+//------------------------------------------------------
+//    Version| Author   | Mod. Date  | Changes Made:
+//    v1.00  | Mueller  | 11/05/2023 | first code
+//------------------------------------------------------
+//eoh
+
+
+//interface for LED
+//reg [2:0]rbg stores rgb values that depend on dip[3:2]
+interface led_if();
+
+	logic [2:0]rgb;
+	logic [2:0]rgbn;
+
+	modport led_port_stim(input rgb, rgbn);
+	modport led_port_top(output rgb, rgbn);
+	
+
+endinterface : led_if
+
+//interface for DIPSCHALER
+// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
+interface dip_if();
+
+	logic [3:0]dip;
+
+	modport dip_port_stim(output dip);
+	modport dip_port_top(input dip);
+
+endinterface : dip_if
+
+//interface for FRAM
+// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
+// clk -> system clock / timer
+// miso -> testbench output
+// mosi -> testbench input
+interface fram_if();
+
+	logic ss;
+	logic mosi;
+	logic miso;
+	logic sclk;
+
+	modport fram_port_stim(input mosi, sclk, ss, output miso);
+	modport fram_port_top(output mosi, sclk, ss, input miso);
+
+endinterface : fram_if
+
+//testbenchclock replaces the oscillator on the board
+interface clock_if();
+
+	logic clk;
+
+	modport clock_port_stim(output clk);
+	modport clock_port_top(input clk);
+
+endinterface : clock_if
+
+

top_level.sv

@@ -0,0 +1,109 @@
+// Definition of top level
+module top(led_if.led_port_top l, dip_if.dip_port_top d, fram_if.fram_port_top f, clock_if.clock_port_top c);
+	
+	// Initialisation of bus
+	bus fpga_bus();
+		
+	// Initialisation of modules
+	timer t(fpga_bus, c);
+	steuerung st(fpga_bus, l); 
+	spi s(fpga_bus, f);
+	parallelport p(fpga_bus, d);
+endmodule : top
+
+// Definition of bus interface
+interface bus();
+	// bus wires
+	logic clk; // clock
+	logic timer;
+	logic [3:0]dip;
+	logic [1:0]spi_read;
+	
+	// modports from modules pov
+	modport timer_port(input dip, output timer, clk);			//dip[0]
+	modport parallel_port(output dip);
+	modport steuerung_port(input dip, timer, clk, spi_read);	//dip[3:0] / spi_read[1:0]
+	modport spi_port(input dip, timer, clk, output spi_read);	//spi_read[1:0]
+endinterface : bus
+
+// Definition of parallelport
+module parallelport(bus.parallel_port b, dip_if.dip_port_top d);
+	//b.dip <= d.dip;	
+endmodule
+
+module spi(bus.spi_port b, fram_if.fram_port_top i);
+	/*...
+	b.dip[3:0], b.timer, b.spi_read[1:0]
+	i.ss, i.mosi, i.miso, i.sclk
+	...*/
+endmodule
+
+module timer(bus.timer_port b, clock_if.clock_port_top i);
+	/*...
+	b.clk, b.dip[0], b.timer
+	i.clk
+	...*/
+endmodule
+
+module steuerung(bus.steuerung_port b, led_if.led_port_top i);
+	/*...
+	b.dip[3:0], b.timer, b.spi_read[1:0]
+	i.rgb[2:0]
+	...*/
+endmodule
+
+/*   
+_______________________________________________________________________________________________________________
+Testbench
+					__________________										 		___________________
+				   |				  |												|				    |
+				   |   DIP-Schalter	  |												|	FRAM-Speicher   |
+				   |				  |												|				    |
+				   |__________________|												|___________________|
+							|																 |
+____________________________|________________________________________________________________|_________________
+Toplevel					|																 |
+							|																 |
+				 dip[3:0]-->|																 |<--mosi, miso, sclk, ss
+							|												  				 |
+					________|_________											     ________|__________
+				   |				  |												|				    |
+				   |   Parallelport	  |												| SPI-Schnittstelle |
+				   |				  |												| & FRAM-Kontroller	|
+				   |__________________|												|___________________|
+							|																 |
+							|																 |
+				 dip[3:0]-->|																 |<--dip[3:0], timer, spi_read[1:0]
+							|																 |
+							|																 |
+							---------------------------------------------------------------------BUS
+							|																 |
+							|																 |
+       dip[0], clk, timer-->|																 |<--dip[3:0], timer, spi_read[1:0]
+							|																 |
+					________|_________			___________________			     	 ________|__________
+				   |				  |		   |				   |				|				    |
+				   |      Timer		  |		   |  Oszillator-Takt  |				|  Ampel-Steuerung  |
+				   |				  |		   |    (auf Board)	   |				|				    |
+				   |__________________|		   |___________________|				|___________________|
+							|	                         |                                   |
+							|							 |									 |
+				 	  clk-->------------------------------									 |<--rgb[2:0]
+							|																 |
+____________________________|________________________________________________________________|___________________
+							|																 |
+				 	________|_________										 		 ________|__________
+				   |				  |												|				    |
+				   |       Takt		  |												|	   RGB-LED		|
+				   |  (der Testbench) |												|				    |
+				   |__________________|												|___________________|
+
+
+__________________________________________________________________________________________________________________
+
+*/
+
+
+
+
+

transcript

@@ -0,0 +1,14 @@
+# //  Questa Sim-64
+# //  Version 2019.4 linux_x86_64 Oct 15 2019
+# //
+# //  Copyright 1991-2019 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //

uebung_projekt/compilescripts/simulation/compile.tcl

@@ -0,0 +1,46 @@
+## -------------------------------------------------------------
+##                                                                       
+##  File          :  compile.tcl    
+##  Author(s)     :  Baesig      
+##					 Gerstner                                       
+##  Email         :  juergen.baesig@fh-nuernberg.de 
+##					 Gerstnermi46611@th-nuernberg.de                    
+##  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg                      
+##                             
+##  Note          :   
+##         
+## -------------------------------------------------------------
+##                                 History    
+## -------------------------------------------------------------
+##    Version| Author   | Mod. Date  | Changes Made:
+##    v1.00  | Baesig   | 09/04/2012 | first code
+##    v1.01  | Gerstner | 20/09/2013 | modified
+## -------------------------------------------------------------
+##eoh
+
+.main clear
+
+echo
+# ----------------------------------------------------------
+echo "create workspace"
+ if [file exists work] { vdel -all }
+ vlib work
+ vmap work ./work
+echo
+# ----------------------------------------------------------
+echo " Compile sv-Designfiles "
+vlog -work work ./hdl_src/sv/interface.sv
+vlog -work work ./hdl_src/sv/stimuli.sv
+vlog -work work ./hdl_src/sv/top_level.sv
+vlog -work work ./hdl_src/sv/top_tb.sv
+vlog -work work ./hdl_src/sv/timer.sv
+vlog -work work ./hdl_src/sv/SPI_Master_Control.sv
+vlog -work work ./hdl_src/sv/SPI_Master.sv
+vlog -work work ./hdl_src/sv/FRAM_Controller.sv
+vlog -work work ./hdl_src/sv/fram.sv
+
+echo
+# ----------------------------------------------------------
+echo " Run Simulation "
+source ./simulationsscripts/simulation.tcl
+

uebung_projekt/hdl_src/sv/FRAM_Controller.sv

@@ -0,0 +1,197 @@
+module FRAM(
+  input i_clk, //Module (Module CLock = SPI Clock)
+  input i_nreset,
+  
+  input logic [19:0] i_adr, //Memorycell adress in FRAM
+  input logic [7:0] i_data, //data to write
+  output logic [7:0] o_data, //data to read
+  
+  input logic i_rw, //Read = 1, Write = 0
+  input logic i_status, //If 1 Read Staut register
+  input logic i_hbn, //If 1 FRAM will enter Hibernation Mode
+  input logic i_cready, //Starts transmission 
+  output logic o_busy, //Indicates FRAM Busy
+  
+  // SPI Interface
+  output o_SPI_Clk,
+  input  i_SPI_MISO,
+  output o_SPI_MOSI,
+  output o_SPI_CS_n  
+
+);
+  
+  
+  //FRAM SPI OP Codes
+
+  //Write Enable Control
+  localparam WREN = 8'h06; //Set Write enable latch
+  localparam WRDI = 8'h04; //Reset write enable latch
+  //Register Access
+  localparam RDSR = 8'h05; //Read Status Register
+  localparam WRSR = 8'h01; //Write Status Register
+  //Memory Write
+  localparam WRITE = 8'h02; //Write Memory Data
+  //Memory Read
+  localparam READ = 8'h03; //Read Memory Data
+  localparam FSTRT = 8'h0B; //Fast read memory Data
+  //Special Sector Memory Access
+  localparam SSWR = 8'h42; //Spcial Sector Write
+  localparam SSRD = 8'h4B; //Special Sector Read
+  //Identification and serial Number
+  localparam RDID = 8'h9F; //Read Device ID
+  localparam RUID = 8'h4C; //Read Unique ID
+  localparam WRSN = 8'hC2; //Write Serial Number
+  localparam RDSN = 8'hC3; //Read Serial Number
+  //Low Power Modes
+  localparam DPD = 8'hBA; // Enter Deep Power-Down
+  localparam HBN = 8'hB9; // Enter Hibernate Mode
+  //end FRAM SPI OP Codes
+  
+  //Controller Specific
+  logic [3:0] state;
+  
+  
+  // SPI Specific
+  parameter SPI_MODE = 0;          // CPOL = 0, CPHA = 0
+  parameter CLKS_PER_HALF_BIT = 2; // 25MHz
+  parameter MAX_BYTES_PER_CS = 5;  // 5 bytes max per chip select cycle
+  parameter CS_INACTIVE_CLKS = 1;  // Adds delay (1clk) between cycles
+  
+  
+  logic [7:0] r_Master_TX_Byte = 0;
+  logic r_Master_TX_DV = 1'b0;
+  logic w_Master_TX_Ready;
+  logic w_Master_RX_DV;
+  logic [7:0] w_Master_RX_Byte;
+  logic [$clog2(MAX_BYTES_PER_CS+1)-1:0] w_Master_RX_Count, r_Master_TX_Count = 3'h1; //Standard 1 Byte pro CS Cycle
+ 
+  
+      
+  SPI_Master_With_Single_CS
+  #(.SPI_MODE(SPI_MODE), //SPI Mode 0-3
+    .CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT), //sets Frequency of SPI_CLK
+    .MAX_BYTES_PER_CS(MAX_BYTES_PER_CS), //Maximum Bytes per CS Cycle
+    .CS_INACTIVE_CLKS(CS_INACTIVE_CLKS) //Amount of Time holding CS Low befor next command
+   ) SPI
+  (
+   // Control/Data Signals,
+    .i_Rst_L(i_nreset),     // FPGA Reset
+    .i_Clk(i_clk),         // FPGA Clock
+   
+   // TX (MOSI) Signals
+   .i_TX_Count(r_Master_TX_Count),   // Number of bytes per CS
+   .i_TX_Byte(r_Master_TX_Byte),     // Byte to transmit on MOSI
+   .i_TX_DV(r_Master_TX_DV),         // Data Valid Pulse with i_TX_Byte
+   .o_TX_Ready(w_Master_TX_Ready),   // Transmit Ready for Byte
+   
+   // RX (MISO) Signals
+   .o_RX_Count(w_Master_RX_Count), // Index of RX'd byte
+   .o_RX_DV(w_Master_RX_DV),       // Data Valid pulse (1 clock cycle)
+   .o_RX_Byte(w_Master_RX_Byte),   // Byte received on MISO
+
+   // SPI Interface
+   .o_SPI_Clk(o_SPI_Clk),
+   .i_SPI_MISO(i_SPI_MISO),
+   .o_SPI_MOSI(o_SPI_MOSI),
+   .o_SPI_CS_n(o_SPI_CS_n)
+   );
+  
+  //end SPI Specific
+  
+  
+  task SPI_SendByte(input [7:0] data);
+    @(posedge i_clk);       
+    r_Master_TX_Byte <= data;
+    r_Master_TX_DV   <= 1'b1;
+    @(posedge i_clk);
+    r_Master_TX_DV <= 1'b0;
+    @(posedge i_clk);
+    @(posedge w_Master_TX_Ready);    
+  endtask //end SPI_SendByte
+  
+  //FRAM Tasks
+  task FRAM_Write(input [19:0] adr, input [7:0] data); //vgl. Fig.11
+  	
+    logic [7:0] value;
+    value <= 8'h0;
+    
+    //Set Write Enable
+    r_Master_TX_Count <= 3'b1; //1Byte Transaction
+    SPI_SendByte(WREN);
+    
+    //Write to fram
+    r_Master_TX_Count <= 3'h5; //5 Byte Transaction 
+    SPI_SendByte(WRITE); //OPCode
+    SPI_SendByte({4'hF,adr[19:16]}); //Adress [23-16]
+    SPI_SendByte(adr[15:8]); //Adress [15-8]
+    SPI_SendByte(adr[7:0]); //Adress [7-0]
+    SPI_SendByte(data); //Data [7:0]
+    
+    //Reset Write Disable and Verify    
+    do begin
+      r_Master_TX_Count <= 3'b1; //1Byte Transaction 
+      SPI_SendByte(WRDI); //Set Write Disable    
+    
+      FRAM_Read_Status(value); //Lese Status Register
+    end while(((value & 8'h2) >> 1) != 0);
+    
+        
+  endtask //end FRAM_Write
+  
+  task FRAM_Read(input [19:0] adr, output [7:0] data); //vgl. Fig12
+    r_Master_TX_Count <= 3'h5; //5 Byte Transaction
+    SPI_SendByte(READ); //Opcode
+    SPI_SendByte({4'hF,adr[19:16]}); //Adress [23-16]
+    SPI_SendByte(adr[15:8]); //Adress [15-8]
+    SPI_SendByte(adr[7:0]); //Adress [7-0]
+    
+    SPI_SendByte(8'hAA); //Dummy Bits, read byte in w_Master_RX_Byte
+    data = w_Master_RX_Byte;
+    
+  endtask //end FRAM_READ
+  
+  task FRAM_Read_Status(output [7:0] data); //vgl. Fig9
+    r_Master_TX_Count <= 3'h2; //2 Byte Transaction
+    SPI_SendByte(RDSR); //OpCode
+    SPI_SendByte(8'hFD); //Dummy Bits, read byte in w_Master_RX_Byte
+    data = w_Master_RX_Byte;
+  endtask //FRAM_Read_Status
+  
+  task FRAM_Hibernation(); //vgl. Fig22
+    r_Master_TX_Count <= 3'h1; //1 Byte Transaction
+    SPI_SendByte(HBN);    
+  endtask //FRAM_Hibernation
+  
+  
+  //end FRAM Tasks
+  
+  
+  always @(posedge i_clk or negedge i_nreset) begin
+ 
+    state[0] = i_cready;
+    state[1] = i_hbn;
+    state[2] = i_status;
+    state[3] = i_rw;    
+        
+    if(~i_nreset) begin //Modul Reset
+      o_data <=  8'h00;
+    end //end if
+    
+    if(w_Master_TX_Ready) begin
+    	case(state) inside
+          4'b??11: FRAM_Hibernation();
+          4'b?101: FRAM_Read_Status(o_data);
+          4'b1001: FRAM_Read(i_adr, o_data);
+          4'b0001: FRAM_Write(i_adr, i_data);
+      		
+      	  default:; 
+        endcase //endcase
+    end //endif
+
+  end //end always
+  
+    
+  assign o_busy = w_Master_TX_Ready; 
+  
+  
+endmodule

uebung_projekt/hdl_src/sv/SPI_Master.sv

@@ -0,0 +1,188 @@
+///////////////////////////////////////////////////////////////////////////////
+//Source: https://github.com/nandland/spi-master/tree/master/Verilog/source 
+//Description: SPI (Serial Peripheral Interface) Master
+//              With single chip-select (AKA Slave Select) capability
+//
+//              Supports arbitrary length byte transfers.
+// 
+//              Instantiates a SPI Master and adds single CS.
+//              If multiple CS signals are needed, will need to use different
+//              module, OR multiplex the CS from this at a higher level.
+//
+// Note:        i_Clk must be at least 2x faster than i_SPI_Clk
+//
+// Parameters:  SPI_MODE, can be 0, 1, 2, or 3.  See above.
+//              Can be configured in one of 4 modes:
+//              Mode | Clock Polarity (CPOL/CKP) | Clock Phase (CPHA)
+//               0   |             0             |        0
+//               1   |             0             |        1
+//               2   |             1             |        0
+//               3   |             1             |        1
+//
+//              CLKS_PER_HALF_BIT - Sets frequency of o_SPI_Clk.  o_SPI_Clk is
+//              derived from i_Clk.  Set to integer number of clocks for each
+//              half-bit of SPI data.  E.g. 100 MHz i_Clk, CLKS_PER_HALF_BIT = 2
+//              would create o_SPI_CLK of 25 MHz.  Must be >= 2
+//
+//              MAX_BYTES_PER_CS - Set to the maximum number of bytes that
+//              will be sent during a single CS-low pulse.
+// 
+//              CS_INACTIVE_CLKS - Sets the amount of time in clock cycles to
+//              hold the state of Chip-Selct high (inactive) before next 
+//              command is allowed on the line.  Useful if chip requires some
+//              time when CS is high between trasnfers.
+///////////////////////////////////////////////////////////////////////////////
+
+
+
+module SPI_Master_With_Single_CS
+  #(parameter SPI_MODE = 0,
+    parameter CLKS_PER_HALF_BIT = 2,
+    parameter MAX_BYTES_PER_CS = 1,
+    parameter CS_INACTIVE_CLKS = 1)
+  (
+   // Control/Data Signals,
+   input        i_Rst_L,     // FPGA Reset
+   input        i_Clk,       // FPGA Clock
+   
+   // TX (MOSI) Signals
+   input [$clog2(MAX_BYTES_PER_CS+1)-1:0] i_TX_Count,  // # bytes per CS low
+   input [7:0]  i_TX_Byte,       // Byte to transmit on MOSI
+   input        i_TX_DV,         // Data Valid Pulse with i_TX_Byte
+   output       o_TX_Ready,      // Transmit Ready for next byte
+   
+   // RX (MISO) Signals
+   output reg [$clog2(MAX_BYTES_PER_CS+1)-1:0] o_RX_Count,  // Index RX byte
+   output       o_RX_DV,     // Data Valid pulse (1 clock cycle)
+   output [7:0] o_RX_Byte,   // Byte received on MISO
+
+   // SPI Interface
+   output o_SPI_Clk,
+   input  i_SPI_MISO,
+   output o_SPI_MOSI,
+   output o_SPI_CS_n
+   );
+
+  localparam IDLE        = 2'b00;
+  localparam TRANSFER    = 2'b01;
+  localparam CS_INACTIVE = 2'b10;
+
+  reg [1:0] r_SM_CS;
+  reg r_CS_n;
+  reg [$clog2(CS_INACTIVE_CLKS)-1:0] r_CS_Inactive_Count;
+  reg [$clog2(MAX_BYTES_PER_CS+1)-1:0] r_TX_Count;
+  wire w_Master_Ready;
+
+  // Instantiate Master
+  SPI_Master 
+    #(.SPI_MODE(SPI_MODE),
+      .CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT)
+     ) SPI_Master_Inst
+   (
+   // Control/Data Signals,
+   .i_Rst_L(i_Rst_L),     // FPGA Reset
+   .i_Clk(i_Clk),         // FPGA Clock
+   
+   // TX (MOSI) Signals
+   .i_TX_Byte(i_TX_Byte),         // Byte to transmit
+   .i_TX_DV(i_TX_DV),             // Data Valid Pulse 
+   .o_TX_Ready(w_Master_Ready),   // Transmit Ready for Byte
+   
+   // RX (MISO) Signals
+   .o_RX_DV(o_RX_DV),       // Data Valid pulse (1 clock cycle)
+   .o_RX_Byte(o_RX_Byte),   // Byte received on MISO
+
+   // SPI Interface
+   .o_SPI_Clk(o_SPI_Clk),
+   .i_SPI_MISO(i_SPI_MISO),
+   .o_SPI_MOSI(o_SPI_MOSI)
+   );
+
+
+  // Purpose: Control CS line using State Machine
+  always @(posedge i_Clk or negedge i_Rst_L)
+  begin
+    if (~i_Rst_L)
+    begin
+      r_SM_CS <= IDLE;
+      r_CS_n  <= 1'b1;   // Resets to high
+      r_TX_Count <= 0;
+      r_CS_Inactive_Count <= CS_INACTIVE_CLKS;
+    end
+    else
+    begin
+
+      case (r_SM_CS)      
+      IDLE:
+        begin
+          if (r_CS_n & i_TX_DV) // Start of transmission
+          begin
+            r_TX_Count <= i_TX_Count - 1; // Register TX Count
+            r_CS_n     <= 1'b0;       // Drive CS low
+            r_SM_CS    <= TRANSFER;   // Transfer bytes
+          end
+        end
+
+      TRANSFER:
+        begin
+          // Wait until SPI is done transferring do next thing
+          if (w_Master_Ready)
+          begin
+            if (r_TX_Count > 0)
+            begin
+              if (i_TX_DV)
+              begin
+                r_TX_Count <= r_TX_Count - 1;
+              end
+            end
+            else
+            begin
+              r_CS_n  <= 1'b1; // we done, so set CS high
+              r_CS_Inactive_Count <= CS_INACTIVE_CLKS;
+              r_SM_CS             <= CS_INACTIVE;
+            end // else: !if(r_TX_Count > 0)
+          end // if (w_Master_Ready)
+        end // case: TRANSFER
+
+      CS_INACTIVE:
+        begin
+          if (r_CS_Inactive_Count > 0)
+          begin
+            r_CS_Inactive_Count <= r_CS_Inactive_Count - 1'b1;
+          end
+          else
+          begin
+            r_SM_CS <= IDLE;
+          end
+        end
+
+      default:
+        begin
+          r_CS_n  <= 1'b1; // we done, so set CS high
+          r_SM_CS <= IDLE;
+        end
+      endcase // case (r_SM_CS)
+    end
+  end // always @ (posedge i_Clk or negedge i_Rst_L)
+
+
+  // Purpose: Keep track of RX_Count
+  always @(posedge i_Clk)
+  begin
+    begin
+      if (r_CS_n)
+      begin
+        o_RX_Count <= 0;
+      end
+      else if (o_RX_DV)
+      begin
+        o_RX_Count <= o_RX_Count + 1'b1;
+      end
+    end
+  end
+
+  assign o_SPI_CS_n = r_CS_n;
+
+  assign o_TX_Ready  = ((r_SM_CS == IDLE) | (r_SM_CS == TRANSFER && w_Master_Ready == 1'b1 && r_TX_Count > 0)) & ~i_TX_DV;
+
+endmodule // SPI_Master_With_Single_CS

uebung_projekt/hdl_src/sv/SPI_Master_Control.sv

@@ -0,0 +1,240 @@
+//////////////////////////////////////////////////////////////////////////////
+//Source: https://github.com/nandland/spi-master/tree/master/Verilog/source
+// Description: SPI (Serial Peripheral Interface) Master
+//              Creates master based on input configuration.
+//              Sends a byte one bit at a time on MOSI
+//              Will also receive byte data one bit at a time on MISO.
+//              Any data on input byte will be shipped out on MOSI.
+//
+//              To kick-off transaction, user must pulse i_TX_DV.
+//              This module supports multi-byte transmissions by pulsing
+//              i_TX_DV and loading up i_TX_Byte when o_TX_Ready is high.
+//
+//              This module is only responsible for controlling Clk, MOSI, 
+//              and MISO.  If the SPI peripheral requires a chip-select, 
+//              this must be done at a higher level.
+//
+// Note:        i_Clk must be at least 2x faster than i_SPI_Clk
+//
+// Parameters:  SPI_MODE, can be 0, 1, 2, or 3.  See above.
+//              Can be configured in one of 4 modes:
+//              Mode | Clock Polarity (CPOL/CKP) | Clock Phase (CPHA)
+//               0   |             0             |        0
+//               1   |             0             |        1
+//               2   |             1             |        0
+//               3   |             1             |        1
+//              More: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#Mode_numbers
+//              CLKS_PER_HALF_BIT - Sets frequency of o_SPI_Clk.  o_SPI_Clk is
+//              derived from i_Clk.  Set to integer number of clocks for each
+//              half-bit of SPI data.  E.g. 100 MHz i_Clk, CLKS_PER_HALF_BIT = 2
+//              would create o_SPI_CLK of 25 MHz.  Must be >= 2
+//
+///////////////////////////////////////////////////////////////////////////////
+
+module SPI_Master
+  #(parameter SPI_MODE = 0,
+    parameter CLKS_PER_HALF_BIT = 2)
+  (
+   // Control/Data Signals,
+   input        i_Rst_L,     // FPGA Reset
+   input        i_Clk,       // FPGA Clock
+   
+   // TX (MOSI) Signals
+   input [7:0]  i_TX_Byte,        // Byte to transmit on MOSI
+   input        i_TX_DV,          // Data Valid Pulse with i_TX_Byte
+   output reg   o_TX_Ready,       // Transmit Ready for next byte
+   
+   // RX (MISO) Signals
+   output reg       o_RX_DV,     // Data Valid pulse (1 clock cycle)
+   output reg [7:0] o_RX_Byte,   // Byte received on MISO
+
+   // SPI Interface
+   output reg o_SPI_Clk,
+   input      i_SPI_MISO,
+   output reg o_SPI_MOSI
+   );
+
+  // SPI Interface (All Runs at SPI Clock Domain)
+  wire w_CPOL;     // Clock polarity
+  wire w_CPHA;     // Clock phase
+
+  reg [$clog2(CLKS_PER_HALF_BIT*2)-1:0] r_SPI_Clk_Count;
+  reg r_SPI_Clk;
+  reg [4:0] r_SPI_Clk_Edges;
+  reg r_Leading_Edge;
+  reg r_Trailing_Edge;
+  reg       r_TX_DV;
+  reg [7:0] r_TX_Byte;
+
+  reg [2:0] r_RX_Bit_Count;
+  reg [2:0] r_TX_Bit_Count;
+
+  // CPOL: Clock Polarity
+  // CPOL=0 means clock idles at 0, leading edge is rising edge.
+  // CPOL=1 means clock idles at 1, leading edge is falling edge.
+  assign w_CPOL  = (SPI_MODE == 2) | (SPI_MODE == 3);
+
+  // CPHA: Clock Phase
+  // CPHA=0 means the "out" side changes the data on trailing edge of clock
+  //              the "in" side captures data on leading edge of clock
+  // CPHA=1 means the "out" side changes the data on leading edge of clock
+  //              the "in" side captures data on the trailing edge of clock
+  assign w_CPHA  = (SPI_MODE == 1) | (SPI_MODE == 3);
+
+
+
+  // Purpose: Generate SPI Clock correct number of times when DV pulse comes
+  always @(posedge i_Clk or negedge i_Rst_L)
+  begin
+    if (~i_Rst_L)
+    begin
+      o_TX_Ready      <= 1'b0;
+      r_SPI_Clk_Edges <= 0;
+      r_Leading_Edge  <= 1'b0;
+      r_Trailing_Edge <= 1'b0;
+      r_SPI_Clk       <= w_CPOL; // assign default state to idle state
+      r_SPI_Clk_Count <= 0;
+    end
+    else
+    begin
+
+      // Default assignments
+      r_Leading_Edge  <= 1'b0;
+      r_Trailing_Edge <= 1'b0;
+      
+      if (i_TX_DV)
+      begin
+        o_TX_Ready      <= 1'b0;
+        r_SPI_Clk_Edges <= 16;  // Total # edges in one byte ALWAYS 16
+      end
+      else if (r_SPI_Clk_Edges > 0)
+      begin
+        o_TX_Ready <= 1'b0;
+        
+        if (r_SPI_Clk_Count == CLKS_PER_HALF_BIT*2-1)
+        begin
+          r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1;
+          r_Trailing_Edge <= 1'b1;
+          r_SPI_Clk_Count <= 0;
+          r_SPI_Clk       <= ~r_SPI_Clk;
+        end
+        else if (r_SPI_Clk_Count == CLKS_PER_HALF_BIT-1)
+        begin
+          r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1;
+          r_Leading_Edge  <= 1'b1;
+          r_SPI_Clk_Count <= r_SPI_Clk_Count + 1;
+          r_SPI_Clk       <= ~r_SPI_Clk;
+        end
+        else
+        begin
+          r_SPI_Clk_Count <= r_SPI_Clk_Count + 1;
+        end
+      end  
+      else
+      begin
+        o_TX_Ready <= 1'b1;
+      end
+      
+      
+    end // else: !if(~i_Rst_L)
+  end // always @ (posedge i_Clk or negedge i_Rst_L)
+
+
+  // Purpose: Register i_TX_Byte when Data Valid is pulsed.
+  // Keeps local storage of byte in case higher level module changes the data
+  always @(posedge i_Clk or negedge i_Rst_L)
+  begin
+    if (~i_Rst_L)
+    begin
+      r_TX_Byte <= 8'h00;
+      r_TX_DV   <= 1'b0;
+    end
+    else
+      begin
+        r_TX_DV <= i_TX_DV; // 1 clock cycle delay
+        if (i_TX_DV)
+        begin
+          r_TX_Byte <= i_TX_Byte;
+        end
+      end // else: !if(~i_Rst_L)
+  end // always @ (posedge i_Clk or negedge i_Rst_L)
+
+
+  // Purpose: Generate MOSI data
+  // Works with both CPHA=0 and CPHA=1
+  always @(posedge i_Clk or negedge i_Rst_L)
+  begin
+    if (~i_Rst_L)
+    begin
+      o_SPI_MOSI     <= 1'b0;
+      r_TX_Bit_Count <= 3'b111; // send MSb first
+    end
+    else
+    begin
+      // If ready is high, reset bit counts to default
+      if (o_TX_Ready)
+      begin
+        r_TX_Bit_Count <= 3'b111;
+      end
+      // Catch the case where we start transaction and CPHA = 0
+      else if (r_TX_DV & ~w_CPHA)
+      begin
+        o_SPI_MOSI     <= r_TX_Byte[3'b111];
+        r_TX_Bit_Count <= 3'b110;
+      end
+      else if ((r_Leading_Edge & w_CPHA) | (r_Trailing_Edge & ~w_CPHA))
+      begin
+        r_TX_Bit_Count <= r_TX_Bit_Count - 1;
+        o_SPI_MOSI     <= r_TX_Byte[r_TX_Bit_Count];
+      end
+    end
+  end
+
+
+  // Purpose: Read in MISO data.
+  always @(posedge i_Clk or negedge i_Rst_L)
+  begin
+    if (~i_Rst_L)
+    begin
+      o_RX_Byte      <= 8'h00;
+      o_RX_DV        <= 1'b0;
+      r_RX_Bit_Count <= 3'b111;
+    end
+    else
+    begin
+
+      // Default Assignments
+      o_RX_DV   <= 1'b0;
+
+      if (o_TX_Ready) // Check if ready is high, if so reset bit count to default
+      begin
+        r_RX_Bit_Count <= 3'b111;
+      end
+      else if ((r_Leading_Edge & ~w_CPHA) | (r_Trailing_Edge & w_CPHA))
+      begin
+        o_RX_Byte[r_RX_Bit_Count] <= i_SPI_MISO;  // Sample data
+        r_RX_Bit_Count            <= r_RX_Bit_Count - 1;
+        if (r_RX_Bit_Count == 3'b000)
+        begin
+          o_RX_DV   <= 1'b1;   // Byte done, pulse Data Valid
+        end
+      end
+    end
+  end
+  
+  
+  // Purpose: Add clock delay to signals for alignment.
+  always @(posedge i_Clk or negedge i_Rst_L)
+  begin
+    if (~i_Rst_L)
+    begin
+      o_SPI_Clk  <= w_CPOL;
+    end
+    else
+      begin
+        o_SPI_Clk <= r_SPI_Clk;
+      end // else: !if(~i_Rst_L)
+  end // always @ (posedge i_Clk or negedge i_Rst_L)
+  
+
+endmodule // SPI_Master

uebung_projekt/hdl_src/sv/assert_file.txt

@@ -0,0 +1,40 @@
+//------------------------------------------------------
+//                                                        
+//  File          :  assert_file.sv
+//  Related Files :                                                     
+//  Author(s)     :  Mueller                              
+//  Email         :  muelleral82290@th-nuernberg.de       
+//  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
+//  Notes         :  Stimuli Modul 
+//
+//------------------------------------------------------
+//                   History    
+//------------------------------------------------------
+//    Version| Author   | Mod. Date  | Changes Made:
+//    v1.00  | Mueller  | 27/04/2023 | first code
+//------------------------------------------------------
+
+
+	//properties-> HIER NOCH NICHTS GEMACHT!
+
+	/* example
+	property p_ones;
+		bus_m.op == 4'h1 |-> bus_m.z == 4'hf;
+	endproperty
+
+	property p_and;
+		bus_m.op == 4'h4 |-> bus_m.z == (bus_m.a & bus_m.b);
+	endproperty
+
+	//assertions
+
+	a_ones : assert property(@(posedge clk) p_ones)
+		$display("%t, property asserted: a_ones", $time());
+	else
+		$display("%t, property failed:   a_ones", $time());
+
+	a_and : assert property(@(posedge clk) p_and)
+		$display("%t, property asserted: a_and",  $time());
+	else
+		$display("%t, property failed:   a_and",  $time());
+	*/

uebung_projekt/hdl_src/sv/fram.sv

@@ -0,0 +1,86 @@
+
+
+
+module spi(bus.spi_port b, fram_if.fram_port_top i);
+
+  parameter ringbuffer_size = 256;
+  
+  logic [19:0] FRAM_Adr;
+  logic [7:0] FRAM_DATA_OUT;
+  logic [7:0] FRAM_DATA_IN;
+  logic FRAM_RW;
+  logic FRAM_RSTATUS;
+  logic FRAM_hbn;
+  logic FRAM_go;
+  logic FRAM_busy;
+  
+  logic [7:0] clk_cntr;
+
+  initial begin    
+    FRAM_Adr <= 20'h0;
+    FRAM_DATA_IN <= 8'h0;
+  	FRAM_RW = 0;
+  	FRAM_RSTATUS = 0;
+  	FRAM_hbn = 0;
+  	FRAM_go = 0;
+    clk_cntr = 0;
+  end
+  
+  always @ (posedge b.timer) begin
+    if(b.dip[0] == 0) begin  //Reset
+      FRAM_Adr <= 20'h0;
+      FRAM_DATA_IN <= 8'h0;
+      FRAM_RW = 0;
+      FRAM_RSTATUS = 0;
+      FRAM_hbn = 0;
+      FRAM_go = 0;
+      clk_cntr = 0;
+    end
+    else if(b.dip[1] == 1) begin //Read
+      FRAM_Adr <= (FRAM_Adr - 1) % (ringbuffer_size - 1);
+      FRAM_RW <= 1'h1; //Read
+      FRAM_go <= 1'h1; //Go
+    end 
+    else if(b.dip[1] == 0) begin //Write
+      FRAM_Adr <= (FRAM_Adr + 1) % (ringbuffer_size - 1);
+      FRAM_DATA_IN <= {6'h0, b.dip[3:2]};
+      FRAM_RW <= 1'h0; //Write Operation
+      FRAM_go <= 1'h1; //Go
+    end      
+  end
+  
+  always @ (posedge b.clk) begin
+    if(FRAM_go == 1) 
+      clk_cntr <= clk_cntr + 1;
+    
+    if(clk_cntr > 250 && FRAM_RW == 1'h1) begin
+      b.spi_read <= FRAM_DATA_OUT[1:0];
+      FRAM_go <= 1'h0;
+      FRAM_RW <= 1'h0; 
+      clk_cntr <= 0;
+    end
+    else if(clk_cntr > 250 && FRAM_RW == 1'h0) begin
+      FRAM_go <= 1'h0;
+      clk_cntr <= 0;
+    end
+  end
+  
+  
+    FRAM FRAM_ut(
+    .i_clk(b.clk),
+    .i_nreset(b.dip[0]),
+    .i_adr(FRAM_Adr),
+    .i_data(FRAM_DATA_IN),
+    .o_data(FRAM_DATA_OUT),
+    .i_rw(FRAM_RW),
+    .i_status(FRAM_RSTATUS),
+    .i_hbn(FRAM_hbn),
+    .i_cready(FRAM_go),
+    .o_busy(FRAM_busy),
+    .o_SPI_Clk(i.sclk),
+    .i_SPI_MISO(i.mosi),
+    .o_SPI_MOSI(i.mosi), 
+    .o_SPI_CS_n(i.ss)
+  );
+  
+endmodule

uebung_projekt/hdl_src/sv/fram.sv.bak

@@ -0,0 +1,86 @@
+
+
+
+module spi(bus.spi_port b, fram_if.fram_port_top i);
+
+  parameter ringbuffer_size = 256;
+  
+  logic [19:0] FRAM_Adr;
+  logic [7:0] FRAM_DATA_OUT;
+  logic [7:0] FRAM_DATA_IN;
+  logic FRAM_RW;
+  logic FRAM_RSTATUS;
+  logic FRAM_hbn;
+  logic FRAM_go;
+  logic FRAM_busy;
+  
+  logic [7:0] clk_cntr;
+
+  initial begin    
+    FRAM_Adr <= 20'h0;
+    FRAM_DATA_IN <= 8'h0;
+  	FRAM_RW = 0;
+  	FRAM_RSTATUS = 0;
+  	FRAM_hbn = 0;
+  	FRAM_go = 0;
+    clk_cntr = 0;
+  end
+  
+  always @ (posedge b.timer) begin
+    if(b.dip[0] == 0) begin  //Reset
+      FRAM_Adr <= 20'h0;
+      FRAM_DATA_IN <= 8'h0;
+      FRAM_RW = 0;
+      FRAM_RSTATUS = 0;
+      FRAM_hbn = 0;
+      FRAM_go = 0;
+      clk_cntr = 0;
+    end
+    else if(b.dip[1] == 1) begin //Read
+      FRAM_Adr <= (FRAM_Adr - 1) % (ringbuffer_size - 1);
+      FRAM_RW <= 1'h1; //Read
+      FRAM_go <= 1'h1; //Go
+    end 
+    else if(b.dip[1] == 0) begin //Write
+      FRAM_Adr <= (FRAM_Adr + 1) % (ringbuffer_size - 1);
+      FRAM_DATA_IN <= {6'h0, b.dip[3:2]};
+      FRAM_RW <= 1'h0; //Write Operation
+      FRAM_go <= 1'h1; //Go
+    end      
+  end
+  
+  always @ (posedge b.clk) begin
+    if(FRAM_go == 1) 
+      clk_cntr <= clk_cntr + 1;
+    
+    if(clk_cntr > 50 && FRAM_RW == 1'h1) begin
+      b.spi_read <= FRAM_DATA_OUT[1:0];
+      FRAM_go <= 1'h0;
+      FRAM_RW <= 1'h0; 
+      clk_cntr <= 0;
+    end
+    else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin
+      FRAM_go <= 1'h0;
+      clk_cntr <= 0;
+    end
+  end
+  
+  
+    FRAM FRAM_ut(
+    .i_clk(b.clk),
+    .i_nreset(b.dip[0]),
+    .i_adr(FRAM_Adr),
+    .i_data(FRAM_DATA_IN),
+    .o_data(FRAM_DATA_OUT),
+    .i_rw(FRAM_RW),
+    .i_status(FRAM_RSTATUS),
+    .i_hbn(FRAM_hbn),
+    .i_cready(FRAM_go),
+    .o_busy(FRAM_busy),
+    .o_SPI_Clk(i.sclk),
+    .i_SPI_MISO(i.mosi),
+    .o_SPI_MOSI(i.mosi), 
+    .o_SPI_CS_n(i.ss)
+  );
+  
+endmodule

uebung_projekt/hdl_src/sv/interface.sv

@@ -0,0 +1,70 @@
+//------------------------------------------------------
+//                                                        
+//  File          :  interface.sv
+//  Related Files :                                                     
+//  Author(s)     :  Mueller                              
+//  Email         :  muelleral82290@th-nuernberg.de       
+//  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
+//  Notes         :  Stimuli Modul 
+//
+//------------------------------------------------------
+//                   History    
+//------------------------------------------------------
+//    Version| Author   | Mod. Date  | Changes Made:
+//    v1.00  | Mueller  | 11/05/2023 | first code
+//------------------------------------------------------
+//eoh
+
+
+//interface for LED
+//reg [2:0]rbg stores rgb values that depend on dip[3:2]
+interface led_if();
+
+	logic [2:0]rgb;
+	logic [2:0]rgbn;
+
+	modport led_port_stim(input rgb, rgbn);
+	modport led_port_top(output rgb, rgbn);
+	
+
+endinterface : led_if
+
+//interface for DIPSCHALER
+// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
+interface dip_if();
+
+	logic [3:0]dip;
+
+	modport dip_port_stim(output dip);
+	modport dip_port_top(input dip);
+
+endinterface : dip_if
+
+//interface for FRAM
+// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
+// clk -> system clock / timer
+// miso -> testbench output
+// mosi -> testbench input
+interface fram_if();
+
+	logic ss;
+	logic mosi;
+	logic miso;
+	logic sclk;
+
+	modport fram_port_stim(input mosi, sclk, ss, output miso);
+	modport fram_port_top(output mosi, sclk, ss, input miso);
+
+endinterface : fram_if
+
+//testbenchclock replaces the oscillator on the board
+interface clock_if();
+
+	logic clk;
+
+	modport clock_port_stim(output clk);
+	modport clock_port_top(input clk);
+
+endinterface : clock_if
+
+

uebung_projekt/hdl_src/sv/stimuli.sv

@@ -0,0 +1,92 @@
+//------------------------------------------------------
+//                                                        
+//  File          :  stimuli.sv
+//  Related Files :                                                     
+//  Author(s)     :  Mueller                              
+//  Email         :  muelleral82290@th-nuernberg.de       
+//  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
+//  Notes         :  Stimuli Modul 
+//
+//------------------------------------------------------
+//                   History    
+//------------------------------------------------------
+//    Version| Author   | Mod. Date  | Changes Made:
+//    v1.00  | Mueller  | 11/05/2023 | first code
+//------------------------------------------------------
+
+//interface for LED
+//reg [2:0]rbg stores rgb values that depend on dip[3:2]
+
+//interface for DIPSCHALER
+// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
+
+//interface for FRAM
+// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
+// clk -> system clock / timer
+// miso -> testbench output
+// mosi -> testbench input
+
+//testbenchclock replaces the oscillator on the board
+
+// 27.04.23 -> #delay/#oszillatordelay is not set jet
+// 09.06.23 -> removed fram_if.fram_port_stim fram_spi from the stimuli parameters, moved to "fram_module"
+// 09.06.23 -> oszillatordelay = 1, delay = 5
+
+`timescale 10ns/10ps
+
+module stimuli(led_if.led_port_stim led_stim, dip_if.dip_port_stim dip_stim, clock_if.clock_port_stim clk_stim);
+
+	// generate oszillator signal for the timer block (clock_if)
+	reg oszillator;
+	
+	initial oszillator = 0;
+
+	always
+	begin
+		#1 oszillator <= ! oszillator;
+		clk_stim.clk <= ! oszillator;
+	end
+	
+
+	initial
+	begin
+
+  /*~~~~toplevel is set to off~~~~~~~~*/
+  /*~~~~dip[0] is set to 0~~~~~~~~~~~~*/
+			dip_stim.dip = 4'b0000;	
+		#500		dip_stim.dip = 4'b0010;
+		#500		dip_stim.dip = 4'b0100;
+		#500		dip_stim.dip = 4'b0110;
+		#500		dip_stim.dip = 4'b1000;
+		#500		dip_stim.dip = 4'b1010;
+		#500		dip_stim.dip = 4'b1100;
+		#500		dip_stim.dip = 4'b1110;
+  /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
+
+  /*~~~~toplevel is set to on~~~~~~~~~*/
+  /*~~~~dip[0] is set to 1~~~~~~~~~~~~*/
+
+	/*~~fram is set to write~~~~~~~~*/
+    /*~~~~dip[1] is set to 0~~~~~~~~*/
+		#800		dip_stim.dip = 4'b0001;
+		#2000	dip_stim.dip = 4'b0101;
+		#2000	dip_stim.dip = 4'b1001;
+		#2000	dip_stim.dip = 4'b1101;
+	/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
+
+	/*~~fram is set to read~~~~~~~~~*/
+	/*~~~~dip[1] is set to 1~~~~~~~~*/
+		#2000	dip_stim.dip = 4'b0011;
+		#2000	dip_stim.dip = 4'b0111;
+		#2000	dip_stim.dip = 4'b1011;
+		#2000	dip_stim.dip = 4'b1111;
+	/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
+
+  /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
+
+	end
+
+endmodule : stimuli
+
+
+

uebung_projekt/hdl_src/sv/timer.sv

@@ -0,0 +1,46 @@
+//------------------------------------------------------
+//                                                        
+//  File          :  Timer.sv
+//  Related Files :                                                     
+//  Author(s)     :                                
+//  Email         :      
+//  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
+//  Notes         :   
+//
+//------------------------------------------------------
+//                   History    
+//------------------------------------------------------
+//    Version| Author   | Mod. Date  | Changes Made:
+//    v1.00  |  		| 11.05.2023 | 
+//------------------------------------------------------
+//eoh
+
+
+module timer(bus.timer_port fpga_bus, clock_if.clock_port_top c); // (bus.timer b, clock_if.clock_port_top i)
+
+  integer counter = 0;	// internal count reg
+  integer reload_val;
+
+     
+  always @ (posedge c.clk or fpga_bus.dip[0]) begin	
+    if (!fpga_bus.dip[0]) begin
+      counter <= 0;
+	  fpga_bus.timer <= 0; 
+    end else begin
+  	  if(counter <= 800) begin  // zu testzwecken kürzer 1000000
+		counter++;
+		fpga_bus.timer <= 0;
+	  end else begin
+		counter <= 0;
+		fpga_bus.timer <= 1;
+      end
+	end
+
+  end
+
+  //give the input clock on the bus
+  always@(posedge c.clk or negedge c.clk)
+  	fpga_bus.clk = c.clk;
+
+endmodule : timer
+

uebung_projekt/hdl_src/sv/top_level.sv

@@ -0,0 +1,99 @@
+// Definition of top level
+module top(led_if.led_port_top l, dip_if.dip_port_top d, fram_if.fram_port_top f, clock_if.clock_port_top c);
+	
+	// Initialisation of bus
+	bus fpga_bus();
+		
+	// Initialisation of modules
+	timer t(fpga_bus, c);
+	steuerung st(fpga_bus, l); 
+	spi s(fpga_bus, f);
+	parallelport p(fpga_bus, d);
+endmodule : top
+
+// Definition of bus interface
+interface bus();
+	// bus wires
+	logic clk; // clock
+	logic timer;
+	logic [3:0]dip;
+	logic [1:0]spi_read;
+	
+	// modports from modules pov
+	modport timer_port(input dip, output timer, clk);			//dip[0]
+	modport parallel_port(output dip);							//dip[3:0]
+	modport steuerung_port(input dip, timer, spi_read, clk);	//dip[3:0] / spi_read[1:0]
+	modport spi_port(input dip, clk, timer, output spi_read);	//spi_read[1:0]
+endinterface : bus
+
+// Definition of parallelport
+module parallelport(bus.parallel_port b, dip_if.dip_port_top d);
+	
+	//always at change of the input dip, put the change on the bus
+	always@(d.dip[0] or d.dip[1] or d.dip[2] or d.dip[3])
+	b.dip = d.dip;	
+	
+endmodule
+
+module steuerung(bus.steuerung_port b, led_if.led_port_top i);
+	/*...
+	b.dip[3:0], b.timer, b.spi_read[1:0]
+	i.rgb[2:0]
+	...*/
+endmodule
+
+/*   
+_______________________________________________________________________________________________________________
+Testbench
+					__________________										 		___________________
+				   |				  |												|				    |
+				   |   DIP-Schalter	  |												|	FRAM-Speicher   |
+				   |				  |												|				    |
+				   |__________________|												|___________________|
+							|																 |
+____________________________|________________________________________________________________|_________________
+Toplevel					|																 |
+							|																 |
+				 dip[3:0]-->|																 |<--mosi, miso, sclk, ss
+							|												  				 |
+					________|_________											     ________|__________
+				   |				  |												|				    |
+				   |   Parallelport	  |												| SPI-Schnittstelle |
+				   |				  |												| & FRAM-Kontroller	|
+				   |__________________|												|___________________|
+							|																 |
+							|																 |
+				 dip[3:0]-->|																 |<--dip[3:0], timer, spi_read[1:0]
+							|																 |
+							|																 |
+							---------------------------------------------------------------------BUS
+							|																 |
+							|																 |
+       dip[0], clk, timer-->|																 |<--dip[3:0], timer, spi_read[1:0]
+							|																 |
+					________|_________			___________________			     	 ________|__________
+				   |				  |		   |				   |				|				    |
+				   |      Timer		  |		   |  Oszillator-Takt  |				|  Ampel-Steuerung  |
+				   |				  |		   |    (auf Board)	   |				|				    |
+				   |__________________|		   |___________________|				|___________________|
+							|	                         |                                   |
+							|							 |									 |
+				 	  clk-->------------------------------									 |<--rgb[2:0]
+							|																 |
+____________________________|________________________________________________________________|___________________
+							|																 |
+				 	________|_________										 		 ________|__________
+				   |				  |												|				    |
+				   |       Takt		  |												|	   RGB-LED		|
+				   |  (der Testbench) |												|				    |
+				   |__________________|												|___________________|
+
+
+__________________________________________________________________________________________________________________
+
+*/
+
+
+
+
+

uebung_projekt/hdl_src/sv/top_tb.sv

@@ -0,0 +1,52 @@
+//------------------------------------------------------
+//                                                        
+//  File          :  top.sv
+//  Related Files :                                                     
+//  Author(s)     :  Mueller                              
+//  Email         :  muelleral82290@th-nuernberg.de       
+//  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
+//  Notes         :  Stimuli Modul 
+//
+//------------------------------------------------------
+//                   History    
+//------------------------------------------------------
+//    Version| Author   | Mod. Date  | Changes Made:
+//    v1.00  | Mueller  | 27/04/2023 | first code
+//------------------------------------------------------
+//eoh
+
+//interface for LED
+//reg [2:0]rbg stores rgb values that depend on dip[3:2]
+
+//interface for DIPSCHALER
+// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
+
+//interface for FRAM
+// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
+// clk -> system clock / timer
+// miso -> testbench output
+// mosi -> testbench input
+
+//testbenchclock replaces the oscillator on the board
+
+`timescale 10us/10ns
+
+module top_tb();
+
+	//  Interface
+	led_if   stim_led_if();
+	dip_if	 stim_dip_if();
+	fram_if  stim_fram_if();	
+	clock_if stim_clock_if();			
+		
+	// Instanziierungen
+	top     t1(stim_led_if, stim_dip_if, stim_fram_if, stim_clock_if);
+	stimuli s1(stim_led_if, stim_dip_if, stim_clock_if);
+	//fram_module f1(stim_fram_if);
+
+	// assertions
+	//`include "./hdl_src/sv/led_assert.txt"
+
+endmodule : top_tb
+
+

uebung_projekt/simulationsscripts/simulation.tcl

@@ -0,0 +1,30 @@
+##------------------------------------------------------
+##                                                        
+##  File          :  simulation.tcl
+##  Related Files :                                                     
+##  Author(s)     :  Mueller                              
+##  Email         :  muelleral82290@th-nuernberg.de    
+##  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
+##  Notes         :  Counter Modul 
+##
+##------------------------------------------------------
+##                   History    
+##------------------------------------------------------
+##    Version| Author   | Mod. Date  | Changes Made:
+##    v1.00  | Mueller  | 27/04/2023 | first code
+##------------------------------------------------------
+
+quit -sim
+
+# Aufruf der Simulation
+# vsim -novopt -coverage -cvg63 -voptargs=+acc work.ShiftRegister_tb --Original
+# vsim -cvg63 -voptargs=+acc work.top
+vsim -cvg63 -voptargs="+acc" top_tb 
+
+do ./simulationsscripts/wave.do
+
+# Objects im Trace-Window
+# add wave sim:/top/*
+
+# Starten des Simulators
+ run 210000 ns

uebung_projekt/simulationsscripts/wave.do

@@ -0,0 +1,32 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -radix binary /top_tb/stim_dip_if/dip
+add wave -noupdate -radix binary /top_tb/t1/fpga_bus/dip
+add wave -noupdate -radix binary /top_tb/stim_clock_if/clk
+add wave -noupdate -radix binary /top_tb/t1/fpga_bus/clk
+add wave -noupdate -radix binary /top_tb/t1/fpga_bus/timer
+add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_Adr
+add wave -noupdate -radix binary /top_tb/t1/s/clk_cntr
+add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_DATA_IN
+add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_DATA_OUT
+add wave -noupdate -radix binary /top_tb/t1/f/mosi
+add wave -noupdate -radix binary /top_tb/t1/f/sclk
+add wave -noupdate -radix binary /top_tb/t1/fpga_bus/spi_read
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ns} 0}
+quietly wave cursor active 0
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {50 ns} {1050 ns}

uebung_projekt/transcript

@@ -0,0 +1,379 @@
+# //  Questa Sim-64
+# //  Version 2019.4 linux_x86_64 Oct 15 2019
+# //
+# //  Copyright 1991-2019 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
+# 
+# create workspace
+# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
+# ** Warning: (vlib-34) Library already exists at "work".
+# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
+# vmap work ./work 
+# Modifying modelsim.ini
+# 
+#  Compile sv-Designfiles 
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:45:50 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv 
+# -- Compiling interface led_if
+# -- Compiling interface dip_if
+# -- Compiling interface fram_if
+# -- Compiling interface clock_if
+# 
+# Top level modules:
+# 	--none--
+# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:45:50 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv 
+# -- Compiling module stimuli
+# 
+# Top level modules:
+# 	stimuli
+# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:45:50 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv 
+# -- Compiling module top
+# -- Compiling interface bus
+# -- Compiling module parallelport
+# -- Compiling module steuerung
+# 
+# Top level modules:
+# 	top
+# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:45:50 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv 
+# -- Compiling module top_tb
+# 
+# Top level modules:
+# 	top_tb
+# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:45:51 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv 
+# -- Compiling module timer
+# 
+# Top level modules:
+# 	timer
+# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:45:51 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv 
+# -- Compiling module SPI_Master
+# 
+# Top level modules:
+# 	SPI_Master
+# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:45:51 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv 
+# -- Compiling module SPI_Master_With_Single_CS
+# 
+# Top level modules:
+# 	SPI_Master_With_Single_CS
+# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:45:51 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv 
+# -- Compiling module FRAM
+# 
+# Top level modules:
+# 	FRAM
+# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:45:51 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv 
+# -- Compiling module spi
+# 
+# Top level modules:
+# 	spi
+# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# 
+#  Run Simulation 
+# vsim -cvg63 -voptargs=""+acc"" top_tb 
+# Start time: 14:45:51 on Jun 15,2023
+# ** Note: (vsim-3812) Design is being optimized...
+# ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)".
+# Loading sv_std.std
+# Loading work.top_tb(fast)
+# Loading work.led_if(fast)
+# Loading work.dip_if(fast)
+# Loading work.fram_if(fast)
+# Loading work.clock_if(fast)
+# Loading work.top(fast)
+# Loading work.bus(fast)
+# Loading work.timer(fast)
+# Loading work.steuerung(fast)
+# Loading work.spi(fast)
+# Loading work.FRAM(fast)
+# Loading work.SPI_Master_With_Single_CS(fast)
+# Loading work.SPI_Master(fast)
+# Loading work.parallelport(fast)
+# Loading work.stimuli(fast)
+do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
+# 
+# create workspace
+# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
+# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
+# ** Warning: (vlib-34) Library already exists at "work".
+# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
+# vmap work ./work 
+# Modifying modelsim.ini
+# 
+#  Compile sv-Designfiles 
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:48:17 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv 
+# -- Compiling interface led_if
+# -- Compiling interface dip_if
+# -- Compiling interface fram_if
+# -- Compiling interface clock_if
+# 
+# Top level modules:
+# 	--none--
+# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:48:17 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv 
+# -- Compiling module stimuli
+# 
+# Top level modules:
+# 	stimuli
+# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:48:17 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv 
+# -- Compiling module top
+# -- Compiling interface bus
+# -- Compiling module parallelport
+# -- Compiling module steuerung
+# 
+# Top level modules:
+# 	top
+# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:48:17 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv 
+# -- Compiling module top_tb
+# 
+# Top level modules:
+# 	top_tb
+# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:48:17 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv 
+# -- Compiling module timer
+# 
+# Top level modules:
+# 	timer
+# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:48:17 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv 
+# -- Compiling module SPI_Master
+# 
+# Top level modules:
+# 	SPI_Master
+# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:48:17 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv 
+# -- Compiling module SPI_Master_With_Single_CS
+# 
+# Top level modules:
+# 	SPI_Master_With_Single_CS
+# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:48:17 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv 
+# -- Compiling module FRAM
+# 
+# Top level modules:
+# 	FRAM
+# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:48:17 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv 
+# -- Compiling module spi
+# 
+# Top level modules:
+# 	spi
+# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# 
+#  Run Simulation 
+# End time: 14:48:18 on Jun 15,2023, Elapsed time: 0:02:27
+# Errors: 3, Warnings: 2
+# vsim -cvg63 -voptargs=""+acc"" top_tb 
+# Start time: 14:48:18 on Jun 15,2023
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# Loading sv_std.std
+# Loading work.top_tb(fast)
+# Loading work.led_if(fast)
+# Loading work.dip_if(fast)
+# Loading work.fram_if(fast)
+# Loading work.clock_if(fast)
+# Loading work.top(fast)
+# Loading work.bus(fast)
+# Loading work.timer(fast)
+# Loading work.steuerung(fast)
+# Loading work.spi(fast)
+# Loading work.FRAM(fast)
+# Loading work.SPI_Master_With_Single_CS(fast)
+# Loading work.SPI_Master(fast)
+# Loading work.parallelport(fast)
+# Loading work.stimuli(fast)
+add wave -position insertpoint  \
+sim:/top_tb/t1/fpga_bus/spi_read
+do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
+# 
+# create workspace
+# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
+# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
+# ** Warning: (vlib-34) Library already exists at "work".
+# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
+# vmap work ./work 
+# Modifying modelsim.ini
+# 
+#  Compile sv-Designfiles 
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:51:02 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv 
+# -- Compiling interface led_if
+# -- Compiling interface dip_if
+# -- Compiling interface fram_if
+# -- Compiling interface clock_if
+# 
+# Top level modules:
+# 	--none--
+# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:51:02 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv 
+# -- Compiling module stimuli
+# 
+# Top level modules:
+# 	stimuli
+# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:51:02 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv 
+# -- Compiling module top
+# -- Compiling interface bus
+# -- Compiling module parallelport
+# -- Compiling module steuerung
+# 
+# Top level modules:
+# 	top
+# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:51:02 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv 
+# -- Compiling module top_tb
+# 
+# Top level modules:
+# 	top_tb
+# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:51:02 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv 
+# -- Compiling module timer
+# 
+# Top level modules:
+# 	timer
+# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:51:02 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv 
+# -- Compiling module SPI_Master
+# 
+# Top level modules:
+# 	SPI_Master
+# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:51:02 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv 
+# -- Compiling module SPI_Master_With_Single_CS
+# 
+# Top level modules:
+# 	SPI_Master_With_Single_CS
+# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:51:02 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv 
+# -- Compiling module FRAM
+# 
+# Top level modules:
+# 	FRAM
+# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:51:02 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv 
+# -- Compiling module spi
+# 
+# Top level modules:
+# 	spi
+# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# 
+#  Run Simulation 
+# End time: 14:51:07 on Jun 15,2023, Elapsed time: 0:02:49
+# Errors: 1, Warnings: 2
+# vsim -cvg63 -voptargs=""+acc"" top_tb 
+# Start time: 14:51:07 on Jun 15,2023
+# ** Note: (vsim-8009) Loading existing optimized design _opt1
+# Loading sv_std.std
+# Loading work.top_tb(fast)
+# Loading work.led_if(fast)
+# Loading work.dip_if(fast)
+# Loading work.fram_if(fast)
+# Loading work.clock_if(fast)
+# Loading work.top(fast)
+# Loading work.bus(fast)
+# Loading work.timer(fast)
+# Loading work.steuerung(fast)
+# Loading work.spi(fast)
+# Loading work.FRAM(fast)
+# Loading work.SPI_Master_With_Single_CS(fast)
+# Loading work.SPI_Master(fast)
+# Loading work.parallelport(fast)
+# Loading work.stimuli(fast)
+# End time: 14:52:23 on Jun 15,2023, Elapsed time: 0:01:16
+# Errors: 3, Warnings: 0

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