Kommentare ergänzt

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc

@@ -1,4 +1,4 @@
 version:1
 57656254616c6b5472616e736d697373696f6e417474656d70746564:13
-6d6f64655f636f756e7465727c4755494d6f6465:28
+6d6f64655f636f756e7465727c4755494d6f6465:30
 eof:

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat

@@ -6,7 +6,7 @@ REM Filename    : compile.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for compiling the simulation design source files
 REM
-REM Generated by Vivado on Wed May 18 21:31:28 +0200 2022
+REM Generated by Vivado on Mon May 23 13:37:07 +0200 2022
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat

@@ -6,7 +6,7 @@ REM Filename    : elaborate.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for elaborating the compiled design
 REM
-REM Generated by Vivado on Wed May 18 21:31:29 +0200 2022
+REM Generated by Vivado on Mon May 23 13:37:09 +0200 2022
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.bat

@@ -6,7 +6,7 @@ REM Filename    : simulate.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for simulating the design by launching the simulator
 REM
-REM Generated by Vivado on Wed May 18 21:31:32 +0200 2022
+REM Generated by Vivado on Mon May 23 13:37:11 +0200 2022
 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 REM
 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log

@@ -0,0 +1 @@
+Time resolution is 1 ps

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx

@@ -1,6 +1,6 @@
 
 { 
-    crc :  7823678164688294818  , 
+    crc :  17288891363008981436  , 
     ccp_crc :  0  , 
     cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , 
     buildDate : "Oct 19 2021" , 

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log

@@ -1,4 +1,7 @@
-Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 55344
+Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 51806
 Design successfully loaded
-Design Loading Memory Usage: 7292 KB (Peak: 7292 KB)
-Design Loading CPU Usage: 15 ms
+Design Loading Memory Usage: 7288 KB (Peak: 7288 KB)
+Design Loading CPU Usage: 0 ms
+Simulation completed
+Simulation Memory Usage: 15780 KB (Peak: 15780 KB)
+Simulation CPU Usage: 1953 ms

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

@@ -2,6 +2,6 @@
 2020.2
 Oct 19 2021
 03:16:22
-C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652902272,vhdl,,,,pwm_test_db,,,,,,,,
+C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1653305822,vhdl,,,,pwm_test_db,,,,,,,,
 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1652901752,vhdl,,,,pt1,,,,,,,,
 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1652901648,vhdl,,,,regler,,,,,,,,

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd

@@ -116,7 +116,8 @@ clk <= not clk after 5 us;
 
 process 
 begin
-    w <= 100000000;
+    --w <= 100000000;
+    w <= 1000000; --muss >= 1000000 sein!
     
 --    if rising_edge(clk) and ( cnt >= 100) then
 --        clk_100 <= not clk_100;

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr

@@ -56,7 +56,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="zybo-z7-10"/>
-    <Option Name="WTXSimLaunchSim" Val="145"/>
+    <Option Name="WTXSimLaunchSim" Val="148"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -249,9 +249,7 @@
   <Runs Version="1" Minor="15">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
         <Step Id="synth_design"/>
       </Strategy>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
@@ -260,9 +258,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou

@@ -2,10 +2,10 @@
 # Vivado v2021.2 (64-bit)
 # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Wed May 18 19:29:49 2022
-# Process ID: 18960
+# Start of session at: Mon May 23 20:31:11 2022
+# Process ID: 10504
 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3712 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent7676 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
 # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
 # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
 # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
@@ -13,140 +13,3 @@
 start_gui
 open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
 update_compile_order -fileset sources_1
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-set_property -name {xsim.simulate.runtime} -value {10 s} -objects [get_filesets sim_1]
-save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-launch_runs synth_1 -jobs 6
-wait_on_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-reset_run synth_1
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl
-close_sim
-launch_simulation
-open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
-source pwm_test_db.tcl

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_18960.backup.jou

@@ -0,0 +1,153 @@
+#-----------------------------------------------------------
+# Vivado v2021.2 (64-bit)
+# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
+# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
+# Start of session at: Wed May 18 19:29:49 2022
+# Process ID: 18960
+# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3712 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
+# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
+# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
+# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
+#-----------------------------------------------------------
+start_gui
+open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
+update_compile_order -fileset sources_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+set_property -name {xsim.simulate.runtime} -value {10 s} -objects [get_filesets sim_1]
+save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+reset_run synth_1
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim
+launch_simulation
+open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
+source pwm_test_db.tcl
+close_sim

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3672.backup.jou

@@ -1,17 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2021.2 (64-bit)
-# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
-# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Fri May 13 11:28:18 2022
-# Process ID: 3672
-# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11452 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
-# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
-# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
-# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
-#-----------------------------------------------------------
-start_gui
-open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
-update_compile_order -fileset sources_1
-launch_runs impl_1 -jobs 6
-ns synth_1 -jobs 6

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3672.backup.log

@@ -1,84 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2021.2 (64-bit)
-# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
-# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
-# Start of session at: Fri May 13 11:28:18 2022
-# Process ID: 3672
-# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11452 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
-# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
-# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
-# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
-#-----------------------------------------------------------
-start_gui
-open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
-INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
-Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
-WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
-INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save.
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save.
-INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
-INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
-WARNING: [Project 1-312] File not found as 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp'; using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp' instead.
-Scanning sources...
-Finished scanning sources
-WARNING: [Project 1-312] File not found as 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp'; using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp' instead.
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
-open_project: Time (s): cpu = 00:00:42 ; elapsed = 00:00:21 . Memory (MB): peak = 1576.332 ; gain = 0.000
-update_compile_order -fileset sources_1
-WARNING: [Common 17-9] Error reading message records.
-WARNING: [Common 17-9] Error reading message records.
-WARNING: [Common 17-9] Error reading message records.
-launch_runs impl_1 -jobs 6
-[Fri May 13 11:32:24 2022] Launched impl_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log
-Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
-
-launch_runs synth_1 -jobs 6
-[Fri May 13 11:29:15 2022] Launched synth_1...
-Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid18360.str → StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid10504.str

@@ -4,11 +4,11 @@ Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]
 SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021
 IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021
 
-Process ID (PID): 18360
+Process ID (PID): 10504
 License: Customer
 Mode: GUI Mode
 
-Current time: 	Fri May 13 11:28:40 CEST 2022
+Current time: 	Mon May 23 20:31:24 CEST 2022
 Time zone: 	Central European Standard Time (Europe/Berlin)
 
 OS: Windows 10
@@ -48,7 +48,7 @@ Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/da
 PlanAhead jar file: 	C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar
 Vivado log file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
 Vivado journal file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
-Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-18360-DESKTOP-PAACOM8
+Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-10504-DESKTOP-PAACOM8
 
 Xilinx Environment Variables
 ----------------------------
@@ -61,16 +61,15 @@ XILINX_VIVADO: C:/Xilinx/Vivado/2021.2
 XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2
 
 
-GUI allocated memory:	256 MB
+GUI allocated memory:	319 MB
 GUI max memory:		3,072 MB
-Engine allocated memory: 1,262 MB
+Engine allocated memory: 1,307 MB
 
 Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 
 */
 
 // TclEventType: START_GUI
-// WARNING: HEventQueue.dispatchEvent() is taking  1129 ms.
 // Tcl Message: start_gui 
 // TclEventType: PROJECT_OPEN_DIALOG
 // Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 
@@ -78,12 +77,10 @@ Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 // TclEventType: FLOW_ADDED
 // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
 // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
-// HMemoryUtils.trashcanNow. Engine heap size: 1,262 MB. GUI used memory: 55 MB. Current time: 5/13/22, 11:28:41 AM CEST
+// HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 55 MB. Current time: 5/23/22, 8:31:25 PM CEST
 // TclEventType: MSGMGR_MOVEMSG
 // TclEventType: FILE_SET_CHANGE
 // TclEventType: FILE_SET_NEW
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
 // TclEventType: RUN_CURRENT
 // TclEventType: PROJECT_DASHBOARD_NEW
 // TclEventType: PROJECT_DASHBOARD_GADGET_NEW
@@ -99,43 +96,17 @@ Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 // TclEventType: PROJECT_DASHBOARD_GADGET_NEW
 // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
 // TclEventType: PROJECT_NEW
+// [GUI Memory]: 70 MB (+71283kb) [00:00:14]
+// [Engine Memory]: 1,307 MB (+1219381kb) [00:00:14]
+// [GUI Memory]: 109 MB (+37180kb) [00:00:15]
+// WARNING: HEventQueue.dispatchEvent() is taking  2465 ms.
 // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
 // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
+// Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. 
 // Tcl Message: Scanning sources... Finished scanning sources 
-// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified 
-// TclEventType: PROJECT_NEW
-// [GUI Memory]: 78 MB (+79097kb) [00:00:27]
-// [Engine Memory]: 1,262 MB (+1171794kb) [00:00:27]
-// WARNING: HEventQueue.dispatchEvent() is taking  5264 ms.
-// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 
-// [GUI Memory]: 105 MB (+24789kb) [00:00:32]
-// Tcl Message: open_project: Time (s): cpu = 00:00:37 ; elapsed = 00:00:17 . Memory (MB): peak = 1250.551 ; gain = 0.000 
+// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 
+// [GUI Memory]: 117 MB (+2679kb) [00:00:16]
 // Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1
+// Tcl Message: open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 1582.152 ; gain = 0.000 
 dismissDialog("Open Project"); // bA
 // Tcl Message: update_compile_order -fileset sources_1 
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: RUN_STATUS_CHANGE
-// [GUI Memory]: 111 MB (+540kb) [00:01:34]
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 205 seconds
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// Tcl Message: launch_runs impl_1 -jobs 6 
-// Tcl Message: [Fri May 13 11:32:24 2022] Launched impl_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log 
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// HMemoryUtils.trashcanNow. Engine heap size: 1,262 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:32:53 AM CEST
-// TclEventType: RUN_FAILED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// Elapsed time: 58 seconds
-selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a
-// 'c' command handler elapsed time: 59 seconds
-// HMemoryUtils.trashcanNow. Engine heap size: 1,262 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:33:24 AM CEST

StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid3672.str

@@ -1,151 +0,0 @@
-/*
-
-Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]
-SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021
-IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021
-
-Process ID (PID): 3672
-License: Customer
-Mode: GUI Mode
-
-Current time: 	Fri May 13 11:28:40 CEST 2022
-Time zone: 	Central European Standard Time (Europe/Berlin)
-
-OS: Windows 10
-OS Version: 10.0
-OS Architecture: amd64
-Available processors (cores): 12
-
-Screen size: 1920x1080
-Screen resolution (DPI): 100
-Available screens: 2
-Default font: family=Dialog,name=Dialog,style=plain,size=12
-Scale size: 12
-
-Java version: 	11.0.11 64-bit
-Java home: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9
-Java executable: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe
-Java arguments: 	[-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]
-Java initial memory (-Xms): 	256 MB
-Java maximum memory (-Xmx):	 3 GB
-
-
-User name: 	Felix
-User home directory: C:/Users/Felix
-User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
-User country: 	DE
-User language: 	de
-User locale: 	de_DE
-
-RDI_BASEROOT: C:/Xilinx/Vivado
-HDI_APPROOT: C:/Xilinx/Vivado/2021.2
-RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data
-RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin
-
-Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml
-Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/
-Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts
-PlanAhead jar file: 	C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar
-Vivado log file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
-Vivado journal file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
-Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-3672-DESKTOP-PAACOM8
-
-Xilinx Environment Variables
-----------------------------
-TWINCATSDK: C:\TwinCAT\3.1\SDK\
-XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
-XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
-XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2
-XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2
-XILINX_VIVADO: C:/Xilinx/Vivado/2021.2
-XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2
-
-
-GUI allocated memory:	256 MB
-GUI max memory:		3,072 MB
-Engine allocated memory: 1,300 MB
-
-Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-
-*/
-
-// TclEventType: START_GUI
-// Tcl Message: start_gui 
-// TclEventType: PROJECT_OPEN_DIALOG
-// Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 
-// TclEventType: DEBUG_PROBE_SET_CHANGE
-// TclEventType: FLOW_ADDED
-// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
-// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 57 MB. Current time: 5/13/22, 11:28:41 AM CEST
-// TclEventType: MSGMGR_MOVEMSG
-// TclEventType: FILE_SET_CHANGE
-// TclEventType: FILE_SET_NEW
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_CURRENT
-// TclEventType: PROJECT_DASHBOARD_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_NEW
-// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 
-// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 
-// Tcl Message: INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save. 
-// Tcl Message: INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. 
-// Tcl Message: Scanning sources... Finished scanning sources 
-// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified 
-// TclEventType: PROJECT_NEW
-// [GUI Memory]: 79 MB (+80353kb) [00:00:27]
-// [Engine Memory]: 1,300 MB (+1211828kb) [00:00:27]
-// WARNING: HEventQueue.dispatchEvent() is taking  7148 ms.
-// WARNING: HEventQueue.dispatchEvent() is taking  1355 ms.
-// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 
-// [GUI Memory]: 107 MB (+24993kb) [00:00:34]
-// Tcl Message: open_project: Time (s): cpu = 00:00:42 ; elapsed = 00:00:21 . Memory (MB): peak = 1576.332 ; gain = 0.000 
-// Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1
-dismissDialog("Open Project"); // bA
-// Tcl Message: update_compile_order -fileset sources_1 
-// Elapsed time: 10 seconds
-selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
-// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
-selectButton("OptionPane.button", "OK"); // JButton
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_RESET
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_RESET
-// TclEventType: RUN_MODIFY
-// Tcl Message: reset_run synth_1 
-// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 
-// TclEventType: FILE_SET_CHANGE
-selectButton(RDIResource.BaseDialog_OK, "OK"); // a
-dismissDialog("Launch Runs"); // f
-// TclEventType: RUN_LAUNCH
-// TclEventType: RUN_MODIFY
-// TclEventType: RUN_STATUS_CHANGE
-// Tcl Message: launch_runs synth_1 -jobs 6 
-// Tcl Message: [Fri May 13 11:29:15 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 
-// TclEventType: RUN_STATUS_CHANGE
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:29:44 AM CEST
-// TclEventType: RUN_COMPLETED
-// TclEventType: RUN_STATUS_CHANGE
-// TclEventType: RUN_STEP_COMPLETED
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:30:15 AM CEST
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:30:45 AM CEST
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:32:14 AM CEST
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:32:45 AM CEST
-// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:33:15 AM CEST
-// Elapsed time: 245 seconds
-selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a
-// 'k' command handler elapsed time: 249 seconds
-closeMainWindow("Coraz7_Test - [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr] - Vivado 2021.2"); // bb
-// HOptionPane Warning: 'A background task is running. Please wait until it completes to exit Vivado. If you choose to abort background task and exit immediately, you will lose all unsaved changes to project. (Background Task)'