I hate git

Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
Added parallelport, timer and ampelsteuerung
2022-06-14 12:33:29 +02:00 · 2022-06-14 12:32:53 +02:00 · 2022-06-14 12:26:26 +02:00 · 2022-06-14 12:25:53 +02:00 · 2022-06-14 12:25:25 +02:00 · 2022-06-14 12:25:19 +02:00
10 changed files with 983 additions and 946 deletions
@@ -14,7 +14,6 @@ module Top(
    // Bus (Interface)
    Bus_if bus(.clk(clk));
    // SPI Interface
-    
    // FSM
    Fsm fsm(
        .clk(clk),
@@ -54,6 +53,5 @@ module Top(
        .alarm(bus.AlarmAmpel)
    );

-    assign AlarmAmpel = bus.AlarmAmpel;
-    
+    assign AlarmAmpel = bus.AlarmAmpel;  
 endmodule
Author	SHA1	Message	Date
sessleral71711	17f361ea12	I hate git	2022-06-14 12:33:29 +02:00
sessleral71711	730cc895b1	Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design	2022-06-14 12:32:53 +02:00
sessleral71711	019dc2868e	Added parallelport, timer and ampelsteuerung	2022-06-14 12:26:26 +02:00
sessleral71711	b30efd039d	Added bus_if and fsm to top level design	2022-06-14 12:25:53 +02:00
sessleral71711	ecd6f16dbe	merge konflikt behoben	2022-06-14 12:25:25 +02:00
sessleral71711	6a72019f25	Initalized top level design	2022-06-14 12:25:19 +02:00
sessleral71711	53868c67fd	Added Bus_if and fsm to top level design	2022-06-14 12:22:52 +02:00
sessleral71711	6ab278694e	Initalized top level design	2022-06-14 12:22:52 +02:00
badenbergra78621	9ffb72cf97	Screenshots from RADIANT --> how to create SPI module with radiant	2022-06-14 09:59:23 +00:00
badenbergra78621	72c964475f	Screenshots from RADIANT --> how to create SPI module with radiant	2022-06-14 09:58:24 +00:00
sessleral71711	d2aa8277c7	spi_interface dateien	2022-06-14 11:56:42 +02:00
badenbergra78621	c46a1c3b33	add "spi_interface_portsI()" (beginning of document)	2022-06-14 09:42:25 +00:00