I hate git

Top/Top.sv

@@ -14,7 +14,6 @@ module Top(
     // Bus (Interface)
     Bus_if bus(.clk(clk));
     // SPI Interface
-    
     // FSM
     Fsm fsm(
         .clk(clk),
@@ -55,5 +54,4 @@ module Top(
     );
 
     assign AlarmAmpel = bus.AlarmAmpel;  
-    
 endmodule

spi_interface_radiant/spi_interface.v

@@ -5,6 +5,45 @@
     Soft IP Version: 1.0.0
     2022 05 31 12:27:15
 *******************************************************************************/
+
+/*******************************************************************************
+    SPI Interface Ports
+    trying to follow instructions from:
+    https://www.chipverify.com/systemverilog/systemverilog-interface
+*******************************************************************************/
+interface spi_interface_ports (input clk);
+// Connection to BUS side (internal)
+  // Inputs from BUS
+  logic sb_clk_i;			// Clock
+  logic sb_stb_i;			// Chip Select from FRAM-Controller who is SPI-Master
+  logic sb_wr_i;			// Write/Read from FRAM-Controller
+  logic sb_adr_i[7:0];		// Adddress from FRAM-Controller
+  logic sb_dat_i[7:0];		// Data in from FRAM-Controller
+  // Outputs to BUS
+  logic sb_dat_o[7:0];		// Data out to FRAM-Controller
+  logic sb_ack_o;			// ACK to FRAM-Controller
+  
+// Connection to SPI side (external)
+  logic spi1_mosi_io;		// MasterOutSlaveIn --> Master to Slave
+  logic spi1_miso_io;		// MasterInSlaveOut --> Slave to Master
+  logic spi1_mcs_n_o[3:0];	// MasterChipSelect --> Master selects Slave
+  logic spi1_sck_io;		// Clock for SPI-Slave
+  
+  // MODPORT form BUS perspective (internal)
+  // modport output from BUS (internal)
+  modport BUS (output sb_clk_i, sb_stb_i, sb_wr_i, sb_adr_i[7:0], sb_dat_i[7:0], spi1_miso_io);
+  // modport input to BUS (internal)
+  modport BUS (input sb_dat_o[7:0], sb_ack_o, spi1_mosi_io, spi1_mcs_n_o[3:0], spi_sck_io);
+  
+  // MODPORT from SPI perspective (external)
+  // modport output from SPI (external)
+  modport SPI (output spi1_miso_io);
+  // modport input to SPI (external)
+  modport SPI (input spi1_mosi_io, spi1_mcs_n_o[3:0], spi_sck_io);
+
+endinterface
+
+
 /*******************************************************************************
     Wrapper Module generated per user settings.
 *******************************************************************************/