kuntzschcl
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ESY1_Projekt_2022
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18 Commits (c7c804a5f9e4dc129722bb48a843e7aaafb1aa07)

Author SHA1 Message Date
  Julian Uebler c7c804a5f9 Verbesserte TB 2 years ago
  sessleral71711 15b48049ab Added SPI interface to top level design 2 years ago
  Julian Uebler a27d049f76 Anfänge einer Tl-TB 2 years ago
  sessleral71711 17f361ea12 I hate git 2 years ago
  sessleral71711 019dc2868e Added parallelport, timer and ampelsteuerung 2 years ago
  sessleral71711 b30efd039d Added bus_if and fsm to top level design 2 years ago
  sessleral71711 ecd6f16dbe merge konflikt behoben 2 years ago
  sessleral71711 6a72019f25 Initalized top level design 2 years ago
  sessleral71711 53868c67fd Added Bus_if and fsm to top level design 2 years ago
  sessleral71711 6ab278694e Initalized top level design 2 years ago
  sessleral71711 026899b930 Added parallelport, timer and ampelsteuerung 2 years ago
  sessleral71711 c93bdaf629 Added bus_if and fsm to top level design 2 years ago
  sessleral71711 1be3ce1cea merge konflikt behoben 2 years ago
  sessleral71711 20f8e707bd Added Bus_if and fsm to top level design 2 years ago
  sessleral71711 6b874ba5c7 Initalized top level design 2 years ago
  sessleral71711 b8d834144b Initalized top level design 2 years ago