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c7c804a5f9
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Verbesserte TB
#100000000 muss öfter aufgerufen werden, sonst zahl zu groß
tb ist noch nicht einmal komplett durchgelaufen
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2022-06-17 10:58:29 +00:00 |
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15b48049ab
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Added SPI interface to top level design
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2022-06-17 11:58:02 +02:00 |
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a27d049f76
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Anfänge einer Tl-TB
Fehlt noch instanziierung modul TL und so weiter und so
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2022-06-14 10:53:32 +00:00 |
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17f361ea12
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I hate git
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2022-06-14 12:33:29 +02:00 |
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730cc895b1
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Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
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2022-06-14 12:32:53 +02:00 |
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019dc2868e
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Added parallelport, timer and ampelsteuerung
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2022-06-14 12:26:26 +02:00 |
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b30efd039d
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Added bus_if and fsm to top level design
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2022-06-14 12:25:53 +02:00 |
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ecd6f16dbe
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merge konflikt behoben
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2022-06-14 12:25:25 +02:00 |
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6a72019f25
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Initalized top level design
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2022-06-14 12:25:19 +02:00 |
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53868c67fd
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Added Bus_if and fsm to top level design
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2022-06-14 12:22:52 +02:00 |
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6ab278694e
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Initalized top level design
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2022-06-14 12:22:52 +02:00 |
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026899b930
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Added parallelport, timer and ampelsteuerung
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2022-06-14 12:21:25 +02:00 |
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c93bdaf629
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Added bus_if and fsm to top level design
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2022-06-14 11:53:20 +02:00 |
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1be3ce1cea
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merge konflikt behoben
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2022-06-14 11:52:04 +02:00 |
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4b0451fc63
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Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
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2022-06-14 11:51:22 +02:00 |
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20f8e707bd
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Added Bus_if and fsm to top level design
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2022-06-14 11:45:29 +02:00 |
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6b874ba5c7
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Initalized top level design
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2022-06-14 11:34:24 +02:00 |
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b8d834144b
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Initalized top level design
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2022-06-14 10:35:05 +02:00 |
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