sessleral71711
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6a72019f25
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Initalized top level design
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2022-06-14 12:25:19 +02:00 |
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sessleral71711
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53868c67fd
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Added Bus_if and fsm to top level design
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2022-06-14 12:22:52 +02:00 |
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sessleral71711
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6ab278694e
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Initalized top level design
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2022-06-14 12:22:52 +02:00 |
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sessleral71711
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d2aa8277c7
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spi_interface dateien
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2022-06-14 11:56:42 +02:00 |
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sessleral71711
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200a989683
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Added modport for timer
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2022-06-14 11:23:54 +02:00 |
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sessleral71711
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613bffbcfc
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Added modport in Bus_if for Fsm
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2022-06-14 11:03:41 +02:00 |
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sessleral71711
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ad550a9ac6
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Created bus as interface
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2022-06-14 10:49:23 +02:00 |
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sessleral71711
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e8af8d04c8
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Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022
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2022-06-14 09:51:22 +02:00 |
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sessleral71711
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71b0458554
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FSM mit 2 States erstellt und getestet
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2022-06-02 09:26:16 +02:00 |
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sessleral71711
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48610eeb8c
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Added Clk_generator
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2022-05-31 12:50:05 +02:00 |
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sessleral71711
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dcb19f11aa
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FSM initial commit
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2022-05-31 12:45:24 +02:00 |
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