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kuntzschcl/ESY1_Projekt_2022
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25 Commits 2 Branches 0 Tags
c93bdaf629c36234379c5ee6bcd9ba666ef19c08
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13 Commits
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Author SHA1 Message Date
sessleral71711 c93bdaf629 Added bus_if and fsm to top level design 2022-06-14 11:53:20 +02:00
sessleral71711 1be3ce1cea merge konflikt behoben 2022-06-14 11:52:04 +02:00
sessleral71711 4b0451fc63 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design 2022-06-14 11:51:22 +02:00
sessleral71711 20f8e707bd Added Bus_if and fsm to top level design 2022-06-14 11:45:29 +02:00
sessleral71711 6b874ba5c7 Initalized top level design 2022-06-14 11:34:24 +02:00
sessleral71711 200a989683 Added modport for timer 2022-06-14 11:23:54 +02:00
sessleral71711 613bffbcfc Added modport in Bus_if for Fsm 2022-06-14 11:03:41 +02:00
sessleral71711 ad550a9ac6 Created bus as interface 2022-06-14 10:49:23 +02:00
sessleral71711 b8d834144b Initalized top level design 2022-06-14 10:35:05 +02:00
sessleral71711 e8af8d04c8 Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 2022-06-14 09:51:22 +02:00
sessleral71711 71b0458554 FSM mit 2 States erstellt und getestet 2022-06-02 09:26:16 +02:00
sessleral71711 48610eeb8c Added Clk_generator 2022-05-31 12:50:05 +02:00
sessleral71711 dcb19f11aa FSM initial commit 2022-05-31 12:45:24 +02:00
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