sessleral71711 - Fakultät Elektrotechnik Feinwerktechnik Informationstechnik

sessleral71711 sessleral71711

Joined on Feb 23, 2022
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sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022

15b48049ab Added SPI interface to top level design

2 years ago

sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022

97113a9804 modports angepasst

2 years ago

sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022

17f361ea12 I hate git
730cc895b1 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
019dc2868e Added parallelport, timer and ampelsteuerung
b30efd039d Added bus_if and fsm to top level design
ecd6f16dbe merge konflikt behoben
Compare 15 commits »

2 years ago

sessleral71711 pushed to top_level_design at kuntzschcl/ESY1_Projekt_2022

17f361ea12 I hate git
730cc895b1 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
019dc2868e Added parallelport, timer and ampelsteuerung
b30efd039d Added bus_if and fsm to top level design
ecd6f16dbe merge konflikt behoben
Compare 12 commits »

2 years ago

sessleral71711 pushed to top_level_design at kuntzschcl/ESY1_Projekt_2022

026899b930 Added parallelport, timer and ampelsteuerung

2 years ago

sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022

d2aa8277c7 spi_interface dateien

2 years ago

sessleral71711 pushed to top_level_design at kuntzschcl/ESY1_Projekt_2022

c93bdaf629 Added bus_if and fsm to top level design
1be3ce1cea merge konflikt behoben
4b0451fc63 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
20f8e707bd Added Bus_if and fsm to top level design
6b874ba5c7 Initalized top level design
Compare 11 commits »

2 years ago

sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022

200a989683 Added modport for timer

2 years ago

sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022

613bffbcfc Added modport in Bus_if for Fsm

2 years ago

sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022

ad550a9ac6 Created bus as interface

2 years ago

sessleral71711 pushed to top_level_design at kuntzschcl/ESY1_Projekt_2022

b8d834144b Initalized top level design

2 years ago

sessleral71711 deleted branch sessleral71711_fsm from kuntzschcl/ESY1_Projekt_2022

2 years ago

sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022

e8af8d04c8 Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022
ca1f1b531c Dateien hochladen nach „“
71b0458554 FSM mit 2 States erstellt und getestet
48610eeb8c Added Clk_generator
dcb19f11aa FSM initial commit
Compare 5 commits »

2 years ago

sessleral71711 pushed to sessleral71711_fsm at kuntzschcl/ESY1_Projekt_2022

71b0458554 FSM mit 2 States erstellt und getestet

2 years ago

sessleral71711 pushed to sessleral71711_fsm at kuntzschcl/ESY1_Projekt_2022

48610eeb8c Added Clk_generator

2 years ago

sessleral71711 pushed to sessleral71711_fsm at kuntzschcl/ESY1_Projekt_2022

dcb19f11aa FSM initial commit

2 years ago