sessleral71711 sessleral71711
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  • Joined on 2022-02-23
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sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-17 09:58:22 +00:00
15b48049ab Added SPI interface to top level design
sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-17 09:49:47 +00:00
97113a9804 modports angepasst
sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-14 10:37:48 +00:00
17f361ea12 I hate git
730cc895b1 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
019dc2868e Added parallelport, timer and ampelsteuerung
b30efd039d Added bus_if and fsm to top level design
ecd6f16dbe merge konflikt behoben
Compare 15 commits »
sessleral71711 pushed to top_level_design at kuntzschcl/ESY1_Projekt_2022 2022-06-14 10:33:48 +00:00
17f361ea12 I hate git
730cc895b1 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
019dc2868e Added parallelport, timer and ampelsteuerung
b30efd039d Added bus_if and fsm to top level design
ecd6f16dbe merge konflikt behoben
Compare 12 commits »
sessleral71711 pushed to top_level_design at kuntzschcl/ESY1_Projekt_2022 2022-06-14 10:21:39 +00:00
026899b930 Added parallelport, timer and ampelsteuerung
sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-14 09:56:54 +00:00
d2aa8277c7 spi_interface dateien
sessleral71711 pushed to top_level_design at kuntzschcl/ESY1_Projekt_2022 2022-06-14 09:53:31 +00:00
c93bdaf629 Added bus_if and fsm to top level design
1be3ce1cea merge konflikt behoben
4b0451fc63 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
20f8e707bd Added Bus_if and fsm to top level design
6b874ba5c7 Initalized top level design
Compare 11 commits »
sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-14 09:24:09 +00:00
200a989683 Added modport for timer
sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-14 09:03:53 +00:00
613bffbcfc Added modport in Bus_if for Fsm
sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-14 08:49:47 +00:00
ad550a9ac6 Created bus as interface
sessleral71711 pushed to top_level_design at kuntzschcl/ESY1_Projekt_2022 2022-06-14 08:35:32 +00:00
b8d834144b Initalized top level design
sessleral71711 deleted branch sessleral71711_fsm from kuntzschcl/ESY1_Projekt_2022 2022-06-14 07:58:09 +00:00
sessleral71711 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-14 07:51:42 +00:00
e8af8d04c8 Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022
ca1f1b531c Dateien hochladen nach „“
71b0458554 FSM mit 2 States erstellt und getestet
48610eeb8c Added Clk_generator
dcb19f11aa FSM initial commit
Compare 5 commits »
sessleral71711 pushed to sessleral71711_fsm at kuntzschcl/ESY1_Projekt_2022 2022-06-02 07:26:35 +00:00
71b0458554 FSM mit 2 States erstellt und getestet
sessleral71711 pushed to sessleral71711_fsm at kuntzschcl/ESY1_Projekt_2022 2022-05-31 10:50:13 +00:00
48610eeb8c Added Clk_generator
sessleral71711 pushed to sessleral71711_fsm at kuntzschcl/ESY1_Projekt_2022 2022-05-31 10:45:33 +00:00
dcb19f11aa FSM initial commit