 sessleral71711
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026899b930
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Added parallelport, timer and ampelsteuerung
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2 years ago |
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sessleral71711
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c93bdaf629
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Added bus_if and fsm to top level design
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2 years ago |
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sessleral71711
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1be3ce1cea
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merge konflikt behoben
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2 years ago |
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sessleral71711
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4b0451fc63
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Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
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2 years ago |
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sessleral71711
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20f8e707bd
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Added Bus_if and fsm to top level design
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2 years ago |
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sessleral71711
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6b874ba5c7
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Initalized top level design
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2 years ago |
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sessleral71711
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200a989683
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Added modport for timer
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2 years ago |
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sessleral71711
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613bffbcfc
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Added modport in Bus_if for Fsm
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2 years ago |
 Christoph Reuss
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19177edb3f
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Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022
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2 years ago |
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Christoph Reuss
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0ecac8324e
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Timer and Port source
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2 years ago |
 Julian Uebler
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37989e5bc1
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Ampel
Ampelsteuerung mit toplevel_verbindungen sowie normaler TB und random TB
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2 years ago |
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sessleral71711
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ad550a9ac6
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Created bus as interface
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2 years ago |
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sessleral71711
|
b8d834144b
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Initalized top level design
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2 years ago |
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sessleral71711
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e8af8d04c8
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Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022
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2 years ago |
 Claus Kuntzsch
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ca1f1b531c
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Dateien hochladen nach „“
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2 years ago |
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Claus Kuntzsch
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7b858e7068
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Dateien hochladen nach „“
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2 years ago |
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sessleral71711
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71b0458554
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FSM mit 2 States erstellt und getestet
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2 years ago |
 Ralph Badenberg
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700350608a
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Dateien hochladen nach „“
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2 years ago |
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sessleral71711
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48610eeb8c
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Added Clk_generator
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2 years ago |
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sessleral71711
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dcb19f11aa
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FSM initial commit
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2 years ago |
 Kseniia Mikhailova
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937da8ec22
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Dateien hochladen nach „“
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2 years ago |
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Claus Kuntzsch
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1cf5934374
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„memory.txt“ löschen
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2 years ago |
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Claus Kuntzsch
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667101d7fd
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„SPI_FRAM_Module.sv“ löschen
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2 years ago |
 kuntzschcl
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08300af99a
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FRAM
added FRAM sources
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2 years ago |
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Claus Kuntzsch
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f691d1318a
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Dateien hochladen nach „“
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2 years ago |
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kuntzschcl
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fec9cd1ae0
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Create FM25CL64B.pdf
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2 years ago |
