I hate git

Bus_if/Bus_if.sv

@@ -9,7 +9,6 @@ interface Bus_if (input clk);
     logic[9:0] Data;
     logic SendData;
     logic TimerMeas;
-    logic Clk;
     logic DataValid;
     logic AlarmAmpel;
     logic TasteAktiv;
@@ -19,4 +18,28 @@ interface Bus_if (input clk);
     logic ReadTemp;
     logic LEDg;
     logic LEDr;
+
+    modport Fsm (
+        input clk,
+        input AlarmAmpel,
+        input DataValid,
+        input TasteAktiv,
+        output Alarm_R,
+        output SendData,
+        output TimerEN
+    );
+
+    modport timer (
+        input clk,
+        input Taste,
+        input TimerEN,
+        output ReadTemp,
+        output TasteAktiv
+    );
+
+/*
+    module parallelport wird in top level design
+    ohne modport verbunden, da inEndOfConv nicht
+    Teil des Bus_if ist.
+*/
 endinterface //Bus

Source_Ampel/rgb_led_top.sv

@@ -3,8 +3,6 @@ input wire clk12M,
 input wire rst,
 input wire [7:0] data_input,
 input wire data_valid,
-output reg REDn,
-output reg GRNn,
 output reg RED,
 output reg GRN,
 output reg alarm
@@ -12,7 +10,8 @@ output reg alarm
 
 wire red_pwm;
 wire grn_pwm;
-
+reg REDn;
+reg GRNn;
 defparam U1.on_hi 			= 2'b10;
 defparam U1.on_lo 			= 2'b01;
 defparam U1.off   			= 2'b00; 

Top/Top.sv

@@ -0,0 +1,57 @@
+`include "../spi_interface.v"
+`include "../fsm/Fsm.sv"
+`include "../Bus_if/Bus_if.sv"
+`include "../timer_port/timer_top.sv"
+
+module Top(
+    input wire clk,
+    input wire rst,
+    input wire endOfConv,
+    output wire LEDg,
+    output wire LEDr,
+    output wire AlarmAmpel
+);
+    // Bus (Interface)
+    Bus_if bus(.clk(clk));
+    // SPI Interface
+    // FSM
+    Fsm fsm(
+        .clk(clk),
+        .inAlarmAmpel(bus.AlarmAmpel),
+        .inDataValid(bus.DataValid),
+        .inTasteAktiv(bus.TasteAktiv),
+        .outAlarm_R(bus.Alarm_R),
+        .outSendData(bus.SendData),
+        .outTimerEN(bus.TimerEN)
+    );
+    // Parallelport
+    parallelport parallelport1 (
+        .inClk(clk),
+        .inTimerMeas(bus.TimerMeas),
+        .inEndOfConv(endOfConv),
+        .inData(bus.Data),
+        .outDataValid(bus.DataValid),
+        .outData(bus.Data)
+    );
+    // FRAM-Controller
+    // Timer
+    timer timer1 (
+        .inClk(clk),
+        .inTaste(bus.Taste),
+        .inEN(bus.TimerEN),
+        .outReadTemp(bus.ReadTemp),
+        .outTasteAktiv(bus.TasteAktiv)
+    );
+    // Ampelsteuerung
+    led_top ampelsteuerung (
+        .clk12M(clk),
+        .rst(rst),
+        .data_input(bus.Data),
+        .data_valid(bus.DataValid),
+        .RED(LEDr),
+        .GRN(LEDg),
+        .alarm(bus.AlarmAmpel)
+    );
+
+    assign AlarmAmpel = bus.AlarmAmpel;  
+endmodule

Top/tb_Top.sv

@@ -0,0 +1,5 @@
+`include "Top.sv"
+
+module tb_Top;
+    
+endmodule

spi_interface_radiant/spi_interface.v

@@ -5,6 +5,45 @@
     Soft IP Version: 1.0.0
     2022 05 31 12:27:15
 *******************************************************************************/
+
+/*******************************************************************************
+    SPI Interface Ports
+    trying to follow instructions from:
+    https://www.chipverify.com/systemverilog/systemverilog-interface
+*******************************************************************************/
+interface spi_interface_ports (input clk);
+// Connection to BUS side (internal)
+  // Inputs from BUS
+  logic sb_clk_i;			// Clock
+  logic sb_stb_i;			// Chip Select from FRAM-Controller who is SPI-Master
+  logic sb_wr_i;			// Write/Read from FRAM-Controller
+  logic sb_adr_i[7:0];		// Adddress from FRAM-Controller
+  logic sb_dat_i[7:0];		// Data in from FRAM-Controller
+  // Outputs to BUS
+  logic sb_dat_o[7:0];		// Data out to FRAM-Controller
+  logic sb_ack_o;			// ACK to FRAM-Controller
+  
+// Connection to SPI side (external)
+  logic spi1_mosi_io;		// MasterOutSlaveIn --> Master to Slave
+  logic spi1_miso_io;		// MasterInSlaveOut --> Slave to Master
+  logic spi1_mcs_n_o[3:0];	// MasterChipSelect --> Master selects Slave
+  logic spi1_sck_io;		// Clock for SPI-Slave
+  
+  // MODPORT form BUS perspective (internal)
+  // modport output from BUS (internal)
+  modport BUS (output sb_clk_i, sb_stb_i, sb_wr_i, sb_adr_i[7:0], sb_dat_i[7:0], spi1_miso_io);
+  // modport input to BUS (internal)
+  modport BUS (input sb_dat_o[7:0], sb_ack_o, spi1_mosi_io, spi1_mcs_n_o[3:0], spi_sck_io);
+  
+  // MODPORT from SPI perspective (external)
+  // modport output from SPI (external)
+  modport SPI (output spi1_miso_io);
+  // modport input to SPI (external)
+  modport SPI (input spi1_mosi_io, spi1_mcs_n_o[3:0], spi_sck_io);
+
+endinterface
+
+
 /*******************************************************************************
     Wrapper Module generated per user settings.
 *******************************************************************************/

timer_port/testbench.sv

@@ -0,0 +1,87 @@
+// Code your testbench here
+// or browse Examples
+
+
+`timescale 1ns/1ps;
+module tb();
+  reg inClk, inEN, inTaste;
+  wire outReadTemp;
+  wire outTasteAktiv;
+
+  reg [7:0] inData;
+  reg inEndOfConv;
+  wire outDataValid;
+  wire [7:0] outData;
+  
+  
+  
+  timer t1 (.inClk(inClk),
+			.inTaste(inTaste),
+			.inEN(inEN),
+            .outReadTemp(outReadTemp),
+			.outTasteAktiv(outTasteAktiv));
+			
+			
+  parallelport p1 (.inData(inData),
+					.inClk(inClk),
+					.inTimerMeas(outReadTemp),
+					.inEndOfConv(inEndOfConv), 
+					.outDataValid(outDataValid), 
+					.outData(outData));
+            
+           
+  always #83 inClk <= ~inClk;
+  always #1000000000 inEndOfConv <= ~inEndOfConv;
+  always #100000000 inData = inData +1;
+  
+  initial begin
+    //$dumpfile("dump.vcd");
+    //$dumpvars;
+    inClk <= 0;
+	inEN <= 0;
+	inTaste <= 0;
+
+	inData <= 8'b0;
+	inEndOfConv <= 0;
+	#1000000000
+	inTaste = 1;
+	#1000000000
+	#1000000000
+	#1000000000
+	inTaste = 0;
+	#1000000000
+	inEN <= 1;
+	#1000000000
+	inEN <= 0;
+	#1000000000
+	
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	$stop;
+  end
+endmodule

timer_port/timer_top.sv

@@ -0,0 +1,62 @@
+//clock divider
+module timer(input inClk, inTaste, inEN, output reg outReadTemp, outTasteAktiv);
+  int divide1 = 30000000;
+  int divide2 = 60000;
+  
+  logic 			state = 0;
+  logic [31:0] 		count1 = 32'b0;
+  logic [31:0]		count2 = 32'b0;
+  
+  initial begin
+    outReadTemp = 0;
+	outTasteAktiv = 0;
+  end
+
+   always @(posedge inClk or posedge inEN) begin
+	   if(inEN) begin
+      count1 <= 0;
+	  count2 <= 0;
+	  outReadTemp <= 0;
+	   end
+	else begin
+      count1 <= count1 +1;
+     if(count1>=((2**32)-1))
+		count1 <= 32'b0;
+     if(count1 % divide1 == 0)
+       outReadTemp <= ~outReadTemp;
+		
+	if(inTaste) begin
+		count2 <= count2 +1;
+		if(count2 >= 6000000) 
+			outTasteAktiv = 1;
+		end
+		else begin
+			outTasteAktiv <= 0;
+			count2 <= 0;
+	end	
+	end
+	end
+endmodule // clk_divider
+
+module parallelport(input inClk, inTimerMeas, inEndOfConv, [7:0] inData, output reg outDataValid, [7:0] outData);
+
+	logic [7:0] 		storage = 8'b0;
+	
+	
+	initial begin
+		outDataValid <= 0;
+		outData <= 8'b0;
+		end
+		
+		always @(posedge inClk) begin
+			if(inEndOfConv)
+				storage <= inData;
+			
+			if(inTimerMeas == 1 && outDataValid == 0) begin
+				outData = storage;
+				outDataValid <= 1;
+			end
+			else if(inTimerMeas == 0)
+				outDataValid <= 0;
+		end	
+endmodule