Kommentare in Sourcecode ergänzt

#100000000 muss öfter aufgerufen werden, sonst zahl zu groß
tb ist noch nicht einmal komplett durchgelaufen

Bus_if/Bus_if.sv

@@ -0,0 +1,45 @@
+interface Bus_if (input clk);
+    logic sbclk;
+    logic sbstb;
+    logic sbrw;
+    logic[7:0] sbadr;
+    logic[7:0] sbdat_r;
+    logic[7:0] sbdat_w;
+    logic sback;
+    logic[9:0] Data;
+    logic SendData;
+    logic TimerMeas;
+    logic DataValid;
+    logic AlarmAmpel;
+    logic TasteAktiv;
+    logic Alarm_R;
+    logic TimerEN;
+    logic Taste;
+    logic ReadTemp;
+    logic LEDg;
+    logic LEDr;
+
+    modport Fsm (
+        input clk,
+        input AlarmAmpel,
+        input DataValid,
+        input TasteAktiv,
+        output Alarm_R,
+        output SendData,
+        output TimerEN
+    );
+
+    modport timer (
+        input clk,
+        input Taste,
+        input TimerEN,
+        output ReadTemp,
+        output TasteAktiv
+    );
+
+/*
+    module parallelport wird in top level design
+    ohne modport verbunden, da inEndOfConv nicht
+    Teil des Bus_if ist.
+*/
+endinterface //Bus

Source_Ampel/LED_control.sv

@@ -0,0 +1,184 @@
+//   ==================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+//   ------------------------------------------------------------------
+//   Copyright (c) 2022 by Ampelsteuerungsgruppe
+//
+// --------------------------------------------------------------------
+//
+//  Project:           iCE5UP 5K RGB LED Steuerung
+//  File:              LED_control.sv
+//  Title:             LED Ampelsteuerung
+//  Description:       Creates RGB PWM per data input
+//                 
+//
+// --------------------------------------------------------------------
+//
+//------------------------------------------------------------
+// Notes:
+//
+//
+//------------------------------------------------------------
+// Development History:
+//
+//   __DATE__ _BY_ _____REV_ _DESCRIPTION___________________________
+//   17.02.22  AmpelGr  1.0    Initial design for Lattice Radiant Ampelsteuerung
+//
+//------------------------------------------------------------
+// Dependencies:
+//
+// 
+//
+//------------------------------------------------------------
+
+
+module LED_control1 (
+        // inputs
+        input   wire    clk12M,        		// 12M clock
+		input 	wire 	enable,             // Asynchronous enable/disable wire
+        input   wire    [7:0] data_input,  	// for selecting color using sensor data
+		input 	wire 	data_valid,			// Data on Parallelport is valid on posedge
+        //outputs
+        output reg  red_pwm,       	// Red LED
+        output reg  grn_pwm,       	// Green LED
+		output reg	alarm			// Alarmmeldung
+        );
+
+
+//------------------------------
+// INTERNAL SIGNAL DECLARATIONS: 
+//------------------------------
+// parameters (constants)
+parameter     on_hi = 2'b10;
+parameter     on_lo = 2'b01;
+parameter     off   = 2'b00; 
+parameter Brightness=4'b0111; //50% Brightness
+
+// wires (assigns)
+wire   [4:0] red_intensity;
+wire   [4:0] grn_intensity;
+wire clk24M;
+wire LOCK;
+
+// regs (always)
+reg     [1:0] RGB_color_s;    		// selected Color    
+reg     [3:0] Brightness_s;              
+
+reg     [1:0] red_set;		  		// hi/lo/off
+reg     [1:0] grn_set;		  	  
+
+reg    [17:0] red_peak;		  		// LED 'on' peak intensity (high precision)
+reg    [17:0] grn_peak;
+
+reg     [17:0] curr_red;			// current LED intensity ( /256 = PWM duty cycle)
+reg     [17:0] curr_grn;
+
+reg     [17:0] pwm_count;           // PWM counter
+reg [7:0] count = 8'b0;
+
+//------------------------------
+// PLL Instantiation
+//------------------------------
+//Block to reset the PLL initially
+
+pll_24M __(.ref_clk_i(clk12M ), .rst_n_i(~enable), .lock_o(LOCK), .outcore_o( ), .outglobal_o(clk24M));
+
+
+//   Capture stable parameters in local clock domain
+always @ (posedge clk24M or posedge enable)
+    if (enable) begin
+      RGB_color_s   <= 2'b00;	//turn off
+      Brightness_s  <= 4'b0000;
+	  alarm <= 0;
+    end else if(!alarm) begin
+		if(data_valid) begin
+			if(data_input <100) begin
+				RGB_color_s <= 2'b10; // set green
+				Brightness_s  <= Brightness;
+			end else if(data_input >168) begin
+				alarm <=1'b1;
+			end else begin
+				RGB_color_s <= 2'b11; // set yellow
+				Brightness_s  <= Brightness;
+			end
+		end
+    end else begin   
+      RGB_color_s   <= 2'b01; // set Color red
+      Brightness_s  <= Brightness;
+    end
+
+
+// interpret 'brightness' setting
+assign red_intensity =  Brightness_s + 1'b1;
+assign grn_intensity = Brightness_s + 1'b1;
+
+
+// interpret 'color' setting
+always @ (RGB_color_s)	 
+  case (RGB_color_s)
+    2'b01:   begin red_set   <= on_hi; grn_set   <= off;    end //Red
+    4'b10:   begin red_set   <= off;   grn_set   <= on_hi;  end //Green
+    4'b11:   begin red_set   <= on_hi; grn_set   <= on_hi;  end //Yellow
+    default: begin red_set   <= off;   grn_set   <= off;    end //2'b00 off
+  endcase
+
+// set peak values per 'brightness' and 'color'
+//   when color setting is 'on_lo', then peak intensity is divided by 2
+always @ (posedge clk24M or posedge enable)
+    if (enable) begin
+      red_peak <= 18'b0;
+    end else begin
+      case (red_set)
+        on_hi:  red_peak <= {red_intensity, 13'h000};       // 100%
+        on_lo:  red_peak <= {1'b0,red_intensity, 12'h000}; // 50%
+        default: red_peak <= 18'h00000;
+      endcase
+    end
+    
+always @ (posedge clk24M or posedge enable)
+    if (enable) begin
+      grn_peak <= 32'b0;
+    end else begin
+      case (grn_set)
+        on_hi:  grn_peak <= {grn_intensity, 13'h000};       // 100%
+        on_lo:  grn_peak <= {1'b0,grn_intensity, 12'h000}; // 50%
+        default: grn_peak <= 18'h00000;
+      endcase
+	  //$monitor("grn_peak=%d",grn_peak);
+    end
+
+// set PWM duty cycle. 8-bit resolution 0x100 is 100% on
+always @ (posedge clk24M or posedge enable)
+    if (enable) begin
+	  curr_red <= 18'b0;
+      curr_grn <= 18'b0;
+    end else begin
+        curr_red <= red_peak;
+        curr_grn <= grn_peak;
+        end
+
+// generate PWM outputs
+always @ (posedge clk24M or posedge enable)
+    if (enable) begin
+      pwm_count <= 18'b0;
+      red_pwm   <= 0;
+      grn_pwm   <= 0;
+    end else begin
+      if(pwm_count < 131071)
+        pwm_count <= pwm_count + 1;
+      else
+        pwm_count <= 0;
+      
+      if(pwm_count < curr_red)       
+        red_pwm <= 1;
+      else
+        red_pwm <= 0;
+
+      if(pwm_count < curr_grn)
+        grn_pwm <= 1;
+      else
+        grn_pwm <= 0;
+		
+    end
+
+
+endmodule // LED_control

Source_Ampel/rgb_led_top.sv

@@ -0,0 +1,45 @@
+module led_top (       
+input wire clk12M,
+input wire rst,
+input wire [7:0] data_input,
+input wire data_valid,
+output reg RED,
+output reg GRN,
+output reg alarm
+); 
+
+wire red_pwm;
+wire grn_pwm;
+reg REDn;
+reg GRNn;
+defparam U1.on_hi 			= 2'b10;
+defparam U1.on_lo 			= 2'b01;
+defparam U1.off   			= 2'b00; 
+defparam U1.Brightness		= 4'b0111; 		//	50% Brightness
+defparam U2.RGB0_CURRENT 	= "0b111111";
+defparam U2.RGB1_CURRENT 	= "0b111111";
+defparam U2.RGB2_CURRENT 	= "0b111111";
+
+LED_control1 U1 (.clk12M(clk12M),.enable(rst),.data_input(data_input),.data_valid(data_valid),.red_pwm(red_pwm),.grn_pwm(grn_pwm),.alarm(alarm));
+
+
+RGB U2 (.CURREN('b1),.RGB0PWM(),.RGB1PWM(grn_pwm),.RGB2PWM(red_pwm),.RGBLEDEN('b1),.RGB0(),.RGB1(GRNn),.RGB2(REDn));
+
+assign RED = red_pwm;
+assign GRN = grn_pwm;
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+

Source_Ampel/testbench.sv

@@ -0,0 +1,141 @@
+//   ==================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+//   ------------------------------------------------------------------
+//   Copyright (c) 2017 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED  
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   --------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Lt++++++++++++++++d.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+// --------------------------------------------------------------------
+//
+//  Project:           iCE5UP 5K RGB LED Tutorial 
+//  File:              testbench.v
+//  Title:             LED PWM control
+//  Description:       Creates RGB PWM per control inputs
+//                 
+//
+// --------------------------------------------------------------------
+//
+//------------------------------------------------------------
+// Notes:
+//
+//
+//------------------------------------------------------------
+// Development History:
+//
+//   __DATE__ _BY_ _REV_ _DESCRIPTION___________________________
+//   04/05/17  RK  1.0    Initial tutorial design for Lattice Radiant
+//
+//------------------------------------------------------------
+// Dependencies:
+//
+// 
+//
+//------------------------------------------------------------
+
+
+
+//------------------------------------------------------------
+// 
+//
+//                     Testbench
+//
+//------------------------------------------------------------
+`timescale 1ns/1ps
+module tb;
+	
+//GSR GSR_INST ( .GSR(1));
+//PUR PUR_INST ( .PUR(1));
+
+
+
+reg clk12M;
+reg rst;
+reg [9:0]data_input;
+reg data_valid;
+wire RED;
+wire GRN;
+wire alarm;
+
+led_top dut(.clk12M(clk12M),
+			.rst(rst),
+			.data_input(data_input),
+			.data_valid(data_valid),
+			.RED(RED),
+			.GRN(GRN),
+			.alarm(alarm)
+			);     
+
+initial
+begin
+    clk12M=1'b0;
+end
+
+always 
+  #41.666666 clk12M=~clk12M;                             //clock generation
+  
+
+ initial
+ begin             
+ rst=1'b1; 
+ data_input=10'b0000000010; // data for green
+ data_valid=1'b0; 
+ #500000
+ rst=1'b0;
+ #500000
+ data_valid = 1'b1;
+ #500000
+ data_valid = 1'b0;
+ #500000
+ rst=1'b1;
+ #500000
+ rst=1'b0;
+ data_valid=1'b1;
+ data_input=10'b1000000001; // data for yellow
+ #500000
+ data_valid=1'b0; 
+ data_input = 10'b1100000001; //data for red
+ #500000
+data_valid = 1'b1;
+ #500000
+  data_input=10'b1000000001; // data for yellow
+ #500000
+rst=1'b1;
+ #500000   
+ $stop;
+ end 
+ 
+ initial
+	 begin
+		 $monitor("time=%t,rst=%d,",$time,rst);
+	end
+
+endmodule

Source_Ampel/testbench_random.sv

@@ -0,0 +1,155 @@
+//   ==================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+//   ------------------------------------------------------------------
+//   Copyright (c) 2017 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED  
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   --------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Lt++++++++++++++++d.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+// --------------------------------------------------------------------
+//
+//  Project:           iCE5UP 5K RGB LED Tutorial 
+//  File:              testbench.v
+//  Title:             LED PWM control
+//  Description:       Creates RGB PWM per control inputs
+//                 
+//
+// --------------------------------------------------------------------
+//
+//------------------------------------------------------------
+// Notes:
+//
+//
+//------------------------------------------------------------
+// Development History:
+//
+//   __DATE__ _BY_ _REV_ _DESCRIPTION___________________________
+//   04/05/17  RK  1.0    Initial tutorial design for Lattice Radiant
+//
+//------------------------------------------------------------
+// Dependencies:
+//
+// 
+//
+//------------------------------------------------------------
+
+
+
+//------------------------------------------------------------
+// 
+//
+//                     Testbench
+//
+//------------------------------------------------------------
+
+class Rst_rnd;
+	rand bit [1:0] data;
+	constraint Rst_rnd
+	{
+	data dist {0:=70,1 :=30};
+	}
+endclass
+class Data_valid_rnd;
+	rand bit [1:0] data;
+	constraint Data_valid_data
+	{
+	data dist {0:=10,1 :=90};
+	}
+endclass
+
+class Data_input_rnd;
+	rand bit [7:0] data;
+endclass
+
+
+
+
+`timescale 1ns/1ps
+// inputs and outputs
+module tb;
+reg clk12M;
+reg rst;
+reg [7:0]data_input;
+reg data_valid;
+wire RED;
+wire GRN;
+wire alarm;
+//random
+Rst_rnd rst_rnd = new();
+Data_valid_rnd data_valid_rnd = new();
+Data_input_rnd data_input_rnd = new();
+// connect module
+led_top dut(.clk12M(clk12M),
+			.rst(rst),
+			.data_input(data_input),
+			.data_valid(data_valid),
+			.RED(RED),
+			.GRN(GRN),
+			.alarm(alarm)
+			);     
+//clock
+initial
+begin
+    clk12M=1'b0;
+end
+always 
+  #41.666666 clk12M=~clk12M;                             //clock generation
+  int cycles = 0;
+//random test
+ initial begin       
+	repeat (50) begin
+		#50000
+		cycles =cycles+1;
+		rst_rnd.randomize();
+		data_input_rnd.randomize();
+		data_valid_rnd.randomize();
+		rst = rst_rnd.data;
+		data_input = data_input_rnd.data;
+		data_valid = data_valid_rnd.data;
+		// assertions
+		// assert that reset resets
+		assert property ( @(posedge clk12M) (##1 rst) |=> !alarm);
+		// assert color green
+		assert property(@(posedge clk12M) disable iff (rst | !data_valid| alarm) ((data_input < 100) |=> ##4 (!RED && GRN));
+		
+		//assert color yellow
+		
+		assert property(@(posedge clk12M) disable iff (rst | !data_valid| alarm) ((data_input >= 100) && (data_input <= 168))|=> ##4 (RED && GRN));
+		
+		//assert color red + alarm
+		
+		assert property(@(posedge clk12M) disable iff (rst | !data_valid) (data_input > 168) |=> ##4 (RED && !GRN && alarm));
+		$monitor("time=%t,cycle%d, rst=%d, data_input=%d, data_valid = %d, RED=%d, GRN=%d, alarm=%d",$time,cycles,rst,data_input, data_valid, RED, GRN, alarm);
+	end
+	$stop;
+end
+
+endmodule

Top/Top.sv

@@ -0,0 +1,69 @@
+`include "../fsm/Fsm.sv"
+`include "../Bus_if/Bus_if.sv"
+`include "../timer_port/timer_top.sv"
+`include "../spi_interface_radiant/spi_interface.sv"
+
+module Top(
+    input wire clk,
+    input wire rst,
+    input wire endOfConv,
+    output wire LEDg,
+    output wire LEDr,
+    output wire AlarmAmpel,
+    output wire Alarm_R
+);
+    // Bus (Interface)
+    Bus_if bus(.clk(clk));
+    // SPI Interface
+    spi_interface_ports spi_bus(.clk(clk));
+
+    // FSM
+    Fsm fsm(
+        .clk(clk),
+        .inAlarmAmpel(bus.AlarmAmpel),
+        .inDataValid(bus.DataValid),
+        .inTasteAktiv(bus.TasteAktiv),
+        .outAlarm_R(bus.Alarm_R),
+        .outSendData(bus.SendData),
+        .outTimerEN(bus.TimerEN)
+    );
+    // Parallelport
+    parallelport parallelport1 (
+        .inClk(clk),
+        .inTimerMeas(bus.TimerMeas),
+        .inEndOfConv(endOfConv),
+        .inData(bus.Data),
+        .outDataValid(bus.DataValid),
+        .outData(bus.Data)
+    );
+    // FRAM-Controller
+    // Timer
+    timer timer1 (
+        .inClk(clk),
+        .inTaste(bus.Taste),
+        .inEN(bus.TimerEN),
+        .outReadTemp(bus.ReadTemp),
+        .outTasteAktiv(bus.TasteAktiv)
+    );
+    // Ampelsteuerung
+    led_top ampelsteuerung (
+        .clk12M(clk),
+        .rst(rst),
+        .data_input(bus.Data),
+        .data_valid(bus.DataValid),
+        .RED(LEDr),
+        .GRN(LEDg),
+        .alarm(bus.AlarmAmpel)
+    );
+
+    assign AlarmAmpel = bus.AlarmAmpel;
+    assign Alarm_R = bus.Alarm_R;
+
+    assign bus.sbclk = spi_bus.sb_clk_i;
+    assign bus.sbstb = spi_bus.sb_stb_i;
+    assign bus.sbrw = spi_bus.sb_wr_i;
+    assign bus.sbadr = spi_bus.sb_adr_i;
+    assign bus.sbdat_r = spi_bus.sb_dat_i;
+    assign bus.sbdat_w = spi_bus.sb_dat_o;
+    assign bus.sback = spi_bus.sb_ack_o;
+endmodule

Top/random_tl.sv

@@ -0,0 +1,128 @@
+//  Project:           ESY-Praktikum-Testbench
+//  File:              random_tl.sv
+//  Title:             Random Testbench Toplevel
+//  Description:       Creates a Testbench that tests the Toplevel-Design with random based verifikation
+//                 
+//
+// --------------------------------------------------------------------
+//
+//------------------------------------------------------------
+// Notes:
+//
+//
+//------------------------------------------------------------
+// Development History:
+//
+//   __DATE__ _BY_ _REV_ _DESCRIPTION___________________________
+//   14/06/22  JU/TL  1.0    Initial testbench design
+//
+//------------------------------------------------------------
+// Dependencies:
+//	Toplevel-Design
+// 
+//
+//------------------------------------------------------------
+
+
+
+//------------------------------------------------------------
+// 
+//
+//                     Testbench
+//
+//------------------------------------------------------------
+
+class Taster_rnd;
+	rand bit [1:0] data;
+	constraint Rst_rnd
+	{
+	data dist {0:=70,1 :=30};
+	}
+endclass
+
+class Data_ADC_rnd;
+	rand bit [7:0] data;
+endclass
+
+
+`timescale 1ns/1ps
+module tb;
+
+// inputs and outputs
+reg taster;
+reg [7:0]data_ADC;
+reg clk12M;
+wire RED;
+wire GRN;
+wire alarm;
+wire alarm_r;
+wire SI;
+wire SO;
+wire SCK;
+wire nCS;
+reg endOfConvRnd;
+
+//random
+Taster_rnd taster_rnd = new();
+Data_ADC_rnd data_ADC_rnd = new();
+
+// connect module
+SPI_FRAM_Module fram_storage(
+.SI(SI),
+.SO(SO),
+.SCK(SCK),
+.nCS(nCS),.opcode(),.addr());
+Top top(.clk(clk12M),.rst(taster),.endOfConv(endOfConvRnd),.LEDg(GRN),.LEDr(RED),.AlarmAmpel(alarm),.Alarm_R(alarm_r));
+
+initial
+begin
+    clk12M=1'b0;
+end
+always 
+  #41.666666 clk12M=~clk12M;                             //clock generation
+  
+//random test
+ initial begin
+		endOfConvRnd = 1;	 
+	repeat (2) begin
+		#100000000
+		#100000000
+		#100000000
+		#100000000
+		#100000000
+		#100000000
+		#100000000
+		#100000000
+		#100000000
+		#100000000
+		data_ADC_rnd.randomize();
+		taster_rnd.randomize();
+		
+		taster = taster_rnd.data;		
+		data_ADC = data_ADC_rnd.data;
+
+		
+		// assertions
+
+		// assert color green
+		assert property(@(posedge clk12M) disable iff (alarm | alarm_r) ((data_ADC < 100) |=> ##4 (!RED && GRN)));
+		
+		//assert color yellow
+		
+		assert property(@(posedge clk12M) disable iff (alarm | alarm_r) (((data_ADC >= 100) && (data_ADC <= 168))|=> ##4 (RED && GRN)));
+		
+		//assert color red + alarm
+		
+		assert property(@(posedge clk12M) disable iff (alarm_r) (data_ADC > 168) |=> ##4 (RED && !GRN && alarm));
+		
+		//assert alarm reset working
+		
+		assert property(@(posedge clk12M) (alarm_r |=> ##4 (!RED && !GRN && !alarm)));
+		
+		$monitor("time=%t, data_ADC=%d, RED=%d, GRN=%d, taster=%d",$time,data_ADC, RED, GRN, taster);
+	end
+	$stop;
+end
+
+endmodule
+

Top/tb_Top.sv

@@ -0,0 +1,5 @@
+`include "Top.sv"
+
+module tb_Top;
+    
+endmodule

spi_interface_radiant/spi_interface.sv

@@ -5,6 +5,41 @@
     Soft IP Version: 1.0.0
     2022 05 31 12:27:15
 *******************************************************************************/
+
+/*******************************************************************************
+    SPI Interface Ports
+    trying to follow instructions from:
+    https://www.chipverify.com/systemverilog/systemverilog-interface
+*******************************************************************************/
+interface spi_interface_ports (input clk);
+// Connection to BUS side (internal)
+  // Inputs from BUS
+  logic sb_clk_i;			// Clock
+  logic sb_stb_i;			// Chip Select from FRAM-Controller who is SPI-Master
+  logic sb_wr_i;			// Write/Read from FRAM-Controller
+  logic sb_adr_i[7:0];		// Adddress from FRAM-Controller
+  logic sb_dat_i[7:0];		// Data in from FRAM-Controller
+  // Outputs to BUS
+  logic sb_dat_o[7:0];		// Data out to FRAM-Controller
+  logic sb_ack_o;			// ACK to FRAM-Controller
+  
+// Connection to SPI side (external)
+  logic spi1_mosi_io;		// MasterOutSlaveIn --> Master to Slave
+  logic spi1_miso_io;		// MasterInSlaveOut --> Slave to Master
+  logic spi1_mcs_n_o[3:0];	// MasterChipSelect --> Master selects Slave
+  logic spi1_sck_io;		// Clock for SPI-Slave
+  
+  // MODPORT form BUS perspective (internal)
+  // modport input and output from BUS (internal)
+  modport BUS (output sb_clk_i, sb_stb_i, sb_wr_i, sb_adr_i, sb_dat_i, spi1_miso_io, input sb_dat_o, sb_ack_o, spi1_mosi_io, spi1_mcs_n_o, spi1_sck_io);
+  
+  // MODPORT from SPI perspective (external)
+  // modport input and output from SPI (external)
+  modport SPI (output spi1_miso_io, input spi1_mosi_io, spi1_mcs_n_o, spi1_sck_io);
+
+endinterface
+
+
 /*******************************************************************************
     Wrapper Module generated per user settings.
 *******************************************************************************/

timer_port/testbench.sv

@@ -0,0 +1,87 @@
+// Code your testbench here
+// or browse Examples
+
+
+`timescale 1ns/1ps;
+module tb();
+  reg inClk, inEN, inTaste;
+  wire outReadTemp;
+  wire outTasteAktiv;
+
+  reg [7:0] inData;
+  reg inEndOfConv;
+  wire outDataValid;
+  wire [7:0] outData;
+  
+  
+  
+  timer t1 (.inClk(inClk),
+			.inTaste(inTaste),
+			.inEN(inEN),
+            .outReadTemp(outReadTemp),
+			.outTasteAktiv(outTasteAktiv));
+			
+			
+  parallelport p1 (.inData(inData),
+					.inClk(inClk),
+					.inTimerMeas(outReadTemp),
+					.inEndOfConv(inEndOfConv), 
+					.outDataValid(outDataValid), 
+					.outData(outData));
+            
+           
+  always #83 inClk <= ~inClk;
+  always #1000000000 inEndOfConv <= ~inEndOfConv;
+  always #100000000 inData = inData +1;
+  
+  initial begin
+    //$dumpfile("dump.vcd");
+    //$dumpvars;
+    inClk <= 0;
+	inEN <= 0;
+	inTaste <= 0;
+
+	inData <= 8'b0;
+	inEndOfConv <= 0;
+	#1000000000
+	inTaste = 1;
+	#1000000000
+	#1000000000
+	#1000000000
+	inTaste = 0;
+	#1000000000
+	inEN <= 1;
+	#1000000000
+	inEN <= 0;
+	#1000000000
+	
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	#1000000000
+	$stop;
+  end
+endmodule

timer_port/timer_top.sv

@@ -0,0 +1,98 @@
+/*Timer soll signalisieren, wenn 10 Sekunden vorbei sind. 
+Zusätzlich soll der Taster abgefragt werden. Wenn der Taster für 1 Sekunde aktiv ist, soll es signalisiert werden.
+
+inClk: Eingang für Clock 12MHz
+inTaste: Eingang Taster
+inEN: Enable Pin, wenn HIGH dann stoppt Timer
+outReadTemp: signalisiert, dass 10 Sekunden vorbei sind
+outTasteAktiv: signalisiert, dass der Taster betätigt wurde
+*/
+
+
+module timer(input inClk, inTaste, inEN, output reg outReadTemp, outTasteAktiv);
+  //Wird genutzt um den Eingangstakt zu teilen.
+  int divide1 = 30000000;	
+  int divide2 = 60000;		
+  
+  //Interne Zwischenspeicher; 
+  logic 			state = 0;
+  logic [31:0] 		count1 = 32'b0;
+  logic [31:0]		count2 = 32'b0;
+  
+  //Initialisierung
+  initial begin
+    outReadTemp = 0;
+	outTasteAktiv = 0;
+  end
+
+   always @(posedge inClk or posedge inEN) begin
+	//Bei positiver Flanke und inEN auf HIGH wird Timer gestoppt
+	   if(inEN) begin
+      count1 <= 0;
+	  count2 <= 0;
+	  outReadTemp <= 0;
+	   end
+	//sonst wird counter1 inkrementiert
+	else begin
+      count1 <= count1 +1;
+     if(count1>=((2**32)-1))
+		count1 <= 32'b0;
+	//wenn counter1 durch divide1 teilbar ist, so wird outReadTemp getoggelt --> es erfolgt ca. alle 5 Sekunden ein toggeln
+	//outReadTemp ist für 5 Sekunden HIGH und 5 Sekunden LOW
+     if(count1 % divide1 == 0)
+       outReadTemp <= ~outReadTemp;
+
+	//Bei positiver Flanke wird Taster abgefragt
+	//Solange Taster HIGH ist wird counter2 erhöht	
+	if(inTaste) begin
+		count2 <= count2 +1;
+	//Sobald counter2 den Wert 6 000 000 übersteigt, wird outTasteAktiv auf HIGH gesetzt --> Taster wurde 1 Sekunde betätigt
+		if(count2 >= 6000000) 
+			outTasteAktiv = 1;
+		end
+	//Wenn Taster losgelassen wird, dann wird Ausgang und counter2 zurück gesetzt.
+		else begin
+			outTasteAktiv <= 0;
+			count2 <= 0;
+		end	
+		end
+	end
+endmodule // clk_divider
+
+
+/*Parallelport, soll die Daten des ADC alle 10 Sekunden auslesen und auf den Bus legen. 
+
+inClk: Eingang für Clock 12MHz
+inTimerMeas: Eingang des 10 Sekunden Takt des Timers
+inEndOdConv: Eingang vom ADC; Signalisiert valide Daten im ADC
+[7:0] inData: Eingang der Daten (parallel)
+outDataValid: Signalisiert, dass Daten auf Bus vaild sind
+[7:0] outData: Ausgang der Daten (parallel)
+*/
+
+module parallelport(input inClk, inTimerMeas, inEndOfConv, [7:0] inData, output reg outDataValid, [7:0] outData);
+
+	//Zwischenspeicher der Daten
+	logic [7:0] 		storage = 8'b0;
+	
+	//Initalisierung
+	initial begin
+		outDataValid <= 0;
+		outData <= 8'b0;
+		end
+		
+		always @(posedge inClk) begin
+			//Wenn inEndOfConv HIGH ist, dann werden die Daten in den Zwischenspeicher gelegt
+			if(inEndOfConv)
+				storage <= inData;
+			//Wenn inTimerMeas HIGH ist, dann werden die Daten aus dem Zwischenspeicher in das Ausgangsregister gelegt
+			//Außerdem wird outDataValid auf HIGH gesetzt, was dem Bus signalisiert, dass die Daten gelesen werden können
+			if(inTimerMeas == 1 && outDataValid == 0) begin
+				outData = storage;
+				outDataValid <= 1;
+			end
+			//Wenn inTimerMeas LOW ist, dann wird outDataValid auf LOW gesetzt
+			else if(inTimerMeas == 0)
+				outDataValid <= 0;
+		end	
+endmodule