100 changed files with 5725 additions and 3143 deletions
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc
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| @@ -1,4 +1,4 @@ | |||
| version:1 | |||
| 57656254616c6b5472616e736d697373696f6e417474656d70746564:13 | |||
| 6d6f64655f636f756e7465727c4755494d6f6465:23 | |||
| 6d6f64655f636f756e7465727c4755494d6f6465:25 | |||
| eof: | |||
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml
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| @@ -1,14 +1,11 @@ | |||
| <?xml version="1.0" encoding="UTF-8"?> | |||
| <GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1652439174" LaunchIncrCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp"> | |||
| <File Type="PA-TCL" Name="regler.tcl"/> | |||
| <File Type="RDS-PROPCONSTRS" Name="regler_drc_synth.rpt"/> | |||
| <File Type="REPORTS-TCL" Name="regler_reports.tcl"/> | |||
| <File Type="RDS-RDS" Name="regler.vds"/> | |||
| <File Type="RDS-UTIL" Name="regler_utilization_synth.rpt"/> | |||
| <File Type="RDS-UTIL-PB" Name="regler_utilization_synth.pb"/> | |||
| <File Type="RDS-DCP" Name="regler.dcp"/> | |||
| <File Type="VDS-TIMINGSUMMARY" Name="regler_timing_summary_synth.rpt"/> | |||
| <File Type="VDS-TIMING-PB" Name="regler_timing_summary_synth.pb"/> | |||
| <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> | |||
| <Filter Type="Srcs"/> | |||
| <File Path="$PSRCDIR/sources_1/new/pwm_test.vhd"> | |||
+ 1
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat
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| @@ -6,7 +6,7 @@ REM Filename : compile.bat | |||
| REM Simulator : Xilinx Vivado Simulator | |||
| REM Description : Script for compiling the simulation design source files | |||
| REM | |||
| REM Generated by Vivado on Fri May 13 12:56:52 +0200 2022 | |||
| REM Generated by Vivado on Fri May 13 13:48:21 +0200 2022 | |||
| REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| REM | |||
| REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
+ 0
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log
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| @@ -1,2 +0,0 @@ | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
+ 1
- 1
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat
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| @@ -6,7 +6,7 @@ REM Filename : elaborate.bat | |||
| REM Simulator : Xilinx Vivado Simulator | |||
| REM Description : Script for elaborating the compiled design | |||
| REM | |||
| REM Generated by Vivado on Fri May 13 12:56:53 +0200 2022 | |||
| REM Generated by Vivado on Fri May 13 13:48:23 +0200 2022 | |||
| REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| REM | |||
| REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
+ 1
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log
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| @@ -8,17 +8,4 @@ WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
BIN
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb
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BIN
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb
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+ 1
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini
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| @@ -28,7 +28,7 @@ VARIABLE_PROTOINST_FILTER=true | |||
| SCOPE_NAME_COLUMN_WIDTH=157 | |||
| SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 | |||
| SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 | |||
| OBJECT_NAME_COLUMN_WIDTH=75 | |||
| OBJECT_NAME_COLUMN_WIDTH=156 | |||
| OBJECT_VALUE_COLUMN_WIDTH=75 | |||
| OBJECT_DATA_TYPE_COLUMN_WIDTH=75 | |||
| PROCESS_NAME_COLUMN_WIDTH=75 | |||
+ 3
- 0
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log
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| @@ -2,3 +2,6 @@ Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_beha | |||
| Design successfully loaded | |||
| Design Loading Memory Usage: 7256 KB (Peak: 7256 KB) | |||
| Design Loading CPU Usage: 15 ms | |||
| Simulation completed | |||
| Simulation Memory Usage: 7792 KB (Peak: 7792 KB) | |||
| Simulation CPU Usage: 15 ms | |||
BIN
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb
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+ 1
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
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| @@ -2,7 +2,7 @@ | |||
| 2020.2 | |||
| Oct 19 2021 | |||
| 03:16:22 | |||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652439407,vhdl2008,,,,pwm_test_db,,,,,,,, | |||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652442389,vhdl,,,,pwm_test_db,,,,,,,, | |||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1651498208,vhdl,,,,pt1,,,,,,,, | |||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1652437038,vhdl,,,,regler,,,,,,,, | |||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd,1652437027,vhdl,,,,wendetangente,,,,,,,, | |||
+ 0
- 2
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log
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| @@ -1,2 +0,0 @@ | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
BIN
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb
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+ 1
- 1
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
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| @@ -116,7 +116,7 @@ begin | |||
| cnt <= cnt+1; | |||
| risingEdge <= '1'; | |||
| clk_100 <= '0'; | |||
| a <= a + to_sfixed(1.111, 7, -6); | |||
| --a <= a + to_sfixed(1.111, 7, -6); | |||
| end if; | |||
| if clk = '0' then | |||
+ 2
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
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| @@ -56,7 +56,7 @@ | |||
| <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> | |||
| <Option Name="EnableBDX" Val="FALSE"/> | |||
| <Option Name="DSABoardId" Val="zybo-z7-10"/> | |||
| <Option Name="WTXSimLaunchSim" Val="116"/> | |||
| <Option Name="WTXSimLaunchSim" Val="119"/> | |||
| <Option Name="WTModelSimLaunchSim" Val="0"/> | |||
| <Option Name="WTQuestaLaunchSim" Val="0"/> | |||
| <Option Name="WTIesLaunchSim" Val="0"/> | |||
| @@ -177,7 +177,7 @@ | |||
| <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> | |||
| <Filter Type="Srcs"/> | |||
| <File Path="$PSRCDIR/sim_1/new/pwm_test_db.vhd"> | |||
| <FileInfo SFType="VHDL2008"> | |||
| <FileInfo> | |||
| <Attr Name="UsedIn" Val="synthesis"/> | |||
| <Attr Name="UsedIn" Val="simulation"/> | |||
| </FileInfo> | |||
+ 3
- 67
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
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| @@ -2,10 +2,10 @@ | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 11:33:33 2022 | |||
| # Process ID: 5492 | |||
| # Start of session at: Fri May 13 14:02:42 2022 | |||
| # Process ID: 17732 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18808 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| @@ -13,67 +13,3 @@ | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| update_compile_order -fileset sources_1 | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_runs impl_1 -jobs 6 | |||
| wait_on_run impl_1 | |||
| close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ] | |||
| add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| update_compile_order -fileset sources_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl} | |||
| update_compile_order -fileset sources_1 | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_runs impl_1 -jobs 6 | |||
| wait_on_run impl_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_simulation | |||
| launch_simulation | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/a}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/b}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/c}} | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55 | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| close_sim | |||
| launch_simulation | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
+ 4
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
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| @@ -2,10 +2,10 @@ | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 11:33:33 2022 | |||
| # Process ID: 5492 | |||
| # Start of session at: Fri May 13 14:02:42 2022 | |||
| # Process ID: 17732 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18808 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| @@ -66,710 +66,5 @@ Finished scanning sources | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| open_project: Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| open_project: Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.184 ; gain = 0.000 | |||
| update_compile_order -fileset sources_1 | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 11:34:46 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_runs impl_1 -jobs 6 | |||
| [Fri May 13 11:36:03 2022] Launched impl_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log | |||
| close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ] | |||
| add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| update_compile_order -fileset sources_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>... | |||
| INFO: [Common 17-41] Interrupt caught. Command should exit soon. | |||
| INFO: [Common 17-344] 'source' was cancelled | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| INFO: [BD 41-1808] Open Block Design has been cancelled. | |||
| INFO: [Common 17-344] 'open_bd_design' was cancelled | |||
| import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl} | |||
| update_compile_order -fileset sources_1 | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:17:21 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_runs impl_1 -jobs 6 | |||
| [Fri May 13 12:18:35 2022] Launched impl_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>... | |||
| Successfully read diagram <design_1> from block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd> | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:28:24 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pt1' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'regler' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'wendeTangente' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
| Printing stacktrace... | |||
| [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe] | |||
| [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d] | |||
| [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc] | |||
| [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132] | |||
| [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda] | |||
| [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff914b26443] | |||
| [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff914b29088] | |||
| [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be] | |||
| [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132] | |||
| [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105] | |||
| [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0] | |||
| [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29] | |||
| [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5] | |||
| [13] [0x7ff65f3a24cf] | |||
| [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457] | |||
| [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce] | |||
| [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c] | |||
| [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0] | |||
| Done | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' | |||
| ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
| Printing stacktrace... | |||
| [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe] | |||
| [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d] | |||
| [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc] | |||
| [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132] | |||
| [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda] | |||
| [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff9180a6443] | |||
| [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff9180a9088] | |||
| [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be] | |||
| [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132] | |||
| [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105] | |||
| [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0] | |||
| [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29] | |||
| [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5] | |||
| [13] [0x7ff65f3a24cf] | |||
| [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457] | |||
| [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce] | |||
| [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c] | |||
| [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0] | |||
| Done | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' | |||
| ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| pwm_test_db_func_synth.wcfg | |||
| add_wave {{/pwm_test_db/uutWendeTangente/a}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| pwm_test_db_func_synth.wcfg | |||
| add_wave {{/pwm_test_db/uutWendeTangente/b}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| pwm_test_db_func_synth.wcfg | |||
| add_wave {{/pwm_test_db/uutWendeTangente/c}} | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55 | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| WARNING: [Vivado 12-1017] Problems encountered: | |||
| 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:52:54 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:46] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:53] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:65] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:66] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:72] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:83] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:90] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:102] | |||
| ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:116] | |||
| ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:117] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114] | |||
| ERROR: [VRFC 10-2123] 0 definitions of operator "and" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114] | |||
| ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:122] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121] | |||
| ERROR: [VRFC 10-2123] 0 definitions of operator "??" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121] | |||
| ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:126] | |||
| ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:43] | |||
| INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd' ignored due to errors | |||
| INFO: [USF-XSim-69] 'compile' step finished in '3' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' | |||
| ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
+ 0
- 14
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.jou
View File
| @@ -1,14 +0,0 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Wed May 4 17:41:44 2022 | |||
| # Process ID: 17388 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22812 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #-----------------------------------------------------------sstart_guiopen_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| update_compile_order -fileset sources_1 | |||
+ 16
- 0
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_19540.backup.jou
View File
| @@ -0,0 +1,16 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 13:47:22 2022 | |||
| # Process ID: 19540 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent17020 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| update_compile_order -fileset sources_1 | |||
| launch_simulation | |||
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.log → StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_19540.backup.log
View File
| @@ -2,21 +2,24 @@ | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Wed May 4 17:41:44 2022 | |||
| # Process ID: 17388 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22812 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Start of session at: Fri May 13 13:47:22 2022 | |||
| # Process ID: 19540 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent17020 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #-----------------------------------------------------------sstart_guiopen_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. | |||
| Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' | |||
| WWARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available | |||
| @@ -56,12 +59,71 @@ WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 avai | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not availableIINFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim' since last save.INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. | |||
| IINFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.Scanning sources... | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available | |||
| INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. | |||
| Scanning sources... | |||
| Finished scanning sources | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| IINFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.open_project: Time (s): cpu = 00:00:36 ; elapsed = 00:00:19 . Memory (MB): peak = 1250.172 ; gain = 0.000 | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| open_project: Time (s): cpu = 00:00:35 ; elapsed = 00:00:15 . Memory (MB): peak = 1251.859 ; gain = 0.000 | |||
| update_compile_order -fileset sources_1 | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
| Printing stacktrace... | |||
| [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe] | |||
| [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d] | |||
| [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc] | |||
| [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132] | |||
| [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda] | |||
| [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff90fea6443] | |||
| [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff90fea9088] | |||
| [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be] | |||
| [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132] | |||
| [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105] | |||
| [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0] | |||
| [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29] | |||
| [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5] | |||
| [13] [0x7ff65f3a24cf] | |||
| [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457] | |||
| [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce] | |||
| [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c] | |||
| [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0] | |||
| Done | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' | |||
| ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| exit | |||
| INFO: [Common 17-206] Exiting Vivado at Wed May 4 17:58:54 2022... | |||
| INFO: [Common 17-206] Exiting Vivado at Fri May 13 13:50:06 2022... | |||
+ 0
- 43
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.jou
View File
| @@ -1,43 +0,0 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Mon May 2 13:48:39 2022 | |||
| # Process ID: 3460 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9928 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| update_compile_order -fileset sources_1 | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 61 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 61 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| close_sim | |||
+ 0
- 295
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.log
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| @@ -1,295 +0,0 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Mon May 2 13:48:39 2022 | |||
| # Process ID: 3460 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9928 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. | |||
| Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim' | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available | |||
| INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. | |||
| INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. | |||
| Scanning sources... | |||
| Finished scanning sources | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| open_project: Time (s): cpu = 00:00:31 ; elapsed = 00:00:12 . Memory (MB): peak = 1254.516 ; gain = 0.000 | |||
| update_compile_order -fileset sources_1 | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pt1' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'regler' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1271.582 ; gain = 17.066 | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| WARNING: [Vivado 12-1017] Problems encountered: | |||
| 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| [Mon May 2 13:54:34 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 61 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 61 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| WARNING: [Vivado 12-1017] Problems encountered: | |||
| 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| [Mon May 2 14:46:17 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'regler' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| WARNING: [Simulator 45-24] Previous breakpoint at line 62 in file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd' not restored because it is no longer a breakable line. | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1271.582 ; gain = 0.000 | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| WARNING: [Vivado 12-1017] Problems encountered: | |||
| 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| [Mon May 2 14:59:49 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pt1' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'regler' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1271.582 ; gain = 0.000 | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| exit | |||
| INFO: [Common 17-206] Exiting Vivado at Mon May 2 15:30:20 2022... | |||
+ 83
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| @@ -0,0 +1,83 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 11:33:33 2022 | |||
| # Process ID: 5492 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| update_compile_order -fileset sources_1 | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_runs impl_1 -jobs 6 | |||
| wait_on_run impl_1 | |||
| close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ] | |||
| add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| update_compile_order -fileset sources_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl} | |||
| update_compile_order -fileset sources_1 | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_runs impl_1 -jobs 6 | |||
| wait_on_run impl_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_simulation | |||
| launch_simulation | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/a}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/b}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/c}} | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55 | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| close_sim | |||
| launch_simulation | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| set_property file_type VHDL [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] | |||
| close_sim | |||
| launch_simulation | |||
| launch_simulation | |||
+ 900
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_5492.backup.log
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| @@ -0,0 +1,900 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 11:33:33 2022 | |||
| # Process ID: 5492 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. | |||
| Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available | |||
| INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. | |||
| INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. | |||
| Scanning sources... | |||
| Finished scanning sources | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| open_project: Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| update_compile_order -fileset sources_1 | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 11:34:46 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_runs impl_1 -jobs 6 | |||
| [Fri May 13 11:36:03 2022] Launched impl_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log | |||
| close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ] | |||
| add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| update_compile_order -fileset sources_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>... | |||
| INFO: [Common 17-41] Interrupt caught. Command should exit soon. | |||
| INFO: [Common 17-344] 'source' was cancelled | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| INFO: [BD 41-1808] Open Block Design has been cancelled. | |||
| INFO: [Common 17-344] 'open_bd_design' was cancelled | |||
| import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl} | |||
| update_compile_order -fileset sources_1 | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:17:21 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_runs impl_1 -jobs 6 | |||
| [Fri May 13 12:18:35 2022] Launched impl_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>... | |||
| Successfully read diagram <design_1> from block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd> | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:28:24 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pt1' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'regler' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'wendeTangente' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
| Printing stacktrace... | |||
| [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe] | |||
| [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d] | |||
| [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc] | |||
| [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132] | |||
| [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda] | |||
| [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff914b26443] | |||
| [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff914b29088] | |||
| [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be] | |||
| [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132] | |||
| [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105] | |||
| [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0] | |||
| [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29] | |||
| [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5] | |||
| [13] [0x7ff65f3a24cf] | |||
| [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457] | |||
| [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce] | |||
| [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c] | |||
| [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0] | |||
| Done | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' | |||
| ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
| Printing stacktrace... | |||
| [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe] | |||
| [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d] | |||
| [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc] | |||
| [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132] | |||
| [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda] | |||
| [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff9180a6443] | |||
| [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff9180a9088] | |||
| [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be] | |||
| [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132] | |||
| [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105] | |||
| [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0] | |||
| [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29] | |||
| [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5] | |||
| [13] [0x7ff65f3a24cf] | |||
| [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457] | |||
| [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce] | |||
| [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c] | |||
| [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0] | |||
| Done | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' | |||
| ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| pwm_test_db_func_synth.wcfg | |||
| add_wave {{/pwm_test_db/uutWendeTangente/a}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| pwm_test_db_func_synth.wcfg | |||
| add_wave {{/pwm_test_db/uutWendeTangente/b}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| pwm_test_db_func_synth.wcfg | |||
| add_wave {{/pwm_test_db/uutWendeTangente/c}} | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55 | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| WARNING: [Vivado 12-1017] Problems encountered: | |||
| 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:52:54 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:46] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:53] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:65] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:66] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:72] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:83] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:90] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:102] | |||
| ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:116] | |||
| ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:117] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114] | |||
| ERROR: [VRFC 10-2123] 0 definitions of operator "and" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114] | |||
| ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:122] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121] | |||
| ERROR: [VRFC 10-2123] 0 definitions of operator "??" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121] | |||
| ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:126] | |||
| ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:43] | |||
| INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd' ignored due to errors | |||
| INFO: [USF-XSim-69] 'compile' step finished in '3' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' | |||
| ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| set_property file_type VHDL [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
| Printing stacktrace... | |||
| [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe] | |||
| [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d] | |||
| [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc] | |||
| [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132] | |||
| [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda] | |||
| [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff9830a6443] | |||
| [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff9830a9088] | |||
| [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be] | |||
| [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132] | |||
| [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105] | |||
| [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0] | |||
| [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29] | |||
| [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5] | |||
| [13] [0x7ff65f3a24cf] | |||
| [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457] | |||
| [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce] | |||
| [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c] | |||
| [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0] | |||
| Done | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' | |||
| ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
| Printing stacktrace... | |||
| [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe] | |||
| [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d] | |||
| [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc] | |||
| [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132] | |||
| [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda] | |||
| [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff90fad6443] | |||
| [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff90fad9088] | |||
| [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be] | |||
| [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132] | |||
| [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105] | |||
| [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0] | |||
| [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29] | |||
| [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5] | |||
| [13] [0x7ff65f3a24cf] | |||
| [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457] | |||
| [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce] | |||
| [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c] | |||
| [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0] | |||
| Done | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' | |||
| ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| exit | |||
| INFO: [Common 17-206] Exiting Vivado at Fri May 13 13:47:14 2022... | |||
+ 154
- 0
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid17732.str
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| @@ -0,0 +1,154 @@ | |||
| /* | |||
| Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2] | |||
| SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| Process ID (PID): 17732 | |||
| License: Customer | |||
| Mode: GUI Mode | |||
| Current time: Fri May 13 14:02:56 CEST 2022 | |||
| Time zone: Central European Standard Time (Europe/Berlin) | |||
| OS: Windows 10 | |||
| OS Version: 10.0 | |||
| OS Architecture: amd64 | |||
| Available processors (cores): 12 | |||
| Screen size: 1920x1080 | |||
| Screen resolution (DPI): 100 | |||
| Available screens: 2 | |||
| Default font: family=Dialog,name=Dialog,style=plain,size=12 | |||
| Scale size: 12 | |||
| Java version: 11.0.11 64-bit | |||
| Java home: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9 | |||
| Java executable: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe | |||
| Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m] | |||
| Java initial memory (-Xms): 256 MB | |||
| Java maximum memory (-Xmx): 3 GB | |||
| User name: Felix | |||
| User home directory: C:/Users/Felix | |||
| User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| User country: DE | |||
| User language: de | |||
| User locale: de_DE | |||
| RDI_BASEROOT: C:/Xilinx/Vivado | |||
| HDI_APPROOT: C:/Xilinx/Vivado/2021.2 | |||
| RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data | |||
| RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin | |||
| Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml | |||
| Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/ | |||
| Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts | |||
| PlanAhead jar file: C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar | |||
| Vivado log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| Vivado journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou | |||
| Engine tmp dir: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-17732-DESKTOP-PAACOM8 | |||
| Xilinx Environment Variables | |||
| ---------------------------- | |||
| TWINCATSDK: C:\TwinCAT\3.1\SDK\ | |||
| XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE | |||
| XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE | |||
| XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2 | |||
| XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2 | |||
| XILINX_VIVADO: C:/Xilinx/Vivado/2021.2 | |||
| XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2 | |||
| GUI allocated memory: 342 MB | |||
| GUI max memory: 3,072 MB | |||
| Engine allocated memory: 1,325 MB | |||
| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| */ | |||
| // TclEventType: START_GUI | |||
| // Tcl Message: start_gui | |||
| // TclEventType: PROJECT_OPEN_DIALOG | |||
| // Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 | |||
| // TclEventType: DEBUG_PROBE_SET_CHANGE | |||
| // TclEventType: FLOW_ADDED | |||
| // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' | |||
| // HMemoryUtils.trashcanNow. Engine heap size: 1,325 MB. GUI used memory: 56 MB. Current time: 5/13/22, 2:02:57 PM CEST | |||
| // TclEventType: MSGMGR_MOVEMSG | |||
| // TclEventType: FILE_SET_CHANGE | |||
| // TclEventType: FILE_SET_NEW | |||
| // TclEventType: RUN_COMPLETED | |||
| // TclEventType: RUN_STATUS_CHANGE | |||
| // TclEventType: RUN_CURRENT | |||
| // TclEventType: PROJECT_DASHBOARD_NEW | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_NEW | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_NEW | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_NEW | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_NEW | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_NEW | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_NEW | |||
| // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE | |||
| // TclEventType: PROJECT_NEW | |||
| // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' | |||
| // Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. | |||
| // Tcl Message: Scanning sources... Finished scanning sources | |||
| // TclEventType: PROJECT_NEW | |||
| // [GUI Memory]: 77 MB (+78665kb) [00:00:15] | |||
| // [Engine Memory]: 1,325 MB (+1237477kb) [00:00:15] | |||
| // WARNING: HEventQueue.dispatchEvent() is taking 3112 ms. | |||
| // Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| // [GUI Memory]: 102 MB (+21713kb) [00:00:18] | |||
| // Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1 | |||
| // Tcl Message: open_project: Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.184 ; gain = 0.000 | |||
| dismissDialog("Open Project"); // bA | |||
| // Tcl Message: update_compile_order -fileset sources_1 | |||
| // PAPropertyPanels.initPanels (pwm_test.vhd) elapsed time: 0.2s | |||
| // Elapsed time: 11 seconds | |||
| selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false); // D | |||
| selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false, false, false, false, false, true); // D - Double Click | |||
| // WARNING: HEventQueue.dispatchEvent() is taking 1801 ms. | |||
| // [GUI Memory]: 134 MB (+27930kb) [00:00:32] | |||
| selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false); // D | |||
| selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false, false, false, false, false, true); // D - Double Click | |||
| // WARNING: HEventQueue.dispatchEvent() is taking 1441 ms. | |||
| // Elapsed time: 10 seconds | |||
| selectCodeEditor("pt1.vhd", 88, 451); // be | |||
| selectCodeEditor("pt1.vhd", 11, 348, false, false, false, true, false); // be - Popup Trigger | |||
| selectMenuItem(RDIResourceCommand.RDICommands_COPY, "Copy"); // ao | |||
| // Elapsed time: 24 seconds | |||
| selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false); // D | |||
| selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false, false, false, false, false, true); // D - Double Click | |||
| // WARNING: HEventQueue.dispatchEvent() is taking 1130 ms. | |||
| dismissDialog("Opening Editor"); // bA | |||
| selectCodeEditor("wendeTangente.vhd", 126, 259); // be | |||
| typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be | |||
| // Elapsed time: 82 seconds | |||
| expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 7); // D | |||
| expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 8); // D | |||
| selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 10, true); // D - Node | |||
| selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd), uut_regler : regler(Behavioral) (pwm_test.vhd)]", 11, false, false, false, false, false, true); // D - Double Click | |||
| // WARNING: HEventQueue.dispatchEvent() is taking 1115 ms. | |||
| // [GUI Memory]: 145 MB (+4836kb) [00:02:44] | |||
| dismissDialog("Opening Editor"); // bA | |||
| selectCodeEditor("pwm_test_db.vhd", 149, 169); // be | |||
| typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be | |||
| // Elapsed time: 45 seconds | |||
| selectCodeEditor("pwm_test_db.vhd", 251, 110); // be | |||
| typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be | |||
| selectCodeEditor("pwm_test_db.vhd", 83, 268); // be | |||
| typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be | |||
| // Elapsed time: 50 seconds | |||
| selectCodeEditor("pwm_test_db.vhd", 217, 345); // be | |||
| // Elapsed time: 732 seconds | |||
| selectCodeEditor("pwm_test_db.vhd", 229, 347); // be | |||
| // HMemoryUtils.trashcanNow. Engine heap size: 1,325 MB. GUI used memory: 81 MB. Current time: 5/13/22, 2:32:57 PM CEST | |||
+ 0
- 1973
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid5492.str
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| @@ -0,0 +1,10 @@ | |||
| ################################################################################ | |||
| # DONOT REMOVE THIS FILE | |||
| # Unified simulation database file for selected simulation model for IP | |||
| # | |||
| # File: ssm.db (Fri May 13 14:10:49 2022) | |||
| # | |||
| # This file is generated by the unified simulation automation and contains the | |||
| # selected simulation model information for the IP/BD instances. | |||
| # DONOT REMOVE THIS FILE | |||
| ################################################################################ | |||
+ 3
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| @@ -0,0 +1,3 @@ | |||
| version:1 | |||
| 6d6f64655f636f756e7465727c4755494d6f6465:1 | |||
| eof: | |||
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| @@ -0,0 +1,44 @@ | |||
| version:1 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303130636c673430302d31:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6669786564506f696e7454657374:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646676:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | |||
| 73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333273:00:00 | |||
| 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313236312e3035354d42:00:00 | |||
| 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:302e3030304d42:00:00 | |||
| eof:738664726 | |||
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| version:1 | |||
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| eof:2511430288 | |||
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| <?xml version="1.0" encoding="UTF-8" ?> | |||
| <document> | |||
| <!--The data in this file is primarily intended for consumption by Xilinx tools. | |||
| The structure and the elements are likely to change over the next few releases. | |||
| This means code written to parse this file will need to be revisited each subsequent release.--> | |||
| <application name="pa" timeStamp="Fri May 13 14:42:26 2022"> | |||
| <section name="Project Information" visible="false"> | |||
| <property name="ProjectID" value="7a8e7c8ef7e84daa83c28bbcb851b3c5" type="ProjectID"/> | |||
| <property name="ProjectIteration" value="5" type="ProjectIteration"/> | |||
| </section> | |||
| <section name="PlanAhead Usage" visible="true"> | |||
| <item name="Project Data"> | |||
| <property name="SrcSetCount" value="1" type="SrcSetCount"/> | |||
| <property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/> | |||
| <property name="DesignMode" value="RTL" type="DesignMode"/> | |||
| <property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/> | |||
| <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> | |||
| </item> | |||
| </section> | |||
| </application> | |||
| </document> | |||
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| version:1 | |||
| 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 | |||
| 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 | |||
| eof:241934075 | |||
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| <?xml version="1.0" encoding="UTF-8"?> | |||
| <!-- Product Version: Vivado v2021.2 (64-bit) --> | |||
| <!-- --> | |||
| <!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. --> | |||
| <labtools version="1" minor="0"/> | |||
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| The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. | |||
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| <?xml version="1.0"?> | |||
| <Runs Version="1" Minor="0"> | |||
| <Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> | |||
| <Parameters> | |||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||
| </Parameters> | |||
| </Runs> | |||
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StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_2.xml
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| <?xml version="1.0"?> | |||
| <Runs Version="1" Minor="0"> | |||
| <Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> | |||
| <Parameters> | |||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||
| </Parameters> | |||
| </Runs> | |||
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StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_3.xml
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| <?xml version="1.0"?> | |||
| <Runs Version="1" Minor="0"> | |||
| <Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> | |||
| <Parameters> | |||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||
| </Parameters> | |||
| </Runs> | |||
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| <?xml version="1.0"?> | |||
| <Runs Version="1" Minor="0"> | |||
| <Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/> | |||
| <Parameters> | |||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||
| </Parameters> | |||
| </Runs> | |||
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| @@ -0,0 +1,9 @@ | |||
| <?xml version="1.0"?> | |||
| <Runs Version="1" Minor="0"> | |||
| <Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/> | |||
| <Parameters> | |||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||
| </Parameters> | |||
| </Runs> | |||
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| @@ -0,0 +1,12 @@ | |||
| <?xml version="1.0"?> | |||
| <Runs Version="1" Minor="0"> | |||
| <Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> | |||
| <Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"> | |||
| <Parent Id="synth_1"/> | |||
| </Run> | |||
| <Parameters> | |||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||
| </Parameters> | |||
| </Runs> | |||
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| @@ -0,0 +1,9 @@ | |||
| <?xml version="1.0"?> | |||
| <Runs Version="1" Minor="0"> | |||
| <Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/> | |||
| <Parameters> | |||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||
| </Parameters> | |||
| </Runs> | |||
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StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/.jobs/vrs_config_8.xml
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| @@ -0,0 +1,9 @@ | |||
| <?xml version="1.0"?> | |||
| <Runs Version="1" Minor="0"> | |||
| <Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/> | |||
| <Parameters> | |||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||
| </Parameters> | |||
| </Runs> | |||
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log → StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/.Vivado_Implementation.queue.rst
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| <?xml version="1.0"?> | |||
| <ProcessHandle Version="1" Minor="0"> | |||
| <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17108"> | |||
| </Process> | |||
| </ProcessHandle> | |||
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| <?xml version="1.0"?> | |||
| <ProcessHandle Version="1" Minor="0"> | |||
| <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17108"> | |||
| </Process> | |||
| </ProcessHandle> | |||
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| <?xml version="1.0"?> | |||
| <ProcessHandle Version="1" Minor="0"> | |||
| <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17108"> | |||
| </Process> | |||
| </ProcessHandle> | |||
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| <?xml version="1.0"?> | |||
| <ProcessHandle Version="1" Minor="0"> | |||
| <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17108"> | |||
| </Process> | |||
| </ProcessHandle> | |||
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| <?xml version="1.0"?> | |||
| <ProcessHandle Version="1" Minor="0"> | |||
| <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17108"> | |||
| </Process> | |||
| </ProcessHandle> | |||
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| <?xml version="1.0"?> | |||
| <ProcessHandle Version="1" Minor="0"> | |||
| <Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="13680" HostCore="12" HostMemory="016927088640"> | |||
| </Process> | |||
| </ProcessHandle> | |||
| <?xml version="1.0"?> | |||
| <ProcessHandle Version="1" Minor="0"> | |||
| <Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="17920" HostCore="12" HostMemory="016927088640"> | |||
| </Process> | |||
| </ProcessHandle> | |||
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| @@ -0,0 +1,5 @@ | |||
| <?xml version="1.0"?> | |||
| <ProcessHandle Version="1" Minor="0"> | |||
| <Process Command=".planAhead." Owner="Felix" Host="DESKTOP-PAACOM8" Pid="11092"> | |||
| </Process> | |||
| </ProcessHandle> | |||
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| // | |||
| // Vivado(TM) | |||
| // ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 | |||
| // Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. | |||
| // | |||
| // GLOBAL VARIABLES | |||
| var ISEShell = new ActiveXObject( "WScript.Shell" ); | |||
| var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); | |||
| var ISERunDir = ""; | |||
| var ISELogFile = "runme.log"; | |||
| var ISELogFileStr = null; | |||
| var ISELogEcho = true; | |||
| var ISEOldVersionWSH = false; | |||
| // BOOTSTRAP | |||
| ISEInit(); | |||
| // | |||
| // ISE FUNCTIONS | |||
| // | |||
| function ISEInit() { | |||
| // 1. RUN DIR setup | |||
| var ISEScrFP = WScript.ScriptFullName; | |||
| var ISEScrN = WScript.ScriptName; | |||
| ISERunDir = | |||
| ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); | |||
| // 2. LOG file setup | |||
| ISELogFileStr = ISEOpenFile( ISELogFile ); | |||
| // 3. LOG echo? | |||
| var ISEScriptArgs = WScript.Arguments; | |||
| for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) { | |||
| if ( ISEScriptArgs(loopi) == "-quiet" ) { | |||
| ISELogEcho = false; | |||
| break; | |||
| } | |||
| } | |||
| // 4. WSH version check | |||
| var ISEOptimalVersionWSH = 5.6; | |||
| var ISECurrentVersionWSH = WScript.Version; | |||
| if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) { | |||
| ISEStdErr( "" ); | |||
| ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " + | |||
| ISEOptimalVersionWSH + " or higher. Downloads" ); | |||
| ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " ); | |||
| ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" ); | |||
| ISEStdErr( "" ); | |||
| ISEOldVersionWSH = true; | |||
| } | |||
| } | |||
| function ISEStep( ISEProg, ISEArgs ) { | |||
| // CHECK for a STOP FILE | |||
| if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) { | |||
| ISEStdErr( "" ); | |||
| ISEStdErr( "*** Halting run - EA reset detected ***" ); | |||
| ISEStdErr( "" ); | |||
| WScript.Quit( 1 ); | |||
| } | |||
| // WRITE STEP HEADER to LOG | |||
| ISEStdOut( "" ); | |||
| ISEStdOut( "*** Running " + ISEProg ); | |||
| ISEStdOut( " with args " + ISEArgs ); | |||
| ISEStdOut( "" ); | |||
| // LAUNCH! | |||
| var ISEExitCode = ISEExec( ISEProg, ISEArgs ); | |||
| if ( ISEExitCode != 0 ) { | |||
| WScript.Quit( ISEExitCode ); | |||
| } | |||
| } | |||
| function ISEExec( ISEProg, ISEArgs ) { | |||
| var ISEStep = ISEProg; | |||
| if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") { | |||
| ISEProg += ".bat"; | |||
| } | |||
| var ISECmdLine = ISEProg + " " + ISEArgs; | |||
| var ISEExitCode = 1; | |||
| if ( ISEOldVersionWSH ) { // WSH 5.1 | |||
| // BEGIN file creation | |||
| ISETouchFile( ISEStep, "begin" ); | |||
| // LAUNCH! | |||
| ISELogFileStr.Close(); | |||
| ISECmdLine = | |||
| "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1"; | |||
| ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); | |||
| ISELogFileStr = ISEOpenFile( ISELogFile ); | |||
| } else { // WSH 5.6 | |||
| // LAUNCH! | |||
| ISEShell.CurrentDirectory = ISERunDir; | |||
| // Redirect STDERR to STDOUT | |||
| ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; | |||
| var ISEProcess = ISEShell.Exec( ISECmdLine ); | |||
| // BEGIN file creation | |||
| var wbemFlagReturnImmediately = 0x10; | |||
| var wbemFlagForwardOnly = 0x20; | |||
| var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); | |||
| var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); | |||
| var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); | |||
| var NOC = 0; | |||
| var NOLP = 0; | |||
| var TPM = 0; | |||
| var cpuInfos = new Enumerator(processor); | |||
| for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { | |||
| var cpuInfo = cpuInfos.item(); | |||
| NOC += cpuInfo.NumberOfCores; | |||
| NOLP += cpuInfo.NumberOfLogicalProcessors; | |||
| } | |||
| var csInfos = new Enumerator(computerSystem); | |||
| for(;!csInfos.atEnd(); csInfos.moveNext()) { | |||
| var csInfo = csInfos.item(); | |||
| TPM += csInfo.TotalPhysicalMemory; | |||
| } | |||
| var ISEHOSTCORE = NOLP | |||
| var ISEMEMTOTAL = TPM | |||
| var ISENetwork = WScript.CreateObject( "WScript.Network" ); | |||
| var ISEHost = ISENetwork.ComputerName; | |||
| var ISEUser = ISENetwork.UserName; | |||
| var ISEPid = ISEProcess.ProcessID; | |||
| var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); | |||
| ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" ); | |||
| ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" ); | |||
| ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg + | |||
| "\" Owner=\"" + ISEUser + | |||
| "\" Host=\"" + ISEHost + | |||
| "\" Pid=\"" + ISEPid + | |||
| "\" HostCore=\"" + ISEHOSTCORE + | |||
| "\" HostMemory=\"" + ISEMEMTOTAL + | |||
| "\">" ); | |||
| ISEBeginFile.WriteLine( " </Process>" ); | |||
| ISEBeginFile.WriteLine( "</ProcessHandle>" ); | |||
| ISEBeginFile.Close(); | |||
| var ISEOutStr = ISEProcess.StdOut; | |||
| var ISEErrStr = ISEProcess.StdErr; | |||
| // WAIT for ISEStep to finish | |||
| while ( ISEProcess.Status == 0 ) { | |||
| // dump stdout then stderr - feels a little arbitrary | |||
| while ( !ISEOutStr.AtEndOfStream ) { | |||
| ISEStdOut( ISEOutStr.ReadLine() ); | |||
| } | |||
| WScript.Sleep( 100 ); | |||
| } | |||
| ISEExitCode = ISEProcess.ExitCode; | |||
| } | |||
| ISELogFileStr.Close(); | |||
| // END/ERROR file creation | |||
| if ( ISEExitCode != 0 ) { | |||
| ISETouchFile( ISEStep, "error" ); | |||
| } else { | |||
| ISETouchFile( ISEStep, "end" ); | |||
| } | |||
| return ISEExitCode; | |||
| } | |||
| // | |||
| // UTILITIES | |||
| // | |||
| function ISEStdOut( ISELine ) { | |||
| ISELogFileStr.WriteLine( ISELine ); | |||
| if ( ISELogEcho ) { | |||
| WScript.StdOut.WriteLine( ISELine ); | |||
| } | |||
| } | |||
| function ISEStdErr( ISELine ) { | |||
| ISELogFileStr.WriteLine( ISELine ); | |||
| if ( ISELogEcho ) { | |||
| WScript.StdErr.WriteLine( ISELine ); | |||
| } | |||
| } | |||
| function ISETouchFile( ISERoot, ISEStatus ) { | |||
| var ISETFile = | |||
| ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); | |||
| ISETFile.Close(); | |||
| } | |||
| function ISEOpenFile( ISEFilename ) { | |||
| // This function has been updated to deal with a problem seen in CR #870871. | |||
| // In that case the user runs a script that runs impl_1, and then turns around | |||
| // and runs impl_1 -to_step write_bitstream. That second run takes place in | |||
| // the same directory, which means we may hit some of the same files, and in | |||
| // particular, we will open the runme.log file. Even though this script closes | |||
| // the file (now), we see cases where a subsequent attempt to open the file | |||
| // fails. Perhaps the OS is slow to release the lock, or the disk comes into | |||
| // play? In any case, we try to work around this by first waiting if the file | |||
| // is already there for an arbitrary 5 seconds. Then we use a try-catch block | |||
| // and try to open the file 10 times with a one second delay after each attempt. | |||
| // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. | |||
| // If there is an unrecognized exception when trying to open the file, we output | |||
| // an error message and write details to an exception.log file. | |||
| var ISEFullPath = ISERunDir + "/" + ISEFilename; | |||
| if (ISEFileSys.FileExists(ISEFullPath)) { | |||
| // File is already there. This could be a problem. Wait in case it is still in use. | |||
| WScript.Sleep(5000); | |||
| } | |||
| var i; | |||
| for (i = 0; i < 10; ++i) { | |||
| try { | |||
| return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); | |||
| } catch (exception) { | |||
| var error_code = exception.number & 0xFFFF; // The other bits are a facility code. | |||
| if (error_code == 52) { // 52 is bad file name or number. | |||
| // Wait a second and try again. | |||
| WScript.Sleep(1000); | |||
| continue; | |||
| } else { | |||
| WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); | |||
| var exceptionFilePath = ISERunDir + "/exception.log"; | |||
| if (!ISEFileSys.FileExists(exceptionFilePath)) { | |||
| WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); | |||
| var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); | |||
| exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); | |||
| exceptionFile.WriteLine("\tException name: " + exception.name); | |||
| exceptionFile.WriteLine("\tException error code: " + error_code); | |||
| exceptionFile.WriteLine("\tException message: " + exception.message); | |||
| exceptionFile.Close(); | |||
| } | |||
| throw exception; | |||
| } | |||
| } | |||
| } | |||
| // If we reached this point, we failed to open the file after 10 attempts. | |||
| // We need to error out. | |||
| WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); | |||
| WScript.Quit(1); | |||
| } | |||
+ 84
- 0
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/ISEWrap.sh
View File
| @@ -0,0 +1,84 @@ | |||
| #!/bin/sh | |||
| # | |||
| # Vivado(TM) | |||
| # ISEWrap.sh: Vivado Runs Script for UNIX | |||
| # Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. | |||
| # | |||
| cmd_exists() | |||
| { | |||
| command -v "$1" >/dev/null 2>&1 | |||
| } | |||
| HD_LOG=$1 | |||
| shift | |||
| # CHECK for a STOP FILE | |||
| if [ -f .stop.rst ] | |||
| then | |||
| echo "" >> $HD_LOG | |||
| echo "*** Halting run - EA reset detected ***" >> $HD_LOG | |||
| echo "" >> $HD_LOG | |||
| exit 1 | |||
| fi | |||
| ISE_STEP=$1 | |||
| shift | |||
| # WRITE STEP HEADER to LOG | |||
| echo "" >> $HD_LOG | |||
| echo "*** Running $ISE_STEP" >> $HD_LOG | |||
| echo " with args $@" >> $HD_LOG | |||
| echo "" >> $HD_LOG | |||
| # LAUNCH! | |||
| $ISE_STEP "$@" >> $HD_LOG 2>&1 & | |||
| # BEGIN file creation | |||
| ISE_PID=$! | |||
| HostNameFile=/proc/sys/kernel/hostname | |||
| if cmd_exists hostname | |||
| then | |||
| ISE_HOST=$(hostname) | |||
| elif cmd_exists uname | |||
| then | |||
| ISE_HOST=$(uname -n) | |||
| elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] | |||
| then | |||
| ISE_HOST=$(cat $HostNameFile) | |||
| elif [ X != X$HOSTNAME ] | |||
| then | |||
| ISE_HOST=$HOSTNAME #bash | |||
| else | |||
| ISE_HOST=$HOST #csh | |||
| fi | |||
| ISE_USER=$USER | |||
| ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) | |||
| ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) | |||
| ISE_BEGINFILE=.$ISE_STEP.begin.rst | |||
| /bin/touch $ISE_BEGINFILE | |||
| echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE | |||
| echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE | |||
| echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE | |||
| echo " </Process>" >> $ISE_BEGINFILE | |||
| echo "</ProcessHandle>" >> $ISE_BEGINFILE | |||
| # WAIT for ISEStep to finish | |||
| wait $ISE_PID | |||
| # END/ERROR file creation | |||
| RETVAL=$? | |||
| if [ $RETVAL -eq 0 ] | |||
| then | |||
| /bin/touch .$ISE_STEP.end.rst | |||
| else | |||
| /bin/touch .$ISE_STEP.error.rst | |||
| fi | |||
| exit $RETVAL | |||
+ 157
- 0
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.tcl
View File
| @@ -0,0 +1,157 @@ | |||
| # | |||
| # Report generation script generated by Vivado | |||
| # | |||
| proc create_report { reportName command } { | |||
| set status "." | |||
| append status $reportName ".fail" | |||
| if { [file exists $status] } { | |||
| eval file delete [glob $status] | |||
| } | |||
| send_msg_id runtcl-4 info "Executing : $command" | |||
| set retval [eval catch { $command } msg] | |||
| if { $retval != 0 } { | |||
| set fp [open $status w] | |||
| close $fp | |||
| send_msg_id runtcl-5 warning "$msg" | |||
| } | |||
| } | |||
| namespace eval ::optrace { | |||
| variable script "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.tcl" | |||
| variable category "vivado_impl" | |||
| } | |||
| # Try to connect to running dispatch if we haven't done so already. | |||
| # This code assumes that the Tcl interpreter is not using threads, | |||
| # since the ::dispatch::connected variable isn't mutex protected. | |||
| if {![info exists ::dispatch::connected]} { | |||
| namespace eval ::dispatch { | |||
| variable connected false | |||
| if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { | |||
| set result "true" | |||
| if {[catch { | |||
| if {[lsearch -exact [package names] DispatchTcl] < 0} { | |||
| set result [load librdi_cd_clienttcl[info sharedlibextension]] | |||
| } | |||
| if {$result eq "false"} { | |||
| puts "WARNING: Could not load dispatch client library" | |||
| } | |||
| set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] | |||
| if { $connect_id eq "" } { | |||
| puts "WARNING: Could not initialize dispatch client" | |||
| } else { | |||
| puts "INFO: Dispatch client connection id - $connect_id" | |||
| set connected true | |||
| } | |||
| } catch_res]} { | |||
| puts "WARNING: failed to connect to dispatch server - $catch_res" | |||
| } | |||
| } | |||
| } | |||
| } | |||
| if {$::dispatch::connected} { | |||
| # Remove the dummy proc if it exists. | |||
| if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { | |||
| rename ::OPTRACE "" | |||
| } | |||
| proc ::OPTRACE { task action {tags {} } } { | |||
| ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category | |||
| } | |||
| # dispatch is generic. We specifically want to attach logging. | |||
| ::vitis_log::connect_client | |||
| } else { | |||
| # Add dummy proc if it doesn't exist. | |||
| if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { | |||
| proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { | |||
| # Do nothing | |||
| } | |||
| } | |||
| } | |||
| proc start_step { step } { | |||
| set stopFile ".stop.rst" | |||
| if {[file isfile .stop.rst]} { | |||
| puts "" | |||
| puts "*** Halting run - EA reset detected ***" | |||
| puts "" | |||
| puts "" | |||
| return -code error | |||
| } | |||
| set beginFile ".$step.begin.rst" | |||
| set platform "$::tcl_platform(platform)" | |||
| set user "$::tcl_platform(user)" | |||
| set pid [pid] | |||
| set host "" | |||
| if { [string equal $platform unix] } { | |||
| if { [info exist ::env(HOSTNAME)] } { | |||
| set host $::env(HOSTNAME) | |||
| } elseif { [info exist ::env(HOST)] } { | |||
| set host $::env(HOST) | |||
| } | |||
| } else { | |||
| if { [info exist ::env(COMPUTERNAME)] } { | |||
| set host $::env(COMPUTERNAME) | |||
| } | |||
| } | |||
| set ch [open $beginFile w] | |||
| puts $ch "<?xml version=\"1.0\"?>" | |||
| puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">" | |||
| puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">" | |||
| puts $ch " </Process>" | |||
| puts $ch "</ProcessHandle>" | |||
| close $ch | |||
| } | |||
| proc end_step { step } { | |||
| set endFile ".$step.end.rst" | |||
| set ch [open $endFile w] | |||
| close $ch | |||
| } | |||
| proc step_failed { step } { | |||
| set endFile ".$step.error.rst" | |||
| set ch [open $endFile w] | |||
| close $ch | |||
| OPTRACE "impl_1" END { } | |||
| } | |||
| set_msg_config -id {Synth 8-256} -limit 10000 | |||
| set_msg_config -id {Synth 8-638} -limit 10000 | |||
| OPTRACE "impl_1" START { ROLLUP_1 } | |||
| OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO } | |||
| OPTRACE "write_bitstream setup" START { } | |||
| start_step write_bitstream | |||
| set ACTIVE_STEP write_bitstream | |||
| set rc [catch { | |||
| create_msg_db write_bitstream.pb | |||
| set_param checkpoint.writeSynthRtdsInDcp 1 | |||
| set_param chipscope.maxJobs 3 | |||
| open_checkpoint fixedPointTest_routed.dcp | |||
| set_property webtalk.parent_dir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.cache/wt [current_project] | |||
| set_property TOP fixedPointTest [current_fileset] | |||
| OPTRACE "read constraints: write_bitstream" START { } | |||
| OPTRACE "read constraints: write_bitstream" END { } | |||
| catch { write_mem_info -force -no_partial_mmi fixedPointTest.mmi } | |||
| OPTRACE "write_bitstream setup" END { } | |||
| OPTRACE "write_bitstream" START { } | |||
| write_bitstream -force fixedPointTest.bit | |||
| OPTRACE "write_bitstream" END { } | |||
| OPTRACE "write_bitstream misc" START { } | |||
| OPTRACE "read constraints: write_bitstream_post" START { } | |||
| OPTRACE "read constraints: write_bitstream_post" END { } | |||
| catch {write_debug_probes -quiet -force fixedPointTest} | |||
| catch {file copy -force fixedPointTest.ltx debug_nets.ltx} | |||
| close_msg_db -file write_bitstream.pb | |||
| } RESULT] | |||
| if {$rc} { | |||
| step_failed write_bitstream | |||
| return -code error $RESULT | |||
| } else { | |||
| end_step write_bitstream | |||
| unset ACTIVE_STEP | |||
| } | |||
| OPTRACE "write_bitstream misc" END { } | |||
| OPTRACE "Phase: Write Bitstream" END { } | |||
| OPTRACE "impl_1" END { } | |||
+ 600
- 0
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi
View File
| @@ -0,0 +1,600 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 14:41:22 2022 | |||
| # Process ID: 17108 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1 | |||
| # Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| source fixedPointTest.tcl -notrace | |||
| create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 10.250 | |||
| Command: link_design -top fixedPointTest -part xc7z010clg400-1 | |||
| Design is defaulting to srcset: sources_1 | |||
| Design is defaulting to constrset: constrs_1 | |||
| INFO: [Device 21-403] Loading part xc7z010clg400-1 | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.340 ; gain = 0.000 | |||
| INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement | |||
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |||
| INFO: [Project 1-479] Netlist was created with Vivado 2021.2 | |||
| INFO: [Project 1-570] Preparing netlist for logic optimization | |||
| Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc] | |||
| WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led1_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc] | |||
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.340 ; gain = 0.000 | |||
| INFO: [Project 1-111] Unisim Transformation Summary: | |||
| No Unisim elements were transformed. | |||
| 7 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| link_design completed successfully | |||
| link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 0.000 | |||
| Command: opt_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| Running DRC as a precondition to command opt_design | |||
| Starting DRC Task | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Project 1-461] DRC finished with 0 Errors | |||
| INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.340 ; gain = 0.000 | |||
| Starting Cache Timing Information Task | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| Ending Cache Timing Information Task | Checksum: d688f8fa | |||
| Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1387.457 ; gain = 126.117 | |||
| Starting Logic Optimization Task | |||
| Phase 1 Retarget | |||
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |||
| INFO: [Opt 31-49] Retargeted 0 cell(s). | |||
| Phase 1 Retarget | Checksum: d688f8fa | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells | |||
| Phase 2 Constant propagation | |||
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |||
| Phase 2 Constant propagation | Checksum: d688f8fa | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells | |||
| Phase 3 Sweep | |||
| Phase 3 Sweep | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells | |||
| Phase 4 BUFG optimization | |||
| Phase 4 BUFG optimization | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. | |||
| Phase 5 Shift Register Optimization | |||
| INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs | |||
| Phase 5 Shift Register Optimization | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells | |||
| Phase 6 Post Processing Netlist | |||
| Phase 6 Post Processing Netlist | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells | |||
| Opt_design Change Summary | |||
| ========================= | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| | Retarget | 0 | 0 | 0 | | |||
| | Constant propagation | 0 | 0 | 0 | | |||
| | Sweep | 0 | 0 | 0 | | |||
| | BUFG optimization | 0 | 0 | 0 | | |||
| | Shift Register Optimization | 0 | 0 | 0 | | |||
| | Post Processing Netlist | 0 | 0 | 0 | | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| Starting Connectivity Check Task | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| Ending Logic Optimization Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| Starting Power Optimization Task | |||
| INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. | |||
| Ending Power Optimization Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| Starting Final Cleanup Task | |||
| Ending Final Cleanup Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| Starting Netlist Obfuscation Task | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| Ending Netlist Obfuscation Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 24 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| opt_design completed successfully | |||
| opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1683.215 ; gain = 421.875 | |||
| INFO: [Timing 38-480] Writing timing data to binary archive. | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_opt.dcp' has been generated. | |||
| INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx | |||
| Command: report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt. | |||
| report_drc completed successfully | |||
| Command: place_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |||
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |||
| Running DRC as a precondition to command place_design | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |||
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |||
| Starting Placer Task | |||
| INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs | |||
| Phase 1 Placer Initialization | |||
| Phase 1.1 Placer Initialization Netlist Sorting | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c5371e47 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | |||
| Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 170083491 | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.141 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 1.3 Build Placer Netlist Model | |||
| Phase 1.3 Build Placer Netlist Model | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.149 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 1.4 Constrain Clocks/Macros | |||
| Phase 1.4 Constrain Clocks/Macros | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.150 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 1 Placer Initialization | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.152 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 2 Global Placement | |||
| Phase 2.1 Floorplanning | |||
| Phase 2.1 Floorplanning | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 2.2 Update Timing before SLR Path Opt | |||
| Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 2.3 Post-Processing in Floorplanning | |||
| Phase 2.3 Post-Processing in Floorplanning | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 2.4 Global Placement Core | |||
| WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer | |||
| Phase 2.4 Global Placement Core | Checksum: 17701980b | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 2 Global Placement | Checksum: 17701980b | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.693 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3 Detail Placement | |||
| Phase 3.1 Commit Multi Column Macros | |||
| Phase 3.1 Commit Multi Column Macros | Checksum: 17701980b | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.2 Commit Most Macros & LUTRAMs | |||
| Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.699 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.3 Area Swap Optimization | |||
| Phase 3.3 Area Swap Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.4 Pipeline Register Optimization | |||
| Phase 3.4 Pipeline Register Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.5 Small Shape Detail Placement | |||
| Phase 3.5 Small Shape Detail Placement | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.6 Re-assign LUT pins | |||
| Phase 3.6 Re-assign LUT pins | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.7 Pipeline Register Optimization | |||
| Phase 3.7 Pipeline Register Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3 Detail Placement | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4 Post Placement Optimization and Clean-Up | |||
| Phase 4.1 Post Commit Optimization | |||
| Phase 4.1 Post Commit Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.771 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4.2 Post Placement Cleanup | |||
| Phase 4.2 Post Placement Cleanup | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.773 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4.3 Placer Reporting | |||
| Phase 4.3.1 Print Estimated Congestion | |||
| INFO: [Place 30-612] Post-Placement Estimated Congestion | |||
| ____________________________________________________ | |||
| | | Global Congestion | Short Congestion | | |||
| | Direction | Region Size | Region Size | | |||
| |___________|___________________|___________________| | |||
| | North| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| | South| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| | East| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| | West| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| Phase 4.3.1 Print Estimated Congestion | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.774 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4.3 Placer Reporting | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4.4 Final Placement Cleanup | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4 Post Placement Optimization and Clean-Up | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Ending Placer Task | Checksum: 1c0019b8b | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 43 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| place_design completed successfully | |||
| INFO: [Timing 38-480] Writing timing data to binary archive. | |||
| Writing placer database... | |||
| Writing XDEF routing. | |||
| Writing XDEF routing logical nets. | |||
| Writing XDEF routing special nets. | |||
| Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_placed.dcp' has been generated. | |||
| INFO: [runtcl-4] Executing : report_io -file fixedPointTest_io_placed.rpt | |||
| report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_placed.rpt -pb fixedPointTest_utilization_placed.pb | |||
| INFO: [runtcl-4] Executing : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt | |||
| report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Command: phys_opt_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 51 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| phys_opt_design completed successfully | |||
| INFO: [Timing 38-480] Writing timing data to binary archive. | |||
| Writing placer database... | |||
| Writing XDEF routing. | |||
| Writing XDEF routing logical nets. | |||
| Writing XDEF routing special nets. | |||
| Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_physopt.dcp' has been generated. | |||
| Command: route_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| Running DRC as a precondition to command route_design | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |||
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |||
| Starting Routing Task | |||
| INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs | |||
| Phase 1 Build RT Design | |||
| Checksum: PlaceDB: faca7d44 ConstDB: 0 ShapeSum: c5371e47 RouteDB: 0 | |||
| Post Restoration Checksum: NetGraph: 54150718 NumContArr: b3d68f27 Constraints: 0 Timing: 0 | |||
| Phase 1 Build RT Design | Checksum: 107eb963f | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1757.188 ; gain = 23.668 | |||
| Phase 2 Router Initialization | |||
| INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. | |||
| Phase 2.1 Fix Topology Constraints | |||
| Phase 2.1 Fix Topology Constraints | Checksum: 107eb963f | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699 | |||
| Phase 2.2 Pre Route Cleanup | |||
| Phase 2.2 Pre Route Cleanup | Checksum: 107eb963f | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699 | |||
| Number of Nodes with overlaps = 0 | |||
| Router Utilization Summary | |||
| Global Vertical Routing Utilization = 0 % | |||
| Global Horizontal Routing Utilization = 0 % | |||
| Routable Net Status* | |||
| *Does not include unroutable nets such as driverless and loadless. | |||
| Run report_route_status for detailed report. | |||
| Number of Failed Nets = 46 | |||
| (Failed Nets is the sum of unrouted and partially routed nets) | |||
| Number of Unrouted Nets = 46 | |||
| Number of Partially Routed Nets = 0 | |||
| Number of Node Overlaps = 0 | |||
| Phase 2 Router Initialization | Checksum: d7f76c92 | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 3 Initial Routing | |||
| Phase 3.1 Global Routing | |||
| Phase 3.1 Global Routing | Checksum: d7f76c92 | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 3 Initial Routing | Checksum: aa1bb3ea | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 4 Rip-up And Reroute | |||
| Phase 4.1 Global Iteration 0 | |||
| Number of Nodes with overlaps = 0 | |||
| Phase 4.1 Global Iteration 0 | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 4 Rip-up And Reroute | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 5 Delay and Skew Optimization | |||
| Phase 5 Delay and Skew Optimization | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 6 Post Hold Fix | |||
| Phase 6.1 Hold Fix Iter | |||
| Phase 6.1 Hold Fix Iter | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 6 Post Hold Fix | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 7 Route finalize | |||
| Router Utilization Summary | |||
| Global Vertical Routing Utilization = 0.0663007 % | |||
| Global Horizontal Routing Utilization = 0.0248162 % | |||
| Routable Net Status* | |||
| *Does not include unroutable nets such as driverless and loadless. | |||
| Run report_route_status for detailed report. | |||
| Number of Failed Nets = 0 | |||
| (Failed Nets is the sum of unrouted and partially routed nets) | |||
| Number of Unrouted Nets = 0 | |||
| Number of Partially Routed Nets = 0 | |||
| Number of Node Overlaps = 0 | |||
| Congestion Report | |||
| North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. | |||
| South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions. | |||
| East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. | |||
| West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. | |||
| ------------------------------ | |||
| Reporting congestion hotspots | |||
| ------------------------------ | |||
| Direction: North | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Direction: South | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Direction: East | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Direction: West | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Phase 7 Route finalize | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 8 Verifying routed nets | |||
| Verification completed successfully | |||
| Phase 8 Verifying routed nets | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910 | |||
| Phase 9 Depositing Routes | |||
| Phase 9 Depositing Routes | Checksum: 156fe757f | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910 | |||
| INFO: [Route 35-16] Router Completed Successfully | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910 | |||
| Routing Is Done. | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 61 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| route_design completed successfully | |||
| route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1765.430 ; gain = 43.164 | |||
| INFO: [Timing 38-480] Writing timing data to binary archive. | |||
| Writing placer database... | |||
| Writing XDEF routing. | |||
| Writing XDEF routing logical nets. | |||
| Writing XDEF routing special nets. | |||
| Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1775.246 ; gain = 9.816 | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_routed.dcp' has been generated. | |||
| INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx | |||
| Command: report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx | |||
| INFO: [IP_Flow 19-1839] IP Catalog is up to date. | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt. | |||
| report_drc completed successfully | |||
| INFO: [runtcl-4] Executing : report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx | |||
| Command: report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| INFO: [DRC 23-133] Running Methodology with 2 threads | |||
| INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt. | |||
| report_methodology completed successfully | |||
| INFO: [runtcl-4] Executing : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx | |||
| Command: report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. | |||
| Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate | |||
| Running Vector-less Activity Propagation... | |||
| Finished Running Vector-less Activity Propagation | |||
| 73 Infos, 9 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| report_power completed successfully | |||
| INFO: [runtcl-4] Executing : report_route_status -file fixedPointTest_route_status.rpt -pb fixedPointTest_route_status.pb | |||
| INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation | |||
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. | |||
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs | |||
| WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. | |||
| INFO: [runtcl-4] Executing : report_incremental_reuse -file fixedPointTest_incremental_reuse_routed.rpt | |||
| INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. | |||
| INFO: [runtcl-4] Executing : report_clock_utilization -file fixedPointTest_clock_utilization_routed.rpt | |||
| INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fixedPointTest_bus_skew_routed.rpt -pb fixedPointTest_bus_skew_routed.pb -rpx fixedPointTest_bus_skew_routed.rpx | |||
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. | |||
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs | |||
| INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:42:11 2022... | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 14:42:39 2022 | |||
| # Process ID: 11092 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1 | |||
| # Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| source fixedPointTest.tcl -notrace | |||
| Command: open_checkpoint fixedPointTest_routed.dcp | |||
| Starting open_checkpoint Task | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1251.590 ; gain = 0.000 | |||
| INFO: [Device 21-403] Loading part xc7z010clg400-1 | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1251.590 ; gain = 0.000 | |||
| INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement | |||
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |||
| INFO: [Project 1-479] Netlist was created with Vivado 2021.2 | |||
| INFO: [Project 1-570] Preparing netlist for logic optimization | |||
| INFO: [Timing 38-478] Restoring timing data from binary archive. | |||
| INFO: [Timing 38-479] Binary timing data restore complete. | |||
| INFO: [Project 1-856] Restoring constraints from binary archive. | |||
| INFO: [Project 1-853] Binary constraint restore complete. | |||
| Reading XDEF placement. | |||
| Reading placer database... | |||
| Reading XDEF routing. | |||
| Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1387.207 ; gain = 17.668 | |||
| Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | | |||
| Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1387.207 ; gain = 17.668 | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1387.207 ; gain = 0.000 | |||
| INFO: [Project 1-111] Unisim Transformation Summary: | |||
| No Unisim elements were transformed. | |||
| INFO: [Project 1-604] Checkpoint was created with Vivado v2021.2 (64-bit) build 3367213 | |||
| open_checkpoint: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1387.207 ; gain = 135.617 | |||
| Command: write_bitstream -force fixedPointTest.bit | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| Running DRC as a precondition to command write_bitstream | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| ERROR: [DRC NSTD-1] Unspecified I/O Standard: 43 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], and c[8:-6]. | |||
| ERROR: [DRC UCIO-1] Unconstrained Logical Port: 43 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], and c[8:-6]. | |||
| WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. | |||
| INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings | |||
| INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. | |||
| ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 19 Infos, 1 Warnings, 0 Critical Warnings and 3 Errors encountered. | |||
| write_bitstream failed | |||
| ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. | |||
| INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:43:07 2022... | |||
+ 512
- 0
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_11388.backup.vdi
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| @@ -0,0 +1,512 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 14:31:34 2022 | |||
| # Process ID: 11388 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1 | |||
| # Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| source fixedPointTest.tcl -notrace | |||
| create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1261.066 ; gain = 9.613 | |||
| Command: link_design -top fixedPointTest -part xc7z010clg400-1 | |||
| Design is defaulting to srcset: sources_1 | |||
| Design is defaulting to constrset: constrs_1 | |||
| INFO: [Device 21-403] Loading part xc7z010clg400-1 | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.066 ; gain = 0.000 | |||
| INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement | |||
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |||
| INFO: [Project 1-479] Netlist was created with Vivado 2021.2 | |||
| INFO: [Project 1-570] Preparing netlist for logic optimization | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.066 ; gain = 0.000 | |||
| INFO: [Project 1-111] Unisim Transformation Summary: | |||
| No Unisim elements were transformed. | |||
| 6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. | |||
| link_design completed successfully | |||
| link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.066 ; gain = 0.000 | |||
| Command: opt_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| Running DRC as a precondition to command opt_design | |||
| Starting DRC Task | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Project 1-461] DRC finished with 0 Errors | |||
| INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.066 ; gain = 0.000 | |||
| Starting Cache Timing Information Task | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| Ending Cache Timing Information Task | Checksum: d688f8fa | |||
| Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1385.141 ; gain = 124.074 | |||
| Starting Logic Optimization Task | |||
| Phase 1 Retarget | |||
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |||
| INFO: [Opt 31-49] Retargeted 0 cell(s). | |||
| Phase 1 Retarget | Checksum: d688f8fa | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells | |||
| Phase 2 Constant propagation | |||
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |||
| Phase 2 Constant propagation | Checksum: d688f8fa | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells | |||
| Phase 3 Sweep | |||
| Phase 3 Sweep | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells | |||
| Phase 4 BUFG optimization | |||
| Phase 4 BUFG optimization | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. | |||
| Phase 5 Shift Register Optimization | |||
| INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs | |||
| Phase 5 Shift Register Optimization | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells | |||
| Phase 6 Post Processing Netlist | |||
| Phase 6 Post Processing Netlist | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells | |||
| Opt_design Change Summary | |||
| ========================= | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| | Retarget | 0 | 0 | 0 | | |||
| | Constant propagation | 0 | 0 | 0 | | |||
| | Sweep | 0 | 0 | 0 | | |||
| | BUFG optimization | 0 | 0 | 0 | | |||
| | Shift Register Optimization | 0 | 0 | 0 | | |||
| | Post Processing Netlist | 0 | 0 | 0 | | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| Starting Connectivity Check Task | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| Ending Logic Optimization Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| Starting Power Optimization Task | |||
| INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. | |||
| Ending Power Optimization Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| Starting Final Cleanup Task | |||
| Ending Final Cleanup Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| Starting Netlist Obfuscation Task | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| Ending Netlist Obfuscation Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1680.863 ; gain = 0.000 | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. | |||
| opt_design completed successfully | |||
| opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1680.863 ; gain = 419.797 | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_opt.dcp' has been generated. | |||
| INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx | |||
| Command: report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt. | |||
| report_drc completed successfully | |||
| Command: place_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |||
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |||
| Running DRC as a precondition to command place_design | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |||
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |||
| Starting Placer Task | |||
| INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs | |||
| Phase 1 Placer Initialization | |||
| Phase 1.1 Placer Initialization Netlist Sorting | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c5371e47 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | |||
| Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 170083491 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.220 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 1.3 Build Placer Netlist Model | |||
| Phase 1.3 Build Placer Netlist Model | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.254 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 1.4 Constrain Clocks/Macros | |||
| Phase 1.4 Constrain Clocks/Macros | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.257 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 1 Placer Initialization | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.264 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 2 Global Placement | |||
| Phase 2.1 Floorplanning | |||
| Phase 2.1 Floorplanning | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.272 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 2.2 Update Timing before SLR Path Opt | |||
| Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.273 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 2.3 Post-Processing in Floorplanning | |||
| Phase 2.3 Post-Processing in Floorplanning | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.273 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 2.4 Global Placement Core | |||
| WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer | |||
| Phase 2.4 Global Placement Core | Checksum: 17701980b | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.793 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 2 Global Placement | Checksum: 17701980b | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.797 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 3 Detail Placement | |||
| Phase 3.1 Commit Multi Column Macros | |||
| Phase 3.1 Commit Multi Column Macros | Checksum: 17701980b | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.800 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 3.2 Commit Most Macros & LUTRAMs | |||
| Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.806 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 3.3 Area Swap Optimization | |||
| Phase 3.3 Area Swap Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.812 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 3.4 Pipeline Register Optimization | |||
| Phase 3.4 Pipeline Register Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.814 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 3.5 Small Shape Detail Placement | |||
| Phase 3.5 Small Shape Detail Placement | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.852 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 3.6 Re-assign LUT pins | |||
| Phase 3.6 Re-assign LUT pins | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.855 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 3.7 Pipeline Register Optimization | |||
| Phase 3.7 Pipeline Register Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.856 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 3 Detail Placement | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.857 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 4 Post Placement Optimization and Clean-Up | |||
| Phase 4.1 Post Commit Optimization | |||
| Phase 4.1 Post Commit Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.873 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 4.2 Post Placement Cleanup | |||
| Phase 4.2 Post Placement Cleanup | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.875 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 4.3 Placer Reporting | |||
| Phase 4.3.1 Print Estimated Congestion | |||
| INFO: [Place 30-612] Post-Placement Estimated Congestion | |||
| ____________________________________________________ | |||
| | | Global Congestion | Short Congestion | | |||
| | Direction | Region Size | Region Size | | |||
| |___________|___________________|___________________| | |||
| | North| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| | South| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| | East| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| | West| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| Phase 4.3.1 Print Estimated Congestion | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.877 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 4.3 Placer Reporting | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.877 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 4.4 Final Placement Cleanup | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.878 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Phase 4 Post Placement Optimization and Clean-Up | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.878 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Ending Placer Task | Checksum: 1c0019b8b | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.879 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 41 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. | |||
| place_design completed successfully | |||
| Writing placer database... | |||
| Writing XDEF routing. | |||
| Writing XDEF routing logical nets. | |||
| Writing XDEF routing special nets. | |||
| Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.124 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_placed.dcp' has been generated. | |||
| INFO: [runtcl-4] Executing : report_io -file fixedPointTest_io_placed.rpt | |||
| report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.079 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_placed.rpt -pb fixedPointTest_utilization_placed.pb | |||
| INFO: [runtcl-4] Executing : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt | |||
| report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| Command: phys_opt_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 48 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. | |||
| phys_opt_design completed successfully | |||
| Writing placer database... | |||
| Writing XDEF routing. | |||
| Writing XDEF routing logical nets. | |||
| Writing XDEF routing special nets. | |||
| Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1718.922 ; gain = 0.000 | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_physopt.dcp' has been generated. | |||
| Command: route_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| Running DRC as a precondition to command route_design | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |||
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |||
| Starting Routing Task | |||
| INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs | |||
| Phase 1 Build RT Design | |||
| Checksum: PlaceDB: faca7d44 ConstDB: 0 ShapeSum: c5371e47 RouteDB: 0 | |||
| Post Restoration Checksum: NetGraph: 54150718 NumContArr: b3d68f27 Constraints: 0 Timing: 0 | |||
| Phase 1 Build RT Design | Checksum: 107eb963f | |||
| Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1755.223 ; gain = 25.043 | |||
| Phase 2 Router Initialization | |||
| INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. | |||
| Phase 2.1 Fix Topology Constraints | |||
| Phase 2.1 Fix Topology Constraints | Checksum: 107eb963f | |||
| Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1761.215 ; gain = 31.035 | |||
| Phase 2.2 Pre Route Cleanup | |||
| Phase 2.2 Pre Route Cleanup | Checksum: 107eb963f | |||
| Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1761.215 ; gain = 31.035 | |||
| Number of Nodes with overlaps = 0 | |||
| Router Utilization Summary | |||
| Global Vertical Routing Utilization = 0 % | |||
| Global Horizontal Routing Utilization = 0 % | |||
| Routable Net Status* | |||
| *Does not include unroutable nets such as driverless and loadless. | |||
| Run report_route_status for detailed report. | |||
| Number of Failed Nets = 46 | |||
| (Failed Nets is the sum of unrouted and partially routed nets) | |||
| Number of Unrouted Nets = 46 | |||
| Number of Partially Routed Nets = 0 | |||
| Number of Node Overlaps = 0 | |||
| Phase 2 Router Initialization | Checksum: d7f76c92 | |||
| Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012 | |||
| Phase 3 Initial Routing | |||
| Phase 3.1 Global Routing | |||
| Phase 3.1 Global Routing | Checksum: d7f76c92 | |||
| Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012 | |||
| Phase 3 Initial Routing | Checksum: aa1bb3ea | |||
| Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012 | |||
| Phase 4 Rip-up And Reroute | |||
| Phase 4.1 Global Iteration 0 | |||
| Number of Nodes with overlaps = 0 | |||
| Phase 4.1 Global Iteration 0 | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012 | |||
| Phase 4 Rip-up And Reroute | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012 | |||
| Phase 5 Delay and Skew Optimization | |||
| Phase 5 Delay and Skew Optimization | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012 | |||
| Phase 6 Post Hold Fix | |||
| Phase 6.1 Hold Fix Iter | |||
| Phase 6.1 Hold Fix Iter | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012 | |||
| Phase 6 Post Hold Fix | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012 | |||
| Phase 7 Route finalize | |||
| Router Utilization Summary | |||
| Global Vertical Routing Utilization = 0.0663007 % | |||
| Global Horizontal Routing Utilization = 0.0248162 % | |||
| Routable Net Status* | |||
| *Does not include unroutable nets such as driverless and loadless. | |||
| Run report_route_status for detailed report. | |||
| Number of Failed Nets = 0 | |||
| (Failed Nets is the sum of unrouted and partially routed nets) | |||
| Number of Unrouted Nets = 0 | |||
| Number of Partially Routed Nets = 0 | |||
| Number of Node Overlaps = 0 | |||
| Congestion Report | |||
| North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. | |||
| South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions. | |||
| East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. | |||
| West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. | |||
| ------------------------------ | |||
| Reporting congestion hotspots | |||
| ------------------------------ | |||
| Direction: North | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Direction: South | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Direction: East | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Direction: West | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Phase 7 Route finalize | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1763.191 ; gain = 33.012 | |||
| Phase 8 Verifying routed nets | |||
| Verification completed successfully | |||
| Phase 8 Verifying routed nets | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.297 ; gain = 34.117 | |||
| Phase 9 Depositing Routes | |||
| Phase 9 Depositing Routes | Checksum: 156fe757f | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.297 ; gain = 34.117 | |||
| INFO: [Route 35-16] Router Completed Successfully | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.297 ; gain = 34.117 | |||
| Routing Is Done. | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 57 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. | |||
| route_design completed successfully | |||
| route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1764.297 ; gain = 45.375 | |||
| Writing placer database... | |||
| Writing XDEF routing. | |||
| Writing XDEF routing logical nets. | |||
| Writing XDEF routing special nets. | |||
| Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1774.078 ; gain = 9.781 | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_routed.dcp' has been generated. | |||
| INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx | |||
| Command: report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx | |||
| INFO: [IP_Flow 19-1839] IP Catalog is up to date. | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt. | |||
| report_drc completed successfully | |||
| INFO: [runtcl-4] Executing : report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx | |||
| Command: report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| INFO: [DRC 23-133] Running Methodology with 2 threads | |||
| INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt. | |||
| report_methodology completed successfully | |||
| INFO: [runtcl-4] Executing : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx | |||
| Command: report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. | |||
| Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate | |||
| Running Vector-less Activity Propagation... | |||
| Finished Running Vector-less Activity Propagation | |||
| 68 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. | |||
| report_power completed successfully | |||
| INFO: [runtcl-4] Executing : report_route_status -file fixedPointTest_route_status.rpt -pb fixedPointTest_route_status.pb | |||
| INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation | |||
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. | |||
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs | |||
| WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. | |||
| INFO: [runtcl-4] Executing : report_incremental_reuse -file fixedPointTest_incremental_reuse_routed.rpt | |||
| INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. | |||
| INFO: [runtcl-4] Executing : report_clock_utilization -file fixedPointTest_clock_utilization_routed.rpt | |||
| INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fixedPointTest_bus_skew_routed.rpt -pb fixedPointTest_bus_skew_routed.pb -rpx fixedPointTest_bus_skew_routed.rpx | |||
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. | |||
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs | |||
| INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:32:21 2022... | |||
+ 540
- 0
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_17108.backup.vdi
View File
| @@ -0,0 +1,540 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 14:41:22 2022 | |||
| # Process ID: 17108 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1 | |||
| # Command line: vivado.exe -log fixedPointTest.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest.vdi | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| source fixedPointTest.tcl -notrace | |||
| create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 10.250 | |||
| Command: link_design -top fixedPointTest -part xc7z010clg400-1 | |||
| Design is defaulting to srcset: sources_1 | |||
| Design is defaulting to constrset: constrs_1 | |||
| INFO: [Device 21-403] Loading part xc7z010clg400-1 | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1261.340 ; gain = 0.000 | |||
| INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement | |||
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |||
| INFO: [Project 1-479] Netlist was created with Vivado 2021.2 | |||
| INFO: [Project 1-570] Preparing netlist for logic optimization | |||
| Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc] | |||
| WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led0_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:11] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led0_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:12] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led0_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:13] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led1_b'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:15] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led1_g'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:16] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| WARNING: [Vivado 12-584] No ports matched 'led1_r'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17] | |||
| CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:17] | |||
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |||
| Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc] | |||
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.340 ; gain = 0.000 | |||
| INFO: [Project 1-111] Unisim Transformation Summary: | |||
| No Unisim elements were transformed. | |||
| 7 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| link_design completed successfully | |||
| link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.340 ; gain = 0.000 | |||
| Command: opt_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| Running DRC as a precondition to command opt_design | |||
| Starting DRC Task | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Project 1-461] DRC finished with 0 Errors | |||
| INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.340 ; gain = 0.000 | |||
| Starting Cache Timing Information Task | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| Ending Cache Timing Information Task | Checksum: d688f8fa | |||
| Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1387.457 ; gain = 126.117 | |||
| Starting Logic Optimization Task | |||
| Phase 1 Retarget | |||
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |||
| INFO: [Opt 31-49] Retargeted 0 cell(s). | |||
| Phase 1 Retarget | Checksum: d688f8fa | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells | |||
| Phase 2 Constant propagation | |||
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |||
| Phase 2 Constant propagation | Checksum: d688f8fa | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells | |||
| Phase 3 Sweep | |||
| Phase 3 Sweep | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells | |||
| Phase 4 BUFG optimization | |||
| Phase 4 BUFG optimization | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. | |||
| Phase 5 Shift Register Optimization | |||
| INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs | |||
| Phase 5 Shift Register Optimization | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells | |||
| Phase 6 Post Processing Netlist | |||
| Phase 6 Post Processing Netlist | Checksum: 9d9fcb97 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells | |||
| Opt_design Change Summary | |||
| ========================= | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| | Retarget | 0 | 0 | 0 | | |||
| | Constant propagation | 0 | 0 | 0 | | |||
| | Sweep | 0 | 0 | 0 | | |||
| | BUFG optimization | 0 | 0 | 0 | | |||
| | Shift Register Optimization | 0 | 0 | 0 | | |||
| | Post Processing Netlist | 0 | 0 | 0 | | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| Starting Connectivity Check Task | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| Ending Logic Optimization Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| Starting Power Optimization Task | |||
| INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. | |||
| Ending Power Optimization Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| Starting Final Cleanup Task | |||
| Ending Final Cleanup Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| Starting Netlist Obfuscation Task | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| Ending Netlist Obfuscation Task | Checksum: f158031e | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1683.215 ; gain = 0.000 | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 24 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| opt_design completed successfully | |||
| opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1683.215 ; gain = 421.875 | |||
| INFO: [Timing 38-480] Writing timing data to binary archive. | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_opt.dcp' has been generated. | |||
| INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx | |||
| Command: report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.rpt. | |||
| report_drc completed successfully | |||
| Command: place_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |||
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |||
| Running DRC as a precondition to command place_design | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |||
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |||
| Starting Placer Task | |||
| INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs | |||
| Phase 1 Placer Initialization | |||
| Phase 1.1 Placer Initialization Netlist Sorting | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c5371e47 | |||
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | |||
| Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 170083491 | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.141 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 1.3 Build Placer Netlist Model | |||
| Phase 1.3 Build Placer Netlist Model | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.149 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 1.4 Constrain Clocks/Macros | |||
| Phase 1.4 Constrain Clocks/Macros | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.150 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 1 Placer Initialization | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.152 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 2 Global Placement | |||
| Phase 2.1 Floorplanning | |||
| Phase 2.1 Floorplanning | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 2.2 Update Timing before SLR Path Opt | |||
| Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.153 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 2.3 Post-Processing in Floorplanning | |||
| Phase 2.3 Post-Processing in Floorplanning | Checksum: 1e3fab18a | |||
| Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 2.4 Global Placement Core | |||
| WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer | |||
| Phase 2.4 Global Placement Core | Checksum: 17701980b | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 2 Global Placement | Checksum: 17701980b | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.693 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3 Detail Placement | |||
| Phase 3.1 Commit Multi Column Macros | |||
| Phase 3.1 Commit Multi Column Macros | Checksum: 17701980b | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.2 Commit Most Macros & LUTRAMs | |||
| Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.699 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.3 Area Swap Optimization | |||
| Phase 3.3 Area Swap Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.4 Pipeline Register Optimization | |||
| Phase 3.4 Pipeline Register Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.5 Small Shape Detail Placement | |||
| Phase 3.5 Small Shape Detail Placement | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.6 Re-assign LUT pins | |||
| Phase 3.6 Re-assign LUT pins | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3.7 Pipeline Register Optimization | |||
| Phase 3.7 Pipeline Register Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 3 Detail Placement | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4 Post Placement Optimization and Clean-Up | |||
| Phase 4.1 Post Commit Optimization | |||
| Phase 4.1 Post Commit Optimization | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.771 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4.2 Post Placement Cleanup | |||
| Phase 4.2 Post Placement Cleanup | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.773 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4.3 Placer Reporting | |||
| Phase 4.3.1 Print Estimated Congestion | |||
| INFO: [Place 30-612] Post-Placement Estimated Congestion | |||
| ____________________________________________________ | |||
| | | Global Congestion | Short Congestion | | |||
| | Direction | Region Size | Region Size | | |||
| |___________|___________________|___________________| | |||
| | North| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| | South| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| | East| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| | West| 1x1| 1x1| | |||
| |___________|___________________|___________________| | |||
| Phase 4.3.1 Print Estimated Congestion | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.774 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4.3 Placer Reporting | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4.4 Final Placement Cleanup | |||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Phase 4 Post Placement Optimization and Clean-Up | Checksum: 236ae8e9c | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Ending Placer Task | Checksum: 1c0019b8b | |||
| Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 43 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| place_design completed successfully | |||
| INFO: [Timing 38-480] Writing timing data to binary archive. | |||
| Writing placer database... | |||
| Writing XDEF routing. | |||
| Writing XDEF routing logical nets. | |||
| Writing XDEF routing special nets. | |||
| Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_placed.dcp' has been generated. | |||
| INFO: [runtcl-4] Executing : report_io -file fixedPointTest_io_placed.rpt | |||
| report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_placed.rpt -pb fixedPointTest_utilization_placed.pb | |||
| INFO: [runtcl-4] Executing : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt | |||
| report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| Command: phys_opt_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 51 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| phys_opt_design completed successfully | |||
| INFO: [Timing 38-480] Writing timing data to binary archive. | |||
| Writing placer database... | |||
| Writing XDEF routing. | |||
| Writing XDEF routing logical nets. | |||
| Writing XDEF routing special nets. | |||
| Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1722.266 ; gain = 0.000 | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_physopt.dcp' has been generated. | |||
| Command: route_design | |||
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' | |||
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' | |||
| Running DRC as a precondition to command route_design | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |||
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |||
| Starting Routing Task | |||
| INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs | |||
| Phase 1 Build RT Design | |||
| Checksum: PlaceDB: faca7d44 ConstDB: 0 ShapeSum: c5371e47 RouteDB: 0 | |||
| Post Restoration Checksum: NetGraph: 54150718 NumContArr: b3d68f27 Constraints: 0 Timing: 0 | |||
| Phase 1 Build RT Design | Checksum: 107eb963f | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1757.188 ; gain = 23.668 | |||
| Phase 2 Router Initialization | |||
| INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. | |||
| Phase 2.1 Fix Topology Constraints | |||
| Phase 2.1 Fix Topology Constraints | Checksum: 107eb963f | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699 | |||
| Phase 2.2 Pre Route Cleanup | |||
| Phase 2.2 Pre Route Cleanup | Checksum: 107eb963f | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1762.219 ; gain = 28.699 | |||
| Number of Nodes with overlaps = 0 | |||
| Router Utilization Summary | |||
| Global Vertical Routing Utilization = 0 % | |||
| Global Horizontal Routing Utilization = 0 % | |||
| Routable Net Status* | |||
| *Does not include unroutable nets such as driverless and loadless. | |||
| Run report_route_status for detailed report. | |||
| Number of Failed Nets = 46 | |||
| (Failed Nets is the sum of unrouted and partially routed nets) | |||
| Number of Unrouted Nets = 46 | |||
| Number of Partially Routed Nets = 0 | |||
| Number of Node Overlaps = 0 | |||
| Phase 2 Router Initialization | Checksum: d7f76c92 | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 3 Initial Routing | |||
| Phase 3.1 Global Routing | |||
| Phase 3.1 Global Routing | Checksum: d7f76c92 | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 3 Initial Routing | Checksum: aa1bb3ea | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 4 Rip-up And Reroute | |||
| Phase 4.1 Global Iteration 0 | |||
| Number of Nodes with overlaps = 0 | |||
| Phase 4.1 Global Iteration 0 | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 4 Rip-up And Reroute | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 5 Delay and Skew Optimization | |||
| Phase 5 Delay and Skew Optimization | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 6 Post Hold Fix | |||
| Phase 6.1 Hold Fix Iter | |||
| Phase 6.1 Hold Fix Iter | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 6 Post Hold Fix | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 7 Route finalize | |||
| Router Utilization Summary | |||
| Global Vertical Routing Utilization = 0.0663007 % | |||
| Global Horizontal Routing Utilization = 0.0248162 % | |||
| Routable Net Status* | |||
| *Does not include unroutable nets such as driverless and loadless. | |||
| Run report_route_status for detailed report. | |||
| Number of Failed Nets = 0 | |||
| (Failed Nets is the sum of unrouted and partially routed nets) | |||
| Number of Unrouted Nets = 0 | |||
| Number of Partially Routed Nets = 0 | |||
| Number of Node Overlaps = 0 | |||
| Congestion Report | |||
| North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. | |||
| South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions. | |||
| East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. | |||
| West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. | |||
| ------------------------------ | |||
| Reporting congestion hotspots | |||
| ------------------------------ | |||
| Direction: North | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Direction: South | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Direction: East | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Direction: West | |||
| ---------------- | |||
| Congested clusters found at Level 0 | |||
| Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 | |||
| Phase 7 Route finalize | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.324 ; gain = 30.805 | |||
| Phase 8 Verifying routed nets | |||
| Verification completed successfully | |||
| Phase 8 Verifying routed nets | Checksum: 1a2c45faa | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910 | |||
| Phase 9 Depositing Routes | |||
| Phase 9 Depositing Routes | Checksum: 156fe757f | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910 | |||
| INFO: [Route 35-16] Router Completed Successfully | |||
| Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1765.430 ; gain = 31.910 | |||
| Routing Is Done. | |||
| INFO: [Common 17-83] Releasing license: Implementation | |||
| 61 Infos, 8 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| route_design completed successfully | |||
| route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1765.430 ; gain = 43.164 | |||
| INFO: [Timing 38-480] Writing timing data to binary archive. | |||
| Writing placer database... | |||
| Writing XDEF routing. | |||
| Writing XDEF routing logical nets. | |||
| Writing XDEF routing special nets. | |||
| Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1775.246 ; gain = 9.816 | |||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_routed.dcp' has been generated. | |||
| INFO: [runtcl-4] Executing : report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx | |||
| Command: report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx | |||
| INFO: [IP_Flow 19-1839] IP Catalog is up to date. | |||
| INFO: [DRC 23-27] Running DRC with 2 threads | |||
| INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_routed.rpt. | |||
| report_drc completed successfully | |||
| INFO: [runtcl-4] Executing : report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx | |||
| Command: report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| INFO: [DRC 23-133] Running Methodology with 2 threads | |||
| INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_methodology_drc_routed.rpt. | |||
| report_methodology completed successfully | |||
| INFO: [runtcl-4] Executing : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx | |||
| Command: report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx | |||
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |||
| WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. | |||
| Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate | |||
| Running Vector-less Activity Propagation... | |||
| Finished Running Vector-less Activity Propagation | |||
| 73 Infos, 9 Warnings, 7 Critical Warnings and 0 Errors encountered. | |||
| report_power completed successfully | |||
| INFO: [runtcl-4] Executing : report_route_status -file fixedPointTest_route_status.rpt -pb fixedPointTest_route_status.pb | |||
| INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation | |||
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. | |||
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs | |||
| WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. | |||
| INFO: [runtcl-4] Executing : report_incremental_reuse -file fixedPointTest_incremental_reuse_routed.rpt | |||
| INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. | |||
| INFO: [runtcl-4] Executing : report_clock_utilization -file fixedPointTest_clock_utilization_routed.rpt | |||
| INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fixedPointTest_bus_skew_routed.rpt -pb fixedPointTest_bus_skew_routed.pb -rpx fixedPointTest_bus_skew_routed.rpx | |||
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. | |||
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs | |||
| INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:42:11 2022... | |||
BIN
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.pb
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StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.rpt
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| @@ -0,0 +1,15 @@ | |||
| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | |||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | |||
| | Date : Fri May 13 14:42:11 2022 | |||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | |||
| | Command : report_bus_skew -warn_on_violation -file fixedPointTest_bus_skew_routed.rpt -pb fixedPointTest_bus_skew_routed.pb -rpx fixedPointTest_bus_skew_routed.rpx | |||
| | Design : fixedPointTest | |||
| | Device : 7z010-clg400 | |||
| | Speed File : -1 PRODUCTION 1.12 2019-11-22 | |||
| --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | |||
| Bus Skew Report | |||
| No bus skew constraints | |||
BIN
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_bus_skew_routed.rpx
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StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_clock_utilization_routed.rpt
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| @@ -0,0 +1,90 @@ | |||
| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| -------------------------------------------------------------------------------------------- | |||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | |||
| | Date : Fri May 13 14:42:11 2022 | |||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | |||
| | Command : report_clock_utilization -file fixedPointTest_clock_utilization_routed.rpt | |||
| | Design : fixedPointTest | |||
| | Device : 7z010-clg400 | |||
| | Speed File : -1 PRODUCTION 1.12 2019-11-22 | |||
| | Design State : Routed | |||
| -------------------------------------------------------------------------------------------- | |||
| Clock Utilization Report | |||
| Table of Contents | |||
| ----------------- | |||
| 1. Clock Primitive Utilization | |||
| 2. Global Clock Resources | |||
| 3. Global Clock Source Details | |||
| 4. Clock Regions: Key Resource Utilization | |||
| 5. Clock Regions : Global Clock Summary | |||
| 1. Clock Primitive Utilization | |||
| ------------------------------ | |||
| +----------+------+-----------+-----+--------------+--------+ | |||
| | Type | Used | Available | LOC | Clock Region | Pblock | | |||
| +----------+------+-----------+-----+--------------+--------+ | |||
| | BUFGCTRL | 0 | 32 | 0 | 0 | 0 | | |||
| | BUFH | 0 | 48 | 0 | 0 | 0 | | |||
| | BUFIO | 0 | 8 | 0 | 0 | 0 | | |||
| | BUFMR | 0 | 4 | 0 | 0 | 0 | | |||
| | BUFR | 0 | 8 | 0 | 0 | 0 | | |||
| | MMCM | 0 | 2 | 0 | 0 | 0 | | |||
| | PLL | 0 | 2 | 0 | 0 | 0 | | |||
| +----------+------+-----------+-----+--------------+--------+ | |||
| 2. Global Clock Resources | |||
| ------------------------- | |||
| +-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ | |||
| | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | | |||
| +-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ | |||
| * Clock Loads column represents the clock pin loads (pin count) | |||
| ** Non-Clock Loads column represents the non-clock pin loads (pin count) | |||
| 3. Global Clock Source Details | |||
| ------------------------------ | |||
| +-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ | |||
| | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | | |||
| +-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ | |||
| * Clock Loads column represents the clock pin loads (pin count) | |||
| ** Non-Clock Loads column represents the non-clock pin loads (pin count) | |||
| 4. Clock Regions: Key Resource Utilization | |||
| ------------------------------------------ | |||
| +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | |||
| | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | | |||
| +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | |||
| | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | | |||
| +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | |||
| | X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | |||
| | X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | | |||
| | X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | |||
| | X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | | |||
| +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | |||
| * Global Clock column represents track count; while other columns represents cell counts | |||
| 5. Clock Regions : Global Clock Summary | |||
| --------------------------------------- | |||
| All Modules | |||
| +----+----+----+ | |||
| | | X0 | X1 | | |||
| +----+----+----+ | |||
| | Y1 | 0 | 0 | | |||
| | Y0 | 0 | 0 | | |||
| +----+----+----+ | |||
| # Location of IO Primitives which is load of clock spine | |||
| # Location of clock ports | |||
+ 77
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| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| ------------------------------------------------------------------------------------------- | |||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | |||
| | Date : Fri May 13 14:41:53 2022 | |||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | |||
| | Command : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt | |||
| | Design : fixedPointTest | |||
| | Device : xc7z010 | |||
| ------------------------------------------------------------------------------------------- | |||
| Control Set Information | |||
| Table of Contents | |||
| ----------------- | |||
| 1. Summary | |||
| 2. Histogram | |||
| 3. Flip-Flop Distribution | |||
| 4. Detailed Control Set Information | |||
| 1. Summary | |||
| ---------- | |||
| +----------------------------------------------------------+-------+ | |||
| | Status | Count | | |||
| +----------------------------------------------------------+-------+ | |||
| | Total control sets | 0 | | |||
| | Minimum number of control sets | 0 | | |||
| | Addition due to synthesis replication | 0 | | |||
| | Addition due to physical synthesis replication | 0 | | |||
| | Unused register locations in slices containing registers | 0 | | |||
| +----------------------------------------------------------+-------+ | |||
| * Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers | |||
| ** Run report_qor_suggestions for automated merging and remapping suggestions | |||
| 2. Histogram | |||
| ------------ | |||
| +--------------------+-------+ | |||
| | Fanout | Count | | |||
| +--------------------+-------+ | |||
| | Total control sets | 0 | | |||
| | >= 0 to < 4 | 0 | | |||
| | >= 4 to < 6 | 0 | | |||
| | >= 6 to < 8 | 0 | | |||
| | >= 8 to < 10 | 0 | | |||
| | >= 10 to < 12 | 0 | | |||
| | >= 12 to < 14 | 0 | | |||
| | >= 14 to < 16 | 0 | | |||
| | >= 16 | 0 | | |||
| +--------------------+-------+ | |||
| * Control sets can be remapped at either synth_design or opt_design | |||
| 3. Flip-Flop Distribution | |||
| ------------------------- | |||
| +--------------+-----------------------+------------------------+-----------------+--------------+ | |||
| | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | | |||
| +--------------+-----------------------+------------------------+-----------------+--------------+ | |||
| | No | No | No | 0 | 0 | | |||
| | No | No | Yes | 0 | 0 | | |||
| | No | Yes | No | 0 | 0 | | |||
| | Yes | No | No | 0 | 0 | | |||
| | Yes | No | Yes | 0 | 0 | | |||
| | Yes | Yes | No | 0 | 0 | | |||
| +--------------+-----------------------+------------------------+-----------------+--------------+ | |||
| 4. Detailed Control Set Information | |||
| ----------------------------------- | |||
| +--------------+---------------+------------------+------------------+----------------+--------------+ | |||
| | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | | |||
| +--------------+---------------+------------------+------------------+----------------+--------------+ | |||
BIN
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_drc_opted.pb
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| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| --------------------------------------------------------------------------------------------------------------------------------- | |||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | |||
| | Date : Fri May 13 14:41:51 2022 | |||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | |||
| | Command : report_drc -file fixedPointTest_drc_opted.rpt -pb fixedPointTest_drc_opted.pb -rpx fixedPointTest_drc_opted.rpx | |||
| | Design : fixedPointTest | |||
| | Device : xc7z010clg400-1 | |||
| | Speed File : -1 | |||
| | Design State : Synthesized | |||
| --------------------------------------------------------------------------------------------------------------------------------- | |||
| Report DRC | |||
| Table of Contents | |||
| ----------------- | |||
| 1. REPORT SUMMARY | |||
| 2. REPORT DETAILS | |||
| 1. REPORT SUMMARY | |||
| ----------------- | |||
| Netlist: netlist | |||
| Floorplan: design_1 | |||
| Design limits: <entire design considered> | |||
| Ruledeck: default | |||
| Max violations: <unlimited> | |||
| Violations found: 3 | |||
| +--------+------------------+----------------------------+------------+ | |||
| | Rule | Severity | Description | Violations | | |||
| +--------+------------------+----------------------------+------------+ | |||
| | NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | | |||
| | UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | | |||
| | ZPS7-1 | Warning | PS7 block required | 1 | | |||
| +--------+------------------+----------------------------+------------+ | |||
| 2. REPORT DETAILS | |||
| ----------------- | |||
| NSTD-1#1 Critical Warning | |||
| Unspecified I/O Standard | |||
| 43 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], c[8:-6]. | |||
| Related violations: <none> | |||
| UCIO-1#1 Critical Warning | |||
| Unconstrained Logical Port | |||
| 43 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], c[8:-6]. | |||
| Related violations: <none> | |||
| ZPS7-1#1 Warning | |||
| PS7 block required | |||
| The PS7 cell must be used in this Zynq design in order to enable correct default configuration. | |||
| Related violations: <none> | |||
BIN
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| @@ -0,0 +1,53 @@ | |||
| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| ------------------------------------------------------------------------------------------------------------------------------------ | |||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | |||
| | Date : Fri May 13 14:42:09 2022 | |||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | |||
| | Command : report_drc -file fixedPointTest_drc_routed.rpt -pb fixedPointTest_drc_routed.pb -rpx fixedPointTest_drc_routed.rpx | |||
| | Design : fixedPointTest | |||
| | Device : xc7z010clg400-1 | |||
| | Speed File : -1 | |||
| | Design State : Fully Routed | |||
| ------------------------------------------------------------------------------------------------------------------------------------ | |||
| Report DRC | |||
| Table of Contents | |||
| ----------------- | |||
| 1. REPORT SUMMARY | |||
| 2. REPORT DETAILS | |||
| 1. REPORT SUMMARY | |||
| ----------------- | |||
| Netlist: netlist | |||
| Floorplan: design_1 | |||
| Design limits: <entire design considered> | |||
| Ruledeck: default | |||
| Max violations: <unlimited> | |||
| Violations found: 3 | |||
| +--------+------------------+----------------------------+------------+ | |||
| | Rule | Severity | Description | Violations | | |||
| +--------+------------------+----------------------------+------------+ | |||
| | NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | | |||
| | UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | | |||
| | ZPS7-1 | Warning | PS7 block required | 1 | | |||
| +--------+------------------+----------------------------+------------+ | |||
| 2. REPORT DETAILS | |||
| ----------------- | |||
| NSTD-1#1 Critical Warning | |||
| Unspecified I/O Standard | |||
| 43 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], c[8:-6]. | |||
| Related violations: <none> | |||
| UCIO-1#1 Critical Warning | |||
| Unconstrained Logical Port | |||
| 43 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a[7:-6], b[7:-6], c[8:-6]. | |||
| Related violations: <none> | |||
| ZPS7-1#1 Warning | |||
| PS7 block required | |||
| The PS7 cell must be used in this Zynq design in order to enable correct default configuration. | |||
| Related violations: <none> | |||
BIN
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| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| ------------------------------------------------------------------------------------------------- | |||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | |||
| | Date : Fri May 13 14:41:53 2022 | |||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | |||
| | Command : report_io -file fixedPointTest_io_placed.rpt | |||
| | Design : fixedPointTest | |||
| | Device : xc7z010 | |||
| | Speed File : -1 | |||
| | Package : clg400 | |||
| | Package Version : FINAL 2012-10-23 | |||
| | Package Pin Delay Version : VERS. 2.0 2012-10-23 | |||
| ------------------------------------------------------------------------------------------------- | |||
| IO Information | |||
| Table of Contents | |||
| ----------------- | |||
| 1. Summary | |||
| 2. IO Assignments by Package Pin | |||
| 1. Summary | |||
| ---------- | |||
| +---------------+ | |||
| | Total User IO | | |||
| +---------------+ | |||
| | 43 | | |||
| +---------------+ | |||
| 2. IO Assignments by Package Pin | |||
| -------------------------------- | |||
| +------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ | |||
| | Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | | |||
| +------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ | |||
| | A1 | | | PS_DDR_DM0_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A2 | | | PS_DDR_DQ2_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | A4 | | | PS_DDR_DQ3_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A5 | | | PS_MIO6_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A6 | | | PS_MIO5_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A7 | | | PS_MIO1_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | A9 | | | PS_MIO43_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A10 | | | PS_MIO37_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A11 | | | PS_MIO36_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A12 | | | PS_MIO34_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | A14 | | | PS_MIO32_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A15 | | | PS_MIO26_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A16 | | | PS_MIO24_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A17 | | | PS_MIO20_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | A19 | | | PS_MIO16_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | A20 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | B1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | B2 | | | PS_DDR_DQS_N0_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B3 | | | PS_DDR_DQ1_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B4 | | | PS_DDR_DRST_B_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B5 | | | PS_MIO9_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | B7 | | | PS_MIO4_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B8 | | | PS_MIO2_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B9 | | | PS_MIO51_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B10 | | | PS_SRST_B_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | B12 | | | PS_MIO48_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B13 | | | PS_MIO50_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B14 | | | PS_MIO47_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B15 | | | PS_MIO45_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B16 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | B17 | | | PS_MIO22_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B18 | | | PS_MIO18_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | B19 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | B20 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | C1 | | | PS_DDR_DQ6_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C2 | | | PS_DDR_DQS_P0_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C3 | | | PS_DDR_DQ0_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | C5 | | | PS_MIO14_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C6 | | | PS_MIO11_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C7 | | | PS_POR_B_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C8 | | | PS_MIO15_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | C10 | | | PS_MIO52_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C11 | | | PS_MIO53_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C12 | | | PS_MIO49_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C13 | | | PS_MIO29_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | C15 | | | PS_MIO30_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C16 | | | PS_MIO28_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C17 | | | PS_MIO41_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C18 | | | PS_MIO39_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | C19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | | |||
| | C20 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | D1 | | | PS_DDR_DQ5_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | D3 | | | PS_DDR_DQ4_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D4 | | | PS_DDR_A13_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D5 | | | PS_MIO8_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D6 | | | PS_MIO3_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | D8 | | | PS_MIO7_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D9 | | | PS_MIO12_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D10 | | | PS_MIO19_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D11 | | | PS_MIO23_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | D13 | | | PS_MIO27_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D14 | | | PS_MIO40_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D15 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D16 | | | PS_MIO46_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | D18 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | D20 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | E1 | | | PS_DDR_DQ7_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E2 | | | PS_DDR_DQ8_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E3 | | | PS_DDR_DQ9_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E4 | | | PS_DDR_A12_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | E6 | | | PS_MIO0_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E7 | | | PS_CLK_500 | PSS Clock | | | | | | | | | | | | | | | | | |||
| | E8 | | | PS_MIO13_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E9 | | | PS_MIO10_500 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | E11 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E12 | | | PS_MIO42_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E13 | | | PS_MIO38_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E14 | | | PS_MIO17_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E15 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | E16 | | | PS_MIO31_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | E17 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | E18 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | E19 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | F1 | | | PS_DDR_DM1_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | F2 | | | PS_DDR_DQS_N1_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | F4 | | | PS_DDR_A14_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | F5 | | | PS_DDR_A10_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | F6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | | |||
| | F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | F8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | | |||
| | F9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | | |||
| | F10 | | | RSVDGND | GND | | | | | | | | | | | | | | | | | |||
| | F11 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | | |||
| | F12 | | | PS_MIO35_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | F13 | | | PS_MIO44_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | F14 | | | PS_MIO21_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | F15 | | | PS_MIO25_501 | PSS IO | | | | | | | | | | | | | | | | | |||
| | F16 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | F17 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | F18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | | |||
| | F19 | | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | F20 | | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | G1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | G2 | | | PS_DDR_DQS_P1_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | G3 | | | PS_DDR_DQ10_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | G4 | | | PS_DDR_A11_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | G5 | | | PS_DDR_VRN_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | G6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | | |||
| | G7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | | |||
| | G8 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | | | | | |||
| | G9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | | |||
| | G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | | |||
| | G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | |||
| | G14 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | G15 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | G16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | G17 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | G18 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | G19 | | High Range | IO_L18P_T2_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | G20 | | High Range | IO_L18N_T2_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | H1 | | | PS_DDR_DQ14_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | H2 | | | PS_DDR_DQ13_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | H3 | | | PS_DDR_DQ11_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | H4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | H5 | | | PS_DDR_VRP_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | H6 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | H8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | | |||
| | H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | H10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | | |||
| | H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | H12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | |||
| | H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | H14 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | | |||
| | H15 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | H16 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | H17 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | H18 | | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | H19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | H20 | | High Range | IO_L17N_T2_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | J1 | | | PS_DDR_DQ15_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | J3 | | | PS_DDR_DQ12_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | J4 | | | PS_DDR_A9_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | J5 | | | PS_DDR_BA2_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | J6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | | |||
| | J7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | | |||
| | J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | J9 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | | |||
| | J10 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | | |||
| | J11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | | |||
| | J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | |||
| | J14 | | High Range | IO_L20N_T3_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | J15 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | J16 | | High Range | IO_L24N_T3_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | J17 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | | |||
| | J18 | | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | J19 | | High Range | IO_L10N_T1_AD11N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | J20 | | High Range | IO_L17P_T2_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | K1 | | | PS_DDR_A8_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | K2 | | | PS_DDR_A1_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | K3 | | | PS_DDR_A3_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | K4 | | | PS_DDR_A7_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | K6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | | |||
| | K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | K8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | | |||
| | K9 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | | |||
| | K10 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | | |||
| | K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | |||
| | K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | K14 | | High Range | IO_L20P_T3_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | K16 | | High Range | IO_L24P_T3_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | K17 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | K18 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | K19 | | High Range | IO_L10P_T1_AD11P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | K20 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | | |||
| | L1 | | | PS_DDR_A5_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | L2 | | | PS_DDR_CKP_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | L3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | L4 | | | PS_DDR_A6_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | L5 | | | PS_DDR_BA0_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | L6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | | |||
| | L7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | | |||
| | L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | L9 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | | |||
| | L10 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | | |||
| | L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | | |||
| | L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | |||
| | L14 | | High Range | IO_L22P_T3_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | L15 | | High Range | IO_L22N_T3_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | L16 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | L17 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | L18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | L19 | | High Range | IO_L9P_T1_DQS_AD3P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | L20 | | High Range | IO_L9N_T1_DQS_AD3N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | M1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | M2 | | | PS_DDR_CKN_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | M3 | | | PS_DDR_A2_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | M4 | | | PS_DDR_A4_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | M5 | | | PS_DDR_WE_B_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | M6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | | |||
| | M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | M8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | | |||
| | M9 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | | |||
| | M10 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | | |||
| | M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | |||
| | M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | M14 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | M15 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | | |||
| | M17 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | M18 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | M19 | | High Range | IO_L7P_T1_AD2P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | M20 | | High Range | IO_L7N_T1_AD2N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | N1 | | | PS_DDR_CS_B_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | N2 | | | PS_DDR_A0_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | N3 | | | PS_DDR_CKE_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | N4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | N5 | | | PS_DDR_ODT_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | N6 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | | | | | |||
| | N7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | | |||
| | N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | | |||
| | N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | N11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | | |||
| | N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | N13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | |||
| | N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | N15 | | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | N16 | | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | | |||
| | N17 | a[-2] | High Range | IO_L23P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | N18 | b[4] | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | N19 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | | |||
| | N20 | b[2] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | P1 | | | PS_DDR_DQ16_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | P2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | P3 | | | PS_DDR_DQ17_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | P4 | | | PS_DDR_RAS_B_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | P5 | | | PS_DDR_CAS_B_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | P6 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | P8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | | |||
| | P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | | |||
| | P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | P12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | |||
| | P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | P14 | c[4] | High Range | IO_L6P_T0_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | P15 | a[-4] | High Range | IO_L24P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | P16 | a[-5] | High Range | IO_L24N_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | P18 | a[-3] | High Range | IO_L23N_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | P19 | b[3] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | P20 | b[1] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | R1 | | | PS_DDR_DQ19_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | R2 | | | PS_DDR_DQS_P2_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | R3 | | | PS_DDR_DQ18_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | R4 | | | PS_DDR_BA1_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | R5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | R6 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | | | | | |||
| | R7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | | |||
| | R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | | |||
| | R10 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | | |||
| | R11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | | |||
| | R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | R13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | |||
| | R14 | c[3] | High Range | IO_L6N_T0_VREF_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | | |||
| | R16 | a[6] | High Range | IO_L19P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | R17 | a[5] | High Range | IO_L19N_T3_VREF_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | R18 | a[3] | High Range | IO_L20N_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | R19 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | | |||
| | R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | T1 | | | PS_DDR_DM2_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | T2 | | | PS_DDR_DQS_N2_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | T3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | T4 | | | PS_DDR_DQ20_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | T5 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | T6 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | | | | | |||
| | T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | T8 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | | |||
| | T9 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | T10 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | | |||
| | T11 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | | |||
| | T12 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | | |||
| | T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | T14 | c[6] | High Range | IO_L5P_T0_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | T15 | c[5] | High Range | IO_L5N_T0_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | T16 | c[-2] | High Range | IO_L9P_T1_DQS_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | T17 | a[4] | High Range | IO_L20P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | T18 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | | |||
| | T19 | a[-6] | High Range | IO_25_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | T20 | b[0] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | U1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | U2 | | | PS_DDR_DQ22_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | U3 | | | PS_DDR_DQ23_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | U4 | | | PS_DDR_DQ21_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | U5 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | U7 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | U8 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | U9 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | U10 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | U11 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | | |||
| | U12 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | | |||
| | U13 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | | | | | |||
| | U14 | c[-6] | High Range | IO_L11P_T1_SRCC_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | U15 | b[7] | High Range | IO_L11N_T1_SRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | U16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | U17 | c[-3] | High Range | IO_L9N_T1_DQS_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | U18 | b[6] | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | U19 | b[5] | High Range | IO_L12N_T1_MRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | U20 | b[-1] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | V1 | | | PS_DDR_DQ24_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | V2 | | | PS_DDR_DQ30_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | V3 | | | PS_DDR_DQ31_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | V4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | |||
| | V5 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | V6 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | V7 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | V8 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | V9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | V10 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | V11 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | V12 | c[8] | High Range | IO_L4P_T0_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | V13 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | | |||
| | V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | | |||
| | V15 | c[-4] | High Range | IO_L10P_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | V16 | b[-6] | High Range | IO_L18P_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | V17 | a[2] | High Range | IO_L21P_T3_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | V18 | a[1] | High Range | IO_L21N_T3_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | V19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | V20 | b[-2] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | W1 | | | PS_DDR_DQ26_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | W3 | | | PS_DDR_DQ29_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | W4 | | | PS_DDR_DQS_N3_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | W5 | | | PS_DDR_DQS_P3_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | W6 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | W7 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | | |||
| | W8 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | W9 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | W10 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | W11 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | W13 | c[7] | High Range | IO_L4N_T0_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | W14 | c[0] | High Range | IO_L8P_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | W15 | c[-5] | High Range | IO_L10N_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | W16 | a[7] | High Range | IO_L18N_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | W17 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | | |||
| | W18 | a[0] | High Range | IO_L22P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | W19 | a[-1] | High Range | IO_L22N_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | W20 | b[-3] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | Y1 | | | PS_DDR_DM3_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | Y2 | | | PS_DDR_DQ28_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | Y3 | | | PS_DDR_DQ25_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | Y4 | | | PS_DDR_DQ27_502 | PSS IO | | | | | | | | | | | | | | | | | |||
| | Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | Y6 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | Y7 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | Y8 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | Y9 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | Y10 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | | |||
| | Y11 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | Y12 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | Y13 | | | NC | Not Connected | | | | | | | | | | | | | | | | | |||
| | Y14 | c[-1] | High Range | IO_L8N_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | |||
| | Y16 | c[2] | High Range | IO_L7P_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | Y17 | c[1] | High Range | IO_L7N_T1_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | |||
| | Y18 | b[-4] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | Y19 | b[-5] | High Range | IO_L17N_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | | |||
| | Y20 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | | |||
| +------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ | |||
| * Default value | |||
| ** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. | |||
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| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | |||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | |||
| | Date : Fri May 13 14:42:10 2022 | |||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | |||
| | Command : report_methodology -file fixedPointTest_methodology_drc_routed.rpt -pb fixedPointTest_methodology_drc_routed.pb -rpx fixedPointTest_methodology_drc_routed.rpx | |||
| | Design : fixedPointTest | |||
| | Device : xc7z010clg400-1 | |||
| | Speed File : -1 | |||
| | Design State : Fully Routed | |||
| -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | |||
| Report Methodology | |||
| Table of Contents | |||
| ----------------- | |||
| 1. REPORT SUMMARY | |||
| 2. REPORT DETAILS | |||
| 1. REPORT SUMMARY | |||
| ----------------- | |||
| Netlist: netlist | |||
| Floorplan: design_1 | |||
| Design limits: <entire design considered> | |||
| Max violations: <unlimited> | |||
| Violations found: 0 | |||
| +------+----------+-------------+------------+ | |||
| | Rule | Severity | Description | Violations | | |||
| +------+----------+-------------+------------+ | |||
| +------+----------+-------------+------------+ | |||
| 2. REPORT DETAILS | |||
| ----------------- | |||
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| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| ---------------------------------------------------------------------------------------------------------------------------------------------------------------- | |||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | |||
| | Date : Fri May 13 14:42:10 2022 | |||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | |||
| | Command : report_power -file fixedPointTest_power_routed.rpt -pb fixedPointTest_power_summary_routed.pb -rpx fixedPointTest_power_routed.rpx | |||
| | Design : fixedPointTest | |||
| | Device : xc7z010clg400-1 | |||
| | Design State : routed | |||
| | Grade : commercial | |||
| | Process : typical | |||
| | Characterization : Production | |||
| ---------------------------------------------------------------------------------------------------------------------------------------------------------------- | |||
| Power Report | |||
| Table of Contents | |||
| ----------------- | |||
| 1. Summary | |||
| 1.1 On-Chip Components | |||
| 1.2 Power Supply Summary | |||
| 1.3 Confidence Level | |||
| 2. Settings | |||
| 2.1 Environment | |||
| 2.2 Clock Constraints | |||
| 3. Detailed Reports | |||
| 3.1 By Hierarchy | |||
| 1. Summary | |||
| ---------- | |||
| +--------------------------+----------------------------------+ | |||
| | Total On-Chip Power (W) | 10.945 (Junction temp exceeded!) | | |||
| | Design Power Budget (W) | Unspecified* | | |||
| | Power Budget Margin (W) | NA | | |||
| | Dynamic (W) | 10.198 | | |||
| | Device Static (W) | 0.747 | | |||
| | Effective TJA (C/W) | 11.5 | | |||
| | Max Ambient (C) | 0.0 | | |||
| | Junction Temperature (C) | 125.0 | | |||
| | Confidence Level | Low | | |||
| | Setting File | --- | | |||
| | Simulation Activity File | --- | | |||
| | Design Nets Matched | NA | | |||
| +--------------------------+----------------------------------+ | |||
| * Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts> | |||
| 1.1 On-Chip Components | |||
| ---------------------- | |||
| +----------------+-----------+----------+-----------+-----------------+ | |||
| | On-Chip | Power (W) | Used | Available | Utilization (%) | | |||
| +----------------+-----------+----------+-----------+-----------------+ | |||
| | Slice Logic | 0.051 | 21 | --- | --- | | |||
| | LUT as Logic | 0.032 | 14 | 17600 | 0.08 | | |||
| | CARRY4 | 0.019 | 4 | 4400 | 0.09 | | |||
| | Others | 0.000 | 2 | --- | --- | | |||
| | Signals | 0.294 | 46 | --- | --- | | |||
| | I/O | 9.853 | 43 | 100 | 43.00 | | |||
| | Static Power | 0.747 | | | | | |||
| | Total | 10.945 | | | | | |||
| +----------------+-----------+----------+-----------+-----------------+ | |||
| 1.2 Power Supply Summary | |||
| ------------------------ | |||
| +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | |||
| | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | | |||
| +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | |||
| | Vccint | 1.000 | 0.586 | 0.457 | 0.129 | NA | Unspecified | NA | | |||
| | Vccaux | 1.800 | 0.838 | 0.797 | 0.040 | NA | Unspecified | NA | | |||
| | Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | Vcco18 | 1.800 | 4.615 | 4.614 | 0.001 | NA | Unspecified | NA | | |||
| | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | Vccbram | 1.000 | 0.011 | 0.000 | 0.011 | NA | Unspecified | NA | | |||
| | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | Vccpint | 1.000 | 0.473 | 0.000 | 0.473 | NA | Unspecified | NA | | |||
| | Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | NA | Unspecified | NA | | |||
| | Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | NA | Unspecified | NA | | |||
| | Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | |||
| | Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | | |||
| +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | |||
| 1.3 Confidence Level | |||
| -------------------- | |||
| +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ | |||
| | User Input Data | Confidence | Details | Action | | |||
| +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ | |||
| | Design implementation state | High | Design is routed | | | |||
| | Clock nodes activity | High | User specified more than 95% of clocks | | | |||
| | I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | | |||
| | Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | | |||
| | Device models | High | Device models are Production | | | |||
| | | | | | | |||
| | Overall confidence level | Low | | | | |||
| +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ | |||
| 2. Settings | |||
| ----------- | |||
| 2.1 Environment | |||
| --------------- | |||
| +-----------------------+------------------------+ | |||
| | Ambient Temp (C) | 25.0 | | |||
| | ThetaJA (C/W) | 11.5 | | |||
| | Airflow (LFM) | 250 | | |||
| | Heat Sink | none | | |||
| | ThetaSA (C/W) | 0.0 | | |||
| | Board Selection | medium (10"x10") | | |||
| | # of Board Layers | 8to11 (8 to 11 Layers) | | |||
| | Board Temperature (C) | 25.0 | | |||
| +-----------------------+------------------------+ | |||
| 2.2 Clock Constraints | |||
| --------------------- | |||
| +-------+--------+-----------------+ | |||
| | Clock | Domain | Constraint (ns) | | |||
| +-------+--------+-----------------+ | |||
| 3. Detailed Reports | |||
| ------------------- | |||
| 3.1 By Hierarchy | |||
| ---------------- | |||
| +----------------+-----------+ | |||
| | Name | Power (W) | | |||
| +----------------+-----------+ | |||
| | fixedPointTest | 10.198 | | |||
| +----------------+-----------+ | |||
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| Design Route Status | |||
| : # nets : | |||
| ------------------------------------------- : ----------- : | |||
| # of logical nets.......................... : 106 : | |||
| # of nets not needing routing.......... : 58 : | |||
| # of internally routed nets........ : 58 : | |||
| # of routable nets..................... : 48 : | |||
| # of fully routed nets............. : 48 : | |||
| # of nets with routing errors.......... : 0 : | |||
| ------------------------------------------- : ----------- : | |||
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| 2012.4’)Timing analysis from Implemented netlist. | |||
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| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | |||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | |||
| | Date : Fri May 13 14:42:10 2022 | |||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | |||
| | Command : report_timing_summary -max_paths 10 -report_unconstrained -file fixedPointTest_timing_summary_routed.rpt -pb fixedPointTest_timing_summary_routed.pb -rpx fixedPointTest_timing_summary_routed.rpx -warn_on_violation | |||
| | Design : fixedPointTest | |||
| | Device : 7z010-clg400 | |||
| | Speed File : -1 PRODUCTION 1.12 2019-11-22 | |||
| --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | |||
| Timing Summary Report | |||
| ------------------------------------------------------------------------------------------------ | |||
| | Timer Settings | |||
| | -------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| Enable Multi Corner Analysis : Yes | |||
| Enable Pessimism Removal : Yes | |||
| Pessimism Removal Resolution : Nearest Common Node | |||
| Enable Input Delay Default Clock : No | |||
| Enable Preset / Clear Arcs : No | |||
| Disable Flight Delays : No | |||
| Ignore I/O Paths : No | |||
| Timing Early Launch at Borrowing Latches : No | |||
| Borrow Time for Max Delay Exceptions : Yes | |||
| Merge Timing Exceptions : Yes | |||
| Corner Analyze Analyze | |||
| Name Max Paths Min Paths | |||
| ------ --------- --------- | |||
| Slow Yes Yes | |||
| Fast Yes Yes | |||
| ------------------------------------------------------------------------------------------------ | |||
| | Report Methodology | |||
| | ------------------ | |||
| ------------------------------------------------------------------------------------------------ | |||
| Rule Severity Description Violations | |||
| ---- -------- ----------- ---------- | |||
| Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report. | |||
| check_timing report | |||
| Table of Contents | |||
| ----------------- | |||
| 1. checking no_clock (0) | |||
| 2. checking constant_clock (0) | |||
| 3. checking pulse_width_clock (0) | |||
| 4. checking unconstrained_internal_endpoints (0) | |||
| 5. checking no_input_delay (0) | |||
| 6. checking no_output_delay (0) | |||
| 7. checking multiple_clock (0) | |||
| 8. checking generated_clocks (0) | |||
| 9. checking loops (0) | |||
| 10. checking partial_input_delay (0) | |||
| 11. checking partial_output_delay (0) | |||
| 12. checking latch_loops (0) | |||
| 1. checking no_clock (0) | |||
| ------------------------ | |||
| There are 0 register/latch pins with no clock. | |||
| 2. checking constant_clock (0) | |||
| ------------------------------ | |||
| There are 0 register/latch pins with constant_clock. | |||
| 3. checking pulse_width_clock (0) | |||
| --------------------------------- | |||
| There are 0 register/latch pins which need pulse_width check | |||
| 4. checking unconstrained_internal_endpoints (0) | |||
| ------------------------------------------------ | |||
| There are 0 pins that are not constrained for maximum delay. | |||
| There are 0 pins that are not constrained for maximum delay due to constant clock. | |||
| 5. checking no_input_delay (0) | |||
| ------------------------------ | |||
| There are 0 input ports with no input delay specified. | |||
| There are 0 input ports with no input delay but user has a false path constraint. | |||
| 6. checking no_output_delay (0) | |||
| ------------------------------- | |||
| There are 0 ports with no output delay specified. | |||
| There are 0 ports with no output delay but user has a false path constraint | |||
| There are 0 ports with no output delay but with a timing clock defined on it or propagating through it | |||
| 7. checking multiple_clock (0) | |||
| ------------------------------ | |||
| There are 0 register/latch pins with multiple clocks. | |||
| 8. checking generated_clocks (0) | |||
| -------------------------------- | |||
| There are 0 generated clocks that are not connected to a clock source. | |||
| 9. checking loops (0) | |||
| --------------------- | |||
| There are 0 combinational loops in the design. | |||
| 10. checking partial_input_delay (0) | |||
| ------------------------------------ | |||
| There are 0 input ports with partial input delay specified. | |||
| 11. checking partial_output_delay (0) | |||
| ------------------------------------- | |||
| There are 0 ports with partial output delay specified. | |||
| 12. checking latch_loops (0) | |||
| ---------------------------- | |||
| There are 0 combinational latch loops in the design through latch input | |||
| ------------------------------------------------------------------------------------------------ | |||
| | Design Timing Summary | |||
| | --------------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints | |||
| ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- | |||
| inf 0.000 0 15 inf 0.000 0 15 NA NA NA NA | |||
| There are no user specified timing constraints. | |||
| ------------------------------------------------------------------------------------------------ | |||
| | Clock Summary | |||
| | ------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| ------------------------------------------------------------------------------------------------ | |||
| | Intra Clock Table | |||
| | ----------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints | |||
| ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| | Inter Clock Table | |||
| | ----------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints | |||
| ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| | Other Path Groups Table | |||
| | ----------------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints | |||
| ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| | User Ignored Path Table | |||
| | ----------------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| Path Group From Clock To Clock | |||
| ---------- ---------- -------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| | Unconstrained Path Table | |||
| | ------------------------ | |||
| ------------------------------------------------------------------------------------------------ | |||
| Path Group From Clock To Clock | |||
| ---------- ---------- -------- | |||
| (none) | |||
| ------------------------------------------------------------------------------------------------ | |||
| | Timing Details | |||
| | -------------- | |||
| ------------------------------------------------------------------------------------------------ | |||
| -------------------------------------------------------------------------------------- | |||
| Path Group: (none) | |||
| From Clock: | |||
| To Clock: | |||
| Max Delay 15 Endpoints | |||
| Min Delay 15 Endpoints | |||
| -------------------------------------------------------------------------------------- | |||
| Max Delay Paths | |||
| -------------------------------------------------------------------------------------- | |||
| Slack: inf | |||
| Source: a[-3] | |||
| (input port) | |||
| Destination: c[7] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Max at Slow Process Corner | |||
| Data Path Delay: 9.462ns (logic 4.925ns (52.050%) route 4.537ns (47.950%)) | |||
| Logic Levels: 7 (CARRY4=4 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| P18 0.000 0.000 r a[-3] (IN) | |||
| net (fo=0) 0.000 0.000 a[-3] | |||
| P18 IBUF (Prop_ibuf_I_O) 0.972 0.972 r a_IBUF[-3]_inst/O | |||
| net (fo=2, routed) 2.100 3.072 a_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I0_O) 0.124 3.196 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 3.196 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) | |||
| 0.401 3.597 r c_OBUF[-3]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.597 c_OBUF[-3]_inst_i_1_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_CI_CO[3]) | |||
| 0.114 3.711 r c_OBUF[1]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.711 c_OBUF[1]_inst_i_1_n_0 | |||
| SLICE_X43Y20 CARRY4 (Prop_carry4_CI_CO[3]) | |||
| 0.114 3.825 r c_OBUF[5]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.825 c_OBUF[5]_inst_i_1_n_0 | |||
| SLICE_X43Y21 CARRY4 (Prop_carry4_CI_O[1]) | |||
| 0.334 4.159 r c_OBUF[8]_inst_i_1/O[1] | |||
| net (fo=1, routed) 2.437 6.596 c_OBUF[7] | |||
| W13 OBUF (Prop_obuf_I_O) 2.866 9.462 r c_OBUF[7]_inst/O | |||
| net (fo=0) 0.000 9.462 c[7] | |||
| W13 r c[7] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[-3] | |||
| (input port) | |||
| Destination: c[8] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Max at Slow Process Corner | |||
| Data Path Delay: 9.266ns (logic 4.823ns (52.047%) route 4.443ns (47.953%)) | |||
| Logic Levels: 7 (CARRY4=4 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| P18 0.000 0.000 r a[-3] (IN) | |||
| net (fo=0) 0.000 0.000 a[-3] | |||
| P18 IBUF (Prop_ibuf_I_O) 0.972 0.972 r a_IBUF[-3]_inst/O | |||
| net (fo=2, routed) 2.100 3.072 a_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I0_O) 0.124 3.196 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 3.196 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) | |||
| 0.401 3.597 r c_OBUF[-3]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.597 c_OBUF[-3]_inst_i_1_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_CI_CO[3]) | |||
| 0.114 3.711 r c_OBUF[1]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.711 c_OBUF[1]_inst_i_1_n_0 | |||
| SLICE_X43Y20 CARRY4 (Prop_carry4_CI_CO[3]) | |||
| 0.114 3.825 r c_OBUF[5]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.825 c_OBUF[5]_inst_i_1_n_0 | |||
| SLICE_X43Y21 CARRY4 (Prop_carry4_CI_O[2]) | |||
| 0.239 4.064 r c_OBUF[8]_inst_i_1/O[2] | |||
| net (fo=1, routed) 2.343 6.407 c_OBUF[8] | |||
| V12 OBUF (Prop_obuf_I_O) 2.858 9.266 r c_OBUF[8]_inst/O | |||
| net (fo=0) 0.000 9.266 c[8] | |||
| V12 r c[8] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[-3] | |||
| (input port) | |||
| Destination: c[6] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Max at Slow Process Corner | |||
| Data Path Delay: 9.175ns (logic 4.778ns (52.082%) route 4.396ns (47.918%)) | |||
| Logic Levels: 7 (CARRY4=4 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| P18 0.000 0.000 r a[-3] (IN) | |||
| net (fo=0) 0.000 0.000 a[-3] | |||
| P18 IBUF (Prop_ibuf_I_O) 0.972 0.972 r a_IBUF[-3]_inst/O | |||
| net (fo=2, routed) 2.100 3.072 a_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I0_O) 0.124 3.196 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 3.196 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) | |||
| 0.401 3.597 r c_OBUF[-3]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.597 c_OBUF[-3]_inst_i_1_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_CI_CO[3]) | |||
| 0.114 3.711 r c_OBUF[1]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.711 c_OBUF[1]_inst_i_1_n_0 | |||
| SLICE_X43Y20 CARRY4 (Prop_carry4_CI_CO[3]) | |||
| 0.114 3.825 r c_OBUF[5]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.825 c_OBUF[5]_inst_i_1_n_0 | |||
| SLICE_X43Y21 CARRY4 (Prop_carry4_CI_O[0]) | |||
| 0.222 4.047 r c_OBUF[8]_inst_i_1/O[0] | |||
| net (fo=1, routed) 2.296 6.343 c_OBUF[6] | |||
| T14 OBUF (Prop_obuf_I_O) 2.831 9.175 r c_OBUF[6]_inst/O | |||
| net (fo=0) 0.000 9.175 c[6] | |||
| T14 r c[6] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[-3] | |||
| (input port) | |||
| Destination: c[3] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Max at Slow Process Corner | |||
| Data Path Delay: 9.173ns (logic 4.784ns (52.155%) route 4.389ns (47.845%)) | |||
| Logic Levels: 6 (CARRY4=3 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| P18 0.000 0.000 r a[-3] (IN) | |||
| net (fo=0) 0.000 0.000 a[-3] | |||
| P18 IBUF (Prop_ibuf_I_O) 0.972 0.972 r a_IBUF[-3]_inst/O | |||
| net (fo=2, routed) 2.100 3.072 a_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I0_O) 0.124 3.196 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 3.196 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) | |||
| 0.401 3.597 r c_OBUF[-3]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.597 c_OBUF[-3]_inst_i_1_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_CI_CO[3]) | |||
| 0.114 3.711 r c_OBUF[1]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.711 c_OBUF[1]_inst_i_1_n_0 | |||
| SLICE_X43Y20 CARRY4 (Prop_carry4_CI_O[1]) | |||
| 0.334 4.045 r c_OBUF[5]_inst_i_1/O[1] | |||
| net (fo=1, routed) 2.289 6.334 c_OBUF[3] | |||
| R14 OBUF (Prop_obuf_I_O) 2.839 9.173 r c_OBUF[3]_inst/O | |||
| net (fo=0) 0.000 9.173 c[3] | |||
| R14 r c[3] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[-3] | |||
| (input port) | |||
| Destination: c[5] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Max at Slow Process Corner | |||
| Data Path Delay: 9.153ns (logic 4.765ns (52.061%) route 4.388ns (47.939%)) | |||
| Logic Levels: 6 (CARRY4=3 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| P18 0.000 0.000 r a[-3] (IN) | |||
| net (fo=0) 0.000 0.000 a[-3] | |||
| P18 IBUF (Prop_ibuf_I_O) 0.972 0.972 r a_IBUF[-3]_inst/O | |||
| net (fo=2, routed) 2.100 3.072 a_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I0_O) 0.124 3.196 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 3.196 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) | |||
| 0.401 3.597 r c_OBUF[-3]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.597 c_OBUF[-3]_inst_i_1_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_CI_CO[3]) | |||
| 0.114 3.711 r c_OBUF[1]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.711 c_OBUF[1]_inst_i_1_n_0 | |||
| SLICE_X43Y20 CARRY4 (Prop_carry4_CI_O[3]) | |||
| 0.313 4.024 r c_OBUF[5]_inst_i_1/O[3] | |||
| net (fo=1, routed) 2.288 6.312 c_OBUF[5] | |||
| T15 OBUF (Prop_obuf_I_O) 2.841 9.153 r c_OBUF[5]_inst/O | |||
| net (fo=0) 0.000 9.153 c[5] | |||
| T15 r c[5] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[-3] | |||
| (input port) | |||
| Destination: c[1] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Max at Slow Process Corner | |||
| Data Path Delay: 9.090ns (logic 4.700ns (51.703%) route 4.390ns (48.297%)) | |||
| Logic Levels: 5 (CARRY4=2 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| P18 0.000 0.000 r a[-3] (IN) | |||
| net (fo=0) 0.000 0.000 a[-3] | |||
| P18 IBUF (Prop_ibuf_I_O) 0.972 0.972 r a_IBUF[-3]_inst/O | |||
| net (fo=2, routed) 2.100 3.072 a_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I0_O) 0.124 3.196 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 3.196 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) | |||
| 0.401 3.597 r c_OBUF[-3]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.597 c_OBUF[-3]_inst_i_1_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_CI_O[3]) | |||
| 0.313 3.910 r c_OBUF[1]_inst_i_1/O[3] | |||
| net (fo=1, routed) 2.290 6.201 c_OBUF[1] | |||
| Y17 OBUF (Prop_obuf_I_O) 2.890 9.090 r c_OBUF[1]_inst/O | |||
| net (fo=0) 0.000 9.090 c[1] | |||
| Y17 r c[1] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[-3] | |||
| (input port) | |||
| Destination: c[-1] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Max at Slow Process Corner | |||
| Data Path Delay: 9.079ns (logic 4.743ns (52.242%) route 4.336ns (47.758%)) | |||
| Logic Levels: 5 (CARRY4=2 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| P18 0.000 0.000 r a[-3] (IN) | |||
| net (fo=0) 0.000 0.000 a[-3] | |||
| P18 IBUF (Prop_ibuf_I_O) 0.972 0.972 r a_IBUF[-3]_inst/O | |||
| net (fo=2, routed) 2.100 3.072 a_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I0_O) 0.124 3.196 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 3.196 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) | |||
| 0.401 3.597 r c_OBUF[-3]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.597 c_OBUF[-3]_inst_i_1_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_CI_O[1]) | |||
| 0.334 3.931 r c_OBUF[1]_inst_i_1/O[1] | |||
| net (fo=1, routed) 2.236 6.167 c_OBUF[-1] | |||
| Y14 OBUF (Prop_obuf_I_O) 2.912 9.079 r c_OBUF[-1]_inst/O | |||
| net (fo=0) 0.000 9.079 c[-1] | |||
| Y14 r c[-1] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[-3] | |||
| (input port) | |||
| Destination: c[4] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Max at Slow Process Corner | |||
| Data Path Delay: 9.079ns (logic 4.693ns (51.693%) route 4.386ns (48.307%)) | |||
| Logic Levels: 6 (CARRY4=3 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| P18 0.000 0.000 r a[-3] (IN) | |||
| net (fo=0) 0.000 0.000 a[-3] | |||
| P18 IBUF (Prop_ibuf_I_O) 0.972 0.972 r a_IBUF[-3]_inst/O | |||
| net (fo=2, routed) 2.100 3.072 a_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I0_O) 0.124 3.196 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 3.196 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) | |||
| 0.401 3.597 r c_OBUF[-3]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.597 c_OBUF[-3]_inst_i_1_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_CI_CO[3]) | |||
| 0.114 3.711 r c_OBUF[1]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.711 c_OBUF[1]_inst_i_1_n_0 | |||
| SLICE_X43Y20 CARRY4 (Prop_carry4_CI_O[2]) | |||
| 0.239 3.950 r c_OBUF[5]_inst_i_1/O[2] | |||
| net (fo=1, routed) 2.286 6.236 c_OBUF[4] | |||
| P14 OBUF (Prop_obuf_I_O) 2.843 9.079 r c_OBUF[4]_inst/O | |||
| net (fo=0) 0.000 9.079 c[4] | |||
| P14 r c[4] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[-3] | |||
| (input port) | |||
| Destination: c[2] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Max at Slow Process Corner | |||
| Data Path Delay: 8.971ns (logic 4.723ns (52.647%) route 4.248ns (47.353%)) | |||
| Logic Levels: 6 (CARRY4=3 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| P18 0.000 0.000 r a[-3] (IN) | |||
| net (fo=0) 0.000 0.000 a[-3] | |||
| P18 IBUF (Prop_ibuf_I_O) 0.972 0.972 r a_IBUF[-3]_inst/O | |||
| net (fo=2, routed) 2.100 3.072 a_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I0_O) 0.124 3.196 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 3.196 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) | |||
| 0.401 3.597 r c_OBUF[-3]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.597 c_OBUF[-3]_inst_i_1_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_CI_CO[3]) | |||
| 0.114 3.711 r c_OBUF[1]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.711 c_OBUF[1]_inst_i_1_n_0 | |||
| SLICE_X43Y20 CARRY4 (Prop_carry4_CI_O[0]) | |||
| 0.222 3.933 r c_OBUF[5]_inst_i_1/O[0] | |||
| net (fo=1, routed) 2.148 6.081 c_OBUF[2] | |||
| Y16 OBUF (Prop_obuf_I_O) 2.890 8.971 r c_OBUF[2]_inst/O | |||
| net (fo=0) 0.000 8.971 c[2] | |||
| Y16 r c[2] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[-3] | |||
| (input port) | |||
| Destination: c[0] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Max at Slow Process Corner | |||
| Data Path Delay: 8.884ns (logic 4.645ns (52.282%) route 4.239ns (47.718%)) | |||
| Logic Levels: 5 (CARRY4=2 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| P18 0.000 0.000 r a[-3] (IN) | |||
| net (fo=0) 0.000 0.000 a[-3] | |||
| P18 IBUF (Prop_ibuf_I_O) 0.972 0.972 r a_IBUF[-3]_inst/O | |||
| net (fo=2, routed) 2.100 3.072 a_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I0_O) 0.124 3.196 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 3.196 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_CO[3]) | |||
| 0.401 3.597 r c_OBUF[-3]_inst_i_1/CO[3] | |||
| net (fo=1, routed) 0.000 3.597 c_OBUF[-3]_inst_i_1_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_CI_O[2]) | |||
| 0.239 3.836 r c_OBUF[1]_inst_i_1/O[2] | |||
| net (fo=1, routed) 2.139 5.975 c_OBUF[0] | |||
| W14 OBUF (Prop_obuf_I_O) 2.909 8.884 r c_OBUF[0]_inst/O | |||
| net (fo=0) 0.000 8.884 c[0] | |||
| W14 r c[0] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Min Delay Paths | |||
| -------------------------------------------------------------------------------------- | |||
| Slack: inf | |||
| Source: b[-3] | |||
| (input port) | |||
| Destination: c[-3] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Min at Fast Process Corner | |||
| Data Path Delay: 2.431ns (logic 1.568ns (64.485%) route 0.863ns (35.515%)) | |||
| Logic Levels: 4 (CARRY4=1 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| W20 0.000 0.000 r b[-3] (IN) | |||
| net (fo=0) 0.000 0.000 b[-3] | |||
| W20 IBUF (Prop_ibuf_I_O) 0.206 0.206 r b_IBUF[-3]_inst/O | |||
| net (fo=1, routed) 0.329 0.534 b_IBUF[-3] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I1_O) 0.045 0.579 r c_OBUF[-3]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 0.579 c_OBUF[-3]_inst_i_2_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[3]_O[3]) | |||
| 0.063 0.642 r c_OBUF[-3]_inst_i_1/O[3] | |||
| net (fo=1, routed) 0.535 1.177 c_OBUF[-3] | |||
| U17 OBUF (Prop_obuf_I_O) 1.254 2.431 r c_OBUF[-3]_inst/O | |||
| net (fo=0) 0.000 2.431 c[-3] | |||
| U17 r c[-3] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: b[-5] | |||
| (input port) | |||
| Destination: c[-5] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Min at Fast Process Corner | |||
| Data Path Delay: 2.505ns (logic 1.604ns (64.018%) route 0.901ns (35.982%)) | |||
| Logic Levels: 4 (CARRY4=1 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Y19 0.000 0.000 r b[-5] (IN) | |||
| net (fo=0) 0.000 0.000 b[-5] | |||
| Y19 IBUF (Prop_ibuf_I_O) 0.205 0.205 r b_IBUF[-5]_inst/O | |||
| net (fo=1, routed) 0.375 0.580 b_IBUF[-5] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I1_O) 0.045 0.625 r c_OBUF[-3]_inst_i_4/O | |||
| net (fo=1, routed) 0.000 0.625 c_OBUF[-3]_inst_i_4_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[1]_O[1]) | |||
| 0.065 0.690 r c_OBUF[-3]_inst_i_1/O[1] | |||
| net (fo=1, routed) 0.527 1.217 c_OBUF[-5] | |||
| W15 OBUF (Prop_obuf_I_O) 1.288 2.505 r c_OBUF[-5]_inst/O | |||
| net (fo=0) 0.000 2.505 c[-5] | |||
| W15 r c[-5] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: b[-6] | |||
| (input port) | |||
| Destination: c[-6] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Min at Fast Process Corner | |||
| Data Path Delay: 2.520ns (logic 1.587ns (62.965%) route 0.933ns (37.035%)) | |||
| Logic Levels: 4 (CARRY4=1 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| V16 0.000 0.000 r b[-6] (IN) | |||
| net (fo=0) 0.000 0.000 b[-6] | |||
| V16 IBUF (Prop_ibuf_I_O) 0.185 0.185 r b_IBUF[-6]_inst/O | |||
| net (fo=1, routed) 0.461 0.646 b_IBUF[-6] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I1_O) 0.045 0.691 r c_OBUF[-3]_inst_i_5/O | |||
| net (fo=1, routed) 0.000 0.691 c_OBUF[-3]_inst_i_5_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[0]_O[0]) | |||
| 0.070 0.761 r c_OBUF[-3]_inst_i_1/O[0] | |||
| net (fo=1, routed) 0.473 1.233 c_OBUF[-6] | |||
| U14 OBUF (Prop_obuf_I_O) 1.287 2.520 r c_OBUF[-6]_inst/O | |||
| net (fo=0) 0.000 2.520 c[-6] | |||
| U14 r c[-6] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: b[-2] | |||
| (input port) | |||
| Destination: c[-2] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Min at Fast Process Corner | |||
| Data Path Delay: 2.529ns (logic 1.573ns (62.198%) route 0.956ns (37.802%)) | |||
| Logic Levels: 4 (CARRY4=1 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| V20 0.000 0.000 r b[-2] (IN) | |||
| net (fo=0) 0.000 0.000 b[-2] | |||
| V20 IBUF (Prop_ibuf_I_O) 0.204 0.204 r b_IBUF[-2]_inst/O | |||
| net (fo=1, routed) 0.419 0.622 b_IBUF[-2] | |||
| SLICE_X43Y19 LUT2 (Prop_lut2_I1_O) 0.045 0.667 r c_OBUF[1]_inst_i_5/O | |||
| net (fo=1, routed) 0.000 0.667 c_OBUF[1]_inst_i_5_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_S[0]_O[0]) | |||
| 0.070 0.737 r c_OBUF[1]_inst_i_1/O[0] | |||
| net (fo=1, routed) 0.537 1.275 c_OBUF[-2] | |||
| T16 OBUF (Prop_obuf_I_O) 1.254 2.529 r c_OBUF[-2]_inst/O | |||
| net (fo=0) 0.000 2.529 c[-2] | |||
| T16 r c[-2] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: b[-1] | |||
| (input port) | |||
| Destination: c[-1] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Min at Fast Process Corner | |||
| Data Path Delay: 2.576ns (logic 1.613ns (62.626%) route 0.963ns (37.374%)) | |||
| Logic Levels: 4 (CARRY4=1 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| U20 0.000 0.000 r b[-1] (IN) | |||
| net (fo=0) 0.000 0.000 b[-1] | |||
| U20 IBUF (Prop_ibuf_I_O) 0.193 0.193 r b_IBUF[-1]_inst/O | |||
| net (fo=1, routed) 0.375 0.567 b_IBUF[-1] | |||
| SLICE_X43Y19 LUT2 (Prop_lut2_I1_O) 0.045 0.612 r c_OBUF[1]_inst_i_4/O | |||
| net (fo=1, routed) 0.000 0.612 c_OBUF[1]_inst_i_4_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_S[1]_O[1]) | |||
| 0.065 0.677 r c_OBUF[1]_inst_i_1/O[1] | |||
| net (fo=1, routed) 0.588 1.265 c_OBUF[-1] | |||
| Y14 OBUF (Prop_obuf_I_O) 1.311 2.576 r c_OBUF[-1]_inst/O | |||
| net (fo=0) 0.000 2.576 c[-1] | |||
| Y14 r c[-1] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: b[0] | |||
| (input port) | |||
| Destination: c[0] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Min at Fast Process Corner | |||
| Data Path Delay: 2.593ns (logic 1.617ns (62.342%) route 0.977ns (37.658%)) | |||
| Logic Levels: 4 (CARRY4=1 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| T20 0.000 0.000 r b[0] (IN) | |||
| net (fo=0) 0.000 0.000 b[0] | |||
| T20 IBUF (Prop_ibuf_I_O) 0.196 0.196 r b_IBUF[0]_inst/O | |||
| net (fo=1, routed) 0.420 0.616 b_IBUF[0] | |||
| SLICE_X43Y19 LUT2 (Prop_lut2_I1_O) 0.045 0.661 r c_OBUF[1]_inst_i_3/O | |||
| net (fo=1, routed) 0.000 0.661 c_OBUF[1]_inst_i_3_n_0 | |||
| SLICE_X43Y19 CARRY4 (Prop_carry4_S[2]_O[2]) | |||
| 0.066 0.727 r c_OBUF[1]_inst_i_1/O[2] | |||
| net (fo=1, routed) 0.557 1.284 c_OBUF[0] | |||
| W14 OBUF (Prop_obuf_I_O) 1.309 2.593 r c_OBUF[0]_inst/O | |||
| net (fo=0) 0.000 2.593 c[0] | |||
| W14 r c[0] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[5] | |||
| (input port) | |||
| Destination: c[5] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Min at Fast Process Corner | |||
| Data Path Delay: 2.595ns (logic 1.510ns (58.186%) route 1.085ns (41.814%)) | |||
| Logic Levels: 4 (CARRY4=1 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| R17 0.000 0.000 r a[5] (IN) | |||
| net (fo=0) 0.000 0.000 a[5] | |||
| R17 IBUF (Prop_ibuf_I_O) 0.161 0.161 r a_IBUF[5]_inst/O | |||
| net (fo=2, routed) 0.467 0.628 a_IBUF[5] | |||
| SLICE_X43Y20 LUT2 (Prop_lut2_I0_O) 0.045 0.673 r c_OBUF[5]_inst_i_2/O | |||
| net (fo=1, routed) 0.000 0.673 c_OBUF[5]_inst_i_2_n_0 | |||
| SLICE_X43Y20 CARRY4 (Prop_carry4_S[3]_O[3]) | |||
| 0.063 0.736 r c_OBUF[5]_inst_i_1/O[3] | |||
| net (fo=1, routed) 0.618 1.354 c_OBUF[5] | |||
| T15 OBUF (Prop_obuf_I_O) 1.241 2.595 r c_OBUF[5]_inst/O | |||
| net (fo=0) 0.000 2.595 c[5] | |||
| T15 r c[5] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: b[-5] | |||
| (input port) | |||
| Destination: c[-4] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Min at Fast Process Corner | |||
| Data Path Delay: 2.603ns (logic 1.698ns (65.228%) route 0.905ns (34.772%)) | |||
| Logic Levels: 4 (CARRY4=1 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Y19 0.000 0.000 r b[-5] (IN) | |||
| net (fo=0) 0.000 0.000 b[-5] | |||
| Y19 IBUF (Prop_ibuf_I_O) 0.205 0.205 r b_IBUF[-5]_inst/O | |||
| net (fo=1, routed) 0.375 0.580 b_IBUF[-5] | |||
| SLICE_X43Y18 LUT2 (Prop_lut2_I1_O) 0.045 0.625 r c_OBUF[-3]_inst_i_4/O | |||
| net (fo=1, routed) 0.000 0.625 c_OBUF[-3]_inst_i_4_n_0 | |||
| SLICE_X43Y18 CARRY4 (Prop_carry4_S[1]_O[2]) | |||
| 0.152 0.777 r c_OBUF[-3]_inst_i_1/O[2] | |||
| net (fo=1, routed) 0.531 1.307 c_OBUF[-4] | |||
| V15 OBUF (Prop_obuf_I_O) 1.296 2.603 r c_OBUF[-4]_inst/O | |||
| net (fo=0) 0.000 2.603 c[-4] | |||
| V15 r c[-4] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: b[2] | |||
| (input port) | |||
| Destination: c[2] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Min at Fast Process Corner | |||
| Data Path Delay: 2.608ns (logic 1.615ns (61.934%) route 0.993ns (38.066%)) | |||
| Logic Levels: 4 (CARRY4=1 IBUF=1 LUT2=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| N20 0.000 0.000 r b[2] (IN) | |||
| net (fo=0) 0.000 0.000 b[2] | |||
| N20 IBUF (Prop_ibuf_I_O) 0.208 0.208 r b_IBUF[2]_inst/O | |||
| net (fo=1, routed) 0.435 0.643 b_IBUF[2] | |||
| SLICE_X43Y20 LUT2 (Prop_lut2_I1_O) 0.045 0.688 r c_OBUF[5]_inst_i_5/O | |||
| net (fo=1, routed) 0.000 0.688 c_OBUF[5]_inst_i_5_n_0 | |||
| SLICE_X43Y20 CARRY4 (Prop_carry4_S[0]_O[0]) | |||
| 0.070 0.758 r c_OBUF[5]_inst_i_1/O[0] | |||
| net (fo=1, routed) 0.558 1.316 c_OBUF[2] | |||
| Y16 OBUF (Prop_obuf_I_O) 1.293 2.608 r c_OBUF[2]_inst/O | |||
| net (fo=0) 0.000 2.608 c[2] | |||
| Y16 r c[2] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
| Slack: inf | |||
| Source: a[2] | |||
| (input port) | |||
| Destination: c[3] | |||
| (output port) | |||
| Path Group: (none) | |||
| Path Type: Min at Fast Process Corner | |||
| Data Path Delay: 2.631ns (logic 1.552ns (58.994%) route 1.079ns (41.006%)) | |||
| Logic Levels: 3 (CARRY4=1 IBUF=1 OBUF=1) | |||
| Location Delay type Incr(ns) Path(ns) Netlist Resource(s) | |||
| ------------------------------------------------------------------- ------------------- | |||
| V17 0.000 0.000 r a[2] (IN) | |||
| net (fo=0) 0.000 0.000 a[2] | |||
| V17 IBUF (Prop_ibuf_I_O) 0.190 0.190 r a_IBUF[2]_inst/O | |||
| net (fo=2, routed) 0.467 0.657 a_IBUF[2] | |||
| SLICE_X43Y20 CARRY4 (Prop_carry4_DI[0]_O[1]) | |||
| 0.124 0.781 r c_OBUF[5]_inst_i_1/O[1] | |||
| net (fo=1, routed) 0.612 1.393 c_OBUF[3] | |||
| R14 OBUF (Prop_obuf_I_O) 1.239 2.631 r c_OBUF[3]_inst/O | |||
| net (fo=0) 0.000 2.631 c[3] | |||
| R14 r c[3] (OUT) | |||
| ------------------------------------------------------------------- ------------------- | |||
BIN
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_timing_summary_routed.rpx
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BIN
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_utilization_placed.pb
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+ 199
- 0
StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_utilization_placed.rpt
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| @@ -0,0 +1,199 @@ | |||
| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | |||
| | Date : Fri May 13 14:41:53 2022 | |||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | |||
| | Command : report_utilization -file fixedPointTest_utilization_placed.rpt -pb fixedPointTest_utilization_placed.pb | |||
| | Design : fixedPointTest | |||
| | Device : xc7z010clg400-1 | |||
| | Speed File : -1 | |||
| | Design State : Fully Placed | |||
| ------------------------------------------------------------------------------------------------------------------------- | |||
| Utilization Design Information | |||
| Table of Contents | |||
| ----------------- | |||
| 1. Slice Logic | |||
| 1.1 Summary of Registers by Type | |||
| 2. Slice Logic Distribution | |||
| 3. Memory | |||
| 4. DSP | |||
| 5. IO and GT Specific | |||
| 6. Clocking | |||
| 7. Specific Feature | |||
| 8. Primitives | |||
| 9. Black Boxes | |||
| 10. Instantiated Netlists | |||
| 1. Slice Logic | |||
| -------------- | |||
| +-------------------------+------+-------+------------+-----------+-------+ | |||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | |||
| +-------------------------+------+-------+------------+-----------+-------+ | |||
| | Slice LUTs | 14 | 0 | 0 | 17600 | 0.08 | | |||
| | LUT as Logic | 14 | 0 | 0 | 17600 | 0.08 | | |||
| | LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 | | |||
| | Slice Registers | 0 | 0 | 0 | 35200 | 0.00 | | |||
| | Register as Flip Flop | 0 | 0 | 0 | 35200 | 0.00 | | |||
| | Register as Latch | 0 | 0 | 0 | 35200 | 0.00 | | |||
| | F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 | | |||
| | F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 | | |||
| +-------------------------+------+-------+------------+-----------+-------+ | |||
| 1.1 Summary of Registers by Type | |||
| -------------------------------- | |||
| +-------+--------------+-------------+--------------+ | |||
| | Total | Clock Enable | Synchronous | Asynchronous | | |||
| +-------+--------------+-------------+--------------+ | |||
| | 0 | _ | - | - | | |||
| | 0 | _ | - | Set | | |||
| | 0 | _ | - | Reset | | |||
| | 0 | _ | Set | - | | |||
| | 0 | _ | Reset | - | | |||
| | 0 | Yes | - | - | | |||
| | 0 | Yes | - | Set | | |||
| | 0 | Yes | - | Reset | | |||
| | 0 | Yes | Set | - | | |||
| | 0 | Yes | Reset | - | | |||
| +-------+--------------+-------------+--------------+ | |||
| 2. Slice Logic Distribution | |||
| --------------------------- | |||
| +------------------------------------------+------+-------+------------+-----------+-------+ | |||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | |||
| +------------------------------------------+------+-------+------------+-----------+-------+ | |||
| | Slice | 4 | 0 | 0 | 4400 | 0.09 | | |||
| | SLICEL | 4 | 0 | | | | | |||
| | SLICEM | 0 | 0 | | | | | |||
| | LUT as Logic | 14 | 0 | 0 | 17600 | 0.08 | | |||
| | using O5 output only | 0 | | | | | | |||
| | using O6 output only | 13 | | | | | | |||
| | using O5 and O6 | 1 | | | | | | |||
| | LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 | | |||
| | LUT as Distributed RAM | 0 | 0 | | | | | |||
| | LUT as Shift Register | 0 | 0 | | | | | |||
| | Slice Registers | 0 | 0 | 0 | 35200 | 0.00 | | |||
| | Register driven from within the Slice | 0 | | | | | | |||
| | Register driven from outside the Slice | 0 | | | | | | |||
| | Unique Control Sets | 0 | | 0 | 4400 | 0.00 | | |||
| +------------------------------------------+------+-------+------------+-----------+-------+ | |||
| * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. | |||
| 3. Memory | |||
| --------- | |||
| +----------------+------+-------+------------+-----------+-------+ | |||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | |||
| +----------------+------+-------+------------+-----------+-------+ | |||
| | Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 | | |||
| | RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 | | |||
| | RAMB18 | 0 | 0 | 0 | 120 | 0.00 | | |||
| +----------------+------+-------+------------+-----------+-------+ | |||
| * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 | |||
| 4. DSP | |||
| ------ | |||
| +-----------+------+-------+------------+-----------+-------+ | |||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | |||
| +-----------+------+-------+------------+-----------+-------+ | |||
| | DSPs | 0 | 0 | 0 | 80 | 0.00 | | |||
| +-----------+------+-------+------------+-----------+-------+ | |||
| 5. IO and GT Specific | |||
| --------------------- | |||
| +-----------------------------+------+-------+------------+-----------+-------+ | |||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | |||
| +-----------------------------+------+-------+------------+-----------+-------+ | |||
| | Bonded IOB | 43 | 0 | 0 | 100 | 43.00 | | |||
| | IOB Master Pads | 21 | | | | | | |||
| | IOB Slave Pads | 21 | | | | | | |||
| | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | | |||
| | Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 | | |||
| | PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 | | |||
| | PHASER_REF | 0 | 0 | 0 | 2 | 0.00 | | |||
| | OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 | | |||
| | IN_FIFO | 0 | 0 | 0 | 8 | 0.00 | | |||
| | IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 | | |||
| | IBUFDS | 0 | 0 | 0 | 96 | 0.00 | | |||
| | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 | | |||
| | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 | | |||
| | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 | | |||
| | ILOGIC | 0 | 0 | 0 | 100 | 0.00 | | |||
| | OLOGIC | 0 | 0 | 0 | 100 | 0.00 | | |||
| +-----------------------------+------+-------+------------+-----------+-------+ | |||
| 6. Clocking | |||
| ----------- | |||
| +------------+------+-------+------------+-----------+-------+ | |||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | |||
| +------------+------+-------+------------+-----------+-------+ | |||
| | BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 | | |||
| | BUFIO | 0 | 0 | 0 | 8 | 0.00 | | |||
| | MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 | | |||
| | PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 | | |||
| | BUFMRCE | 0 | 0 | 0 | 4 | 0.00 | | |||
| | BUFHCE | 0 | 0 | 0 | 48 | 0.00 | | |||
| | BUFR | 0 | 0 | 0 | 8 | 0.00 | | |||
| +------------+------+-------+------------+-----------+-------+ | |||
| 7. Specific Feature | |||
| ------------------- | |||
| +-------------+------+-------+------------+-----------+-------+ | |||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | |||
| +-------------+------+-------+------------+-----------+-------+ | |||
| | BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | | |||
| | CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | | |||
| | DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | | |||
| | EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | | |||
| | FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | | |||
| | ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | | |||
| | STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | | |||
| | XADC | 0 | 0 | 0 | 1 | 0.00 | | |||
| +-------------+------+-------+------------+-----------+-------+ | |||
| 8. Primitives | |||
| ------------- | |||
| +----------+------+---------------------+ | |||
| | Ref Name | Used | Functional Category | | |||
| +----------+------+---------------------+ | |||
| | IBUF | 28 | IO | | |||
| | OBUF | 15 | IO | | |||
| | LUT2 | 14 | LUT | | |||
| | CARRY4 | 4 | CarryLogic | | |||
| | LUT1 | 1 | LUT | | |||
| +----------+------+---------------------+ | |||
| 9. Black Boxes | |||
| -------------- | |||
| +----------+------+ | |||
| | Ref Name | Used | | |||
| +----------+------+ | |||
| 10. Instantiated Netlists | |||
| ------------------------- | |||
| +----------+------+ | |||
| | Ref Name | Used | | |||
| +----------+------+ | |||
+ 170
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StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/gen_run.xml
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| @@ -0,0 +1,170 @@ | |||
| <?xml version="1.0" encoding="UTF-8"?> | |||
| <GenRun Id="impl_1" LaunchPart="xc7z010clg400-1" LaunchTime="1652445674"> | |||
| <File Type="ROUTE-PWR" Name="fixedPointTest_power_routed.rpt"/> | |||
| <File Type="PA-TCL" Name="fixedPointTest.tcl"/> | |||
| <File Type="BITSTR-MMI" Name="fixedPointTest.mmi"/> | |||
| <File Type="OPT-METHODOLOGY-DRC" Name="fixedPointTest_methodology_drc_opted.rpt"/> | |||
| <File Type="INIT-TIMING" Name="fixedPointTest_timing_summary_init.rpt"/> | |||
| <File Type="ROUTE-PWR-SUM" Name="fixedPointTest_power_summary_routed.pb"/> | |||
| <File Type="REPORTS-TCL" Name="fixedPointTest_reports.tcl"/> | |||
| <File Type="OPT-TIMING" Name="fixedPointTest_timing_summary_opted.rpt"/> | |||
| <File Type="OPT-DCP" Name="fixedPointTest_opt.dcp"/> | |||
| <File Type="OPT-DRC" Name="fixedPointTest_drc_opted.rpt"/> | |||
| <File Type="OPT-HWDEF" Name="fixedPointTest.hwdef"/> | |||
| <File Type="PWROPT-DCP" Name="fixedPointTest_pwropt.dcp"/> | |||
| <File Type="PWROPT-DRC" Name="fixedPointTest_drc_pwropted.rpt"/> | |||
| <File Type="PWROPT-TIMING" Name="fixedPointTest_timing_summary_pwropted.rpt"/> | |||
| <File Type="PLACE-DCP" Name="fixedPointTest_placed.dcp"/> | |||
| <File Type="PLACE-IO" Name="fixedPointTest_io_placed.rpt"/> | |||
| <File Type="PLACE-CLK" Name="fixedPointTest_clock_utilization_placed.rpt"/> | |||
| <File Type="PLACE-UTIL" Name="fixedPointTest_utilization_placed.rpt"/> | |||
| <File Type="PLACE-UTIL-PB" Name="fixedPointTest_utilization_placed.pb"/> | |||
| <File Type="PLACE-CTRL" Name="fixedPointTest_control_sets_placed.rpt"/> | |||
| <File Type="PLACE-SIMILARITY" Name="fixedPointTest_incremental_reuse_placed.rpt"/> | |||
| <File Type="PLACE-PRE-SIMILARITY" Name="fixedPointTest_incremental_reuse_pre_placed.rpt"/> | |||
| <File Type="BG-BIN" Name="fixedPointTest.bin"/> | |||
| <File Type="PLACE-TIMING" Name="fixedPointTest_timing_summary_placed.rpt"/> | |||
| <File Type="POSTPLACE-PWROPT-DCP" Name="fixedPointTest_postplace_pwropt.dcp"/> | |||
| <File Type="BITSTR-MSK" Name="fixedPointTest.msk"/> | |||
| <File Type="POSTPLACE-PWROPT-TIMING" Name="fixedPointTest_timing_summary_postplace_pwropted.rpt"/> | |||
| <File Type="PHYSOPT-DCP" Name="fixedPointTest_physopt.dcp"/> | |||
| <File Type="PHYSOPT-DRC" Name="fixedPointTest_drc_physopted.rpt"/> | |||
| <File Type="BITSTR-RBT" Name="fixedPointTest.rbt"/> | |||
| <File Type="PHYSOPT-TIMING" Name="fixedPointTest_timing_summary_physopted.rpt"/> | |||
| <File Type="ROUTE-ERROR-DCP" Name="fixedPointTest_routed_error.dcp"/> | |||
| <File Type="ROUTE-DCP" Name="fixedPointTest_routed.dcp"/> | |||
| <File Type="ROUTE-BLACKBOX-DCP" Name="fixedPointTest_routed_bb.dcp"/> | |||
| <File Type="ROUTE-DRC" Name="fixedPointTest_drc_routed.rpt"/> | |||
| <File Type="ROUTE-DRC-PB" Name="fixedPointTest_drc_routed.pb"/> | |||
| <File Type="ROUTE-DRC-RPX" Name="fixedPointTest_drc_routed.rpx"/> | |||
| <File Type="ROUTE-METHODOLOGY-DRC" Name="fixedPointTest_methodology_drc_routed.rpt"/> | |||
| <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="fixedPointTest_methodology_drc_routed.rpx"/> | |||
| <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="fixedPointTest_methodology_drc_routed.pb"/> | |||
| <File Type="ROUTE-PWR-RPX" Name="fixedPointTest_power_routed.rpx"/> | |||
| <File Type="ROUTE-STATUS" Name="fixedPointTest_route_status.rpt"/> | |||
| <File Type="ROUTE-STATUS-PB" Name="fixedPointTest_route_status.pb"/> | |||
| <File Type="ROUTE-TIMINGSUMMARY" Name="fixedPointTest_timing_summary_routed.rpt"/> | |||
| <File Type="ROUTE-TIMING-PB" Name="fixedPointTest_timing_summary_routed.pb"/> | |||
| <File Type="ROUTE-TIMING-RPX" Name="fixedPointTest_timing_summary_routed.rpx"/> | |||
| <File Type="ROUTE-SIMILARITY" Name="fixedPointTest_incremental_reuse_routed.rpt"/> | |||
| <File Type="ROUTE-CLK" Name="fixedPointTest_clock_utilization_routed.rpt"/> | |||
| <File Type="ROUTE-BUS-SKEW" Name="fixedPointTest_bus_skew_routed.rpt"/> | |||
| <File Type="ROUTE-BUS-SKEW-PB" Name="fixedPointTest_bus_skew_routed.pb"/> | |||
| <File Type="ROUTE-BUS-SKEW-RPX" Name="fixedPointTest_bus_skew_routed.rpx"/> | |||
| <File Type="POSTROUTE-PHYSOPT-DCP" Name="fixedPointTest_postroute_physopt.dcp"/> | |||
| <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="fixedPointTest_postroute_physopt_bb.dcp"/> | |||
| <File Type="POSTROUTE-PHYSOPT-TIMING" Name="fixedPointTest_timing_summary_postroute_physopted.rpt"/> | |||
| <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="fixedPointTest_timing_summary_postroute_physopted.pb"/> | |||
| <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="fixedPointTest_timing_summary_postroute_physopted.rpx"/> | |||
| <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="fixedPointTest_bus_skew_postroute_physopted.rpt"/> | |||
| <File Type="BG-BIT" Name="fixedPointTest.bit"/> | |||
| <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="fixedPointTest_bus_skew_postroute_physopted.pb"/> | |||
| <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="fixedPointTest_bus_skew_postroute_physopted.rpx"/> | |||
| <File Type="BITSTR-NKY" Name="fixedPointTest.nky"/> | |||
| <File Type="BITSTR-BMM" Name="fixedPointTest_bd.bmm"/> | |||
| <File Type="PDI-FILE" Name="fixedPointTest.pdi"/> | |||
| <File Type="RCFI_FILE" Name="fixedPointTest.rcfi"/> | |||
| <File Type="CFI_FILE" Name="fixedPointTest.cfi"/> | |||
| <File Type="RNPI_FILE" Name="fixedPointTest.rnpi"/> | |||
| <File Type="NPI_FILE" Name="fixedPointTest.npi"/> | |||
| <File Type="RBD_FILE" Name="fixedPointTest.rbd"/> | |||
| <File Type="BITSTR-LTX" Name="debug_nets.ltx"/> | |||
| <File Type="BITSTR-LTX" Name="fixedPointTest.ltx"/> | |||
| <File Type="BITSTR-SYSDEF" Name="fixedPointTest.sysdef"/> | |||
| <File Type="BG-BGN" Name="fixedPointTest.bgn"/> | |||
| <File Type="BG-DRC" Name="fixedPointTest.drc"/> | |||
| <File Type="RDI-RDI" Name="fixedPointTest.vdi"/> | |||
| <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/> | |||
| <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> | |||
| <Filter Type="Srcs"/> | |||
| <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_float_types.vhdl"> | |||
| <FileInfo SFType="VHDL2008"> | |||
| <Attr Name="Library" Val="ieee_proposed"/> | |||
| <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_float_types.vhdl"/> | |||
| <Attr Name="ImportTime" Val="1652436395"/> | |||
| <Attr Name="UsedIn" Val="synthesis"/> | |||
| <Attr Name="UsedIn" Val="simulation"/> | |||
| </FileInfo> | |||
| </File> | |||
| <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl"> | |||
| <FileInfo SFType="VHDL2008"> | |||
| <Attr Name="Library" Val="ieee_proposed"/> | |||
| <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl"/> | |||
| <Attr Name="ImportTime" Val="1652436398"/> | |||
| <Attr Name="UsedIn" Val="synthesis"/> | |||
| <Attr Name="UsedIn" Val="simulation"/> | |||
| </FileInfo> | |||
| </File> | |||
| <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl"> | |||
| <FileInfo SFType="VHDL2008"> | |||
| <Attr Name="Library" Val="ieee_proposed"/> | |||
| <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl"/> | |||
| <Attr Name="ImportTime" Val="1652436400"/> | |||
| <Attr Name="UsedIn" Val="synthesis"/> | |||
| <Attr Name="UsedIn" Val="simulation"/> | |||
| </FileInfo> | |||
| </File> | |||
| <File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_pkg.vhdl"> | |||
| <FileInfo SFType="VHDL2008"> | |||
| <Attr Name="Library" Val="ieee_proposed"/> | |||
| <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/fixedPoint/fixed_pkg.vhdl"/> | |||
| <Attr Name="ImportTime" Val="1652436402"/> | |||
| <Attr Name="UsedIn" Val="synthesis"/> | |||
| <Attr Name="UsedIn" Val="simulation"/> | |||
| </FileInfo> | |||
| </File> | |||
| <File Path="$PSRCDIR/sources_1/new/fixedPointTest.vhd"> | |||
| <FileInfo SFType="VHDL2008"> | |||
| <Attr Name="UsedIn" Val="synthesis"/> | |||
| <Attr Name="UsedIn" Val="simulation"/> | |||
| </FileInfo> | |||
| </File> | |||
| <Config> | |||
| <Option Name="DesignMode" Val="RTL"/> | |||
| <Option Name="TopModule" Val="fixedPointTest"/> | |||
| <Option Name="TopAutoSet" Val="TRUE"/> | |||
| </Config> | |||
| </FileSet> | |||
| <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> | |||
| <Filter Type="Constrs"/> | |||
| <File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc"> | |||
| <FileInfo> | |||
| <Attr Name="ImportPath" Val="$PPRDIR/../../../../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc"/> | |||
| <Attr Name="ImportTime" Val="1648802911"/> | |||
| <Attr Name="UsedIn" Val="synthesis"/> | |||
| <Attr Name="UsedIn" Val="implementation"/> | |||
| </FileInfo> | |||
| </File> | |||
| <Config> | |||
| <Option Name="ConstrsType" Val="XDC"/> | |||
| </Config> | |||
| </FileSet> | |||
| <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1"> | |||
| <Filter Type="Utils"/> | |||
| <File Path="$PSRCDIR/utils_1/imports/synth_1/fixedPointTest.dcp"> | |||
| <FileInfo> | |||
| <Attr Name="UsedIn" Val="synthesis"/> | |||
| <Attr Name="UsedIn" Val="implementation"/> | |||
| <Attr Name="UsedInSteps" Val="synth_1"/> | |||
| <Attr Name="AutoDcp" Val="1"/> | |||
| </FileInfo> | |||
| </File> | |||
| <Config> | |||
| <Option Name="TopAutoSet" Val="TRUE"/> | |||
| </Config> | |||
| </FileSet> | |||
| <Strategy Version="1" Minor="2"> | |||
| <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"> | |||
| <Desc>Default settings for Implementation.</Desc> | |||
| </StratHandle> | |||
| <Step Id="init_design"/> | |||
| <Step Id="opt_design"/> | |||
| <Step Id="power_opt_design"/> | |||
| <Step Id="place_design"/> | |||
| <Step Id="post_place_power_opt_design"/> | |||
| <Step Id="phys_opt_design"/> | |||
| <Step Id="route_design"/> | |||
| <Step Id="post_route_phys_opt_design"/> | |||
| <Step Id="write_bitstream"/> | |||
| </Strategy> | |||
| </GenRun> | |||
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StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/htr.txt
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| REM | |||
| REM Vivado(TM) | |||
| REM htr.txt: a Vivado-generated description of how-to-repeat the | |||
| REM the basic steps of a run. Note that runme.bat/sh needs | |||
| REM to be invoked for Vivado to track run status. | |||
| REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | |||
| REM | |||
| vivado -log fixedPointTest.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fixedPointTest.tcl -notrace | |||
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StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/init_design.pb
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StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/opt_design.pb
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StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/place_design.pb
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