 Julian Uebler
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a27d049f76
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Anfänge einer Tl-TB
Fehlt noch instanziierung modul TL und so weiter und so
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2 years ago |
 sessleral71711
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17f361ea12
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I hate git
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2 years ago |
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sessleral71711
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730cc895b1
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Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
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2 years ago |
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sessleral71711
|
019dc2868e
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Added parallelport, timer and ampelsteuerung
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2 years ago |
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sessleral71711
|
b30efd039d
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Added bus_if and fsm to top level design
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2 years ago |
|
sessleral71711
|
ecd6f16dbe
|
merge konflikt behoben
|
2 years ago |
|
sessleral71711
|
6a72019f25
|
Initalized top level design
|
2 years ago |
|
sessleral71711
|
53868c67fd
|
Added Bus_if and fsm to top level design
|
2 years ago |
|
sessleral71711
|
6ab278694e
|
Initalized top level design
|
2 years ago |
|
sessleral71711
|
026899b930
|
Added parallelport, timer and ampelsteuerung
|
2 years ago |
 Ralph Badenberg
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9ffb72cf97
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Screenshots from RADIANT --> how to create SPI module with radiant
|
2 years ago |
|
Ralph Badenberg
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72c964475f
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Screenshots from RADIANT --> how to create SPI module with radiant
|
2 years ago |
|
sessleral71711
|
d2aa8277c7
|
spi_interface dateien
|
2 years ago |
|
sessleral71711
|
c93bdaf629
|
Added bus_if and fsm to top level design
|
2 years ago |
|
sessleral71711
|
1be3ce1cea
|
merge konflikt behoben
|
2 years ago |
|
sessleral71711
|
4b0451fc63
|
Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
|
2 years ago |
|
sessleral71711
|
20f8e707bd
|
Added Bus_if and fsm to top level design
|
2 years ago |
|
Ralph Badenberg
|
c46a1c3b33
|
add "spi_interface_portsI()" (beginning of document)
|
2 years ago |
|
sessleral71711
|
6b874ba5c7
|
Initalized top level design
|
2 years ago |
|
sessleral71711
|
200a989683
|
Added modport for timer
|
2 years ago |
|
sessleral71711
|
613bffbcfc
|
Added modport in Bus_if for Fsm
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2 years ago |
 Christoph Reuss
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19177edb3f
|
Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022
|
2 years ago |
|
Christoph Reuss
|
0ecac8324e
|
Timer and Port source
|
2 years ago |
|
Julian Uebler
|
37989e5bc1
|
Ampel
Ampelsteuerung mit toplevel_verbindungen sowie normaler TB und random TB
|
2 years ago |
|
sessleral71711
|
ad550a9ac6
|
Created bus as interface
|
2 years ago |
|
sessleral71711
|
b8d834144b
|
Initalized top level design
|
2 years ago |
|
sessleral71711
|
e8af8d04c8
|
Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022
|
2 years ago |
 Claus Kuntzsch
|
ca1f1b531c
|
Dateien hochladen nach „“
|
2 years ago |
|
Claus Kuntzsch
|
7b858e7068
|
Dateien hochladen nach „“
|
2 years ago |
|
sessleral71711
|
71b0458554
|
FSM mit 2 States erstellt und getestet
|
2 years ago |
|
Ralph Badenberg
|
700350608a
|
Dateien hochladen nach „“
|
2 years ago |
|
sessleral71711
|
48610eeb8c
|
Added Clk_generator
|
2 years ago |
|
sessleral71711
|
dcb19f11aa
|
FSM initial commit
|
2 years ago |
 Kseniia Mikhailova
|
937da8ec22
|
Dateien hochladen nach „“
|
2 years ago |
|
Claus Kuntzsch
|
1cf5934374
|
„memory.txt“ löschen
|
2 years ago |
|
Claus Kuntzsch
|
667101d7fd
|
„SPI_FRAM_Module.sv“ löschen
|
2 years ago |
 kuntzschcl
|
08300af99a
|
FRAM
added FRAM sources
|
2 years ago |
|
Claus Kuntzsch
|
f691d1318a
|
Dateien hochladen nach „“
|
2 years ago |
|
kuntzschcl
|
fec9cd1ae0
|
Create FM25CL64B.pdf
|
2 years ago |
