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||||
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|
||||
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="7932" HostCore="12" HostMemory="016927088640">
|
||||
<Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="25900" HostCore="12" HostMemory="016927088640">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+4
-8
@@ -1,11 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1652439174" LaunchIncrCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp">
|
||||
<GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1653339519" LaunchIncrCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp">
|
||||
<File Type="PA-TCL" Name="regler.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="regler_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="regler_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="regler.vds"/>
|
||||
<File Type="RDS-UTIL" Name="regler_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="regler_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="regler.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="regler_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="regler_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/pwm_test.vhd">
|
||||
@@ -29,13 +32,6 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/wendeTangente.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_pkg.vhdl">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="Library" Val="ieee_proposed"/>
|
||||
|
||||
+3
-3
@@ -1,5 +1,5 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
@@ -13,7 +13,7 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313630:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
@@ -28,4 +28,4 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3035343861623234333065633433623139386531656634383534326531333964:506172656e742050412070726f6a656374204944:00
|
||||
eof:83681024
|
||||
eof:186662213
|
||||
BIN
Binary file not shown.
-2
@@ -70,8 +70,6 @@ proc create_report { reportName command } {
|
||||
}
|
||||
}
|
||||
OPTRACE "synth_1" START { ROLLUP_AUTO }
|
||||
set_param chipscope.maxJobs 3
|
||||
set_msg_config -id {Common 17-41} -limit 10000000
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z010clg400-1
|
||||
|
||||
|
||||
+155
-63
@@ -2,8 +2,8 @@
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Fri May 13 12:52:57 2022
|
||||
# Process ID: 2508
|
||||
# Start of session at: Mon May 23 22:58:42 2022
|
||||
# Process ID: 23388
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
|
||||
# Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds
|
||||
@@ -11,7 +11,7 @@
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
#-----------------------------------------------------------
|
||||
source regler.tcl -notrace
|
||||
create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1260.457 ; gain = 7.594
|
||||
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 8.066
|
||||
Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp
|
||||
INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis
|
||||
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
|
||||
@@ -24,27 +24,37 @@ WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis b
|
||||
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 12584
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 25492
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43]
|
||||
WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:97]
|
||||
WARNING: [Synth 8-6014] Unused sequential element e_k2_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:98]
|
||||
INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43]
|
||||
INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]
|
||||
WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:110]
|
||||
WARNING: [Synth 8-6014] Unused sequential element u_var_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:121]
|
||||
INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]
|
||||
WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.043 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1261.043 ; gain = 0.000
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
@@ -55,47 +65,51 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1273.594 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1273.594 ; gain = 0.000
|
||||
WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
|
||||
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z010clg400-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
3 Input 32 Bit Adders := 2
|
||||
2 Input 32 Bit Adders := 1
|
||||
2 Input 31 Bit Adders := 1
|
||||
2 Input 148 Bit Adders := 2
|
||||
3 Input 64 Bit Adders := 1
|
||||
2 Input 64 Bit Adders := 1
|
||||
2 Input 20 Bit Adders := 2
|
||||
2 Input 10 Bit Adders := 1
|
||||
+---Registers :
|
||||
32 Bit Registers := 2
|
||||
64 Bit Registers := 1
|
||||
+---Multipliers :
|
||||
1x32 Multipliers := 1
|
||||
41x64 Multipliers := 1
|
||||
10x64 Multipliers := 1
|
||||
+---Muxes :
|
||||
2 Input 32 Bit Muxes := 1
|
||||
2 Input 31 Bit Muxes := 1
|
||||
2 Input 148 Bit Muxes := 2
|
||||
2 Input 20 Bit Muxes := 2
|
||||
2 Input 10 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
@@ -112,26 +126,102 @@ Finished Part Resource Summary
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
DSP Report: Generating DSP I_k5, operation Mode is: (A:0xf4240)*B.
|
||||
DSP Report: operator I_k5 is absorbed into DSP I_k5.
|
||||
DSP Report: operator I_k5 is absorbed into DSP I_k5.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP u_reg1, operation Mode is: A*B.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: Generating DSP u_reg1, operation Mode is: A*B.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 1273.594 ; gain = 12.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
|
||||
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
|
||||
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|regler | (A:0xf4240)*B | 21 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | (PCIN>>17)+A*B | 24 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | PCIN+A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | (PCIN>>17)+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | PCIN+A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | (PCIN>>17)+A*B | 13 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | (PCIN>>17)+A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|
||||
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1288.984 ; gain = 27.941
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1297.449 ; gain = 36.406
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 1507.957 ; gain = 246.914
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
@@ -149,37 +239,37 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -192,42 +282,44 @@ Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |CARRY4 | 104|
|
||||
|3 |LUT1 | 66|
|
||||
|4 |LUT2 | 59|
|
||||
|5 |LUT3 | 182|
|
||||
|6 |LUT4 | 138|
|
||||
|7 |LUT5 | 49|
|
||||
|8 |LUT6 | 186|
|
||||
|9 |FDRE | 64|
|
||||
|10 |IBUF | 65|
|
||||
|11 |OBUF | 32|
|
||||
+------+-------+------+
|
||||
+------+--------+------+
|
||||
| |Cell |Count |
|
||||
+------+--------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |CARRY4 | 1613|
|
||||
|3 |DSP48E1 | 13|
|
||||
|4 |LUT1 | 165|
|
||||
|5 |LUT2 | 1000|
|
||||
|6 |LUT3 | 2638|
|
||||
|7 |LUT4 | 2484|
|
||||
|8 |LUT5 | 799|
|
||||
|9 |LUT6 | 3246|
|
||||
|10 |FDRE | 128|
|
||||
|11 |IBUF | 159|
|
||||
|12 |OBUF | 64|
|
||||
+------+--------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 11 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 1517.203 ; gain = 243.609
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1286.504 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 104 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.125 . Memory (MB): peak = 1517.203 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 1626 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
|
||||
WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1290.160 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1517.203 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Synth Design complete, checksum: 235c9ea4
|
||||
Synth Design complete, checksum: b5ea81b7
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
21 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.160 ; gain = 29.703
|
||||
synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 13 12:53:45 2022...
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon May 23 22:59:52 2022...
|
||||
BIN
Binary file not shown.
+41
-39
@@ -1,7 +1,7 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri May 13 12:53:45 2022
|
||||
| Date : Mon May 23 22:59:52 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb
|
||||
| Design : regler
|
||||
@@ -31,11 +31,11 @@ Table of Contents
|
||||
+-------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------------------+------+-------+------------+-----------+-------+
|
||||
| Slice LUTs* | 538 | 0 | 0 | 17600 | 3.06 |
|
||||
| LUT as Logic | 538 | 0 | 0 | 17600 | 3.06 |
|
||||
| Slice LUTs* | 7673 | 0 | 0 | 17600 | 43.60 |
|
||||
| LUT as Logic | 7673 | 0 | 0 | 17600 | 43.60 |
|
||||
| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
|
||||
| Slice Registers | 64 | 0 | 0 | 35200 | 0.18 |
|
||||
| Register as Flip Flop | 64 | 0 | 0 | 35200 | 0.18 |
|
||||
| Slice Registers | 128 | 0 | 0 | 35200 | 0.36 |
|
||||
| Register as Flip Flop | 128 | 0 | 0 | 35200 | 0.36 |
|
||||
| Register as Latch | 0 | 0 | 0 | 35200 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 |
|
||||
@@ -58,7 +58,7 @@ Table of Contents
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 64 | Yes | Reset | - |
|
||||
| 128 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -78,34 +78,35 @@ Table of Contents
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 0 | 80 | 0.00 |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| DSPs | 13 | 0 | 0 | 80 | 16.25 |
|
||||
| DSP48E1 only | 13 | | | | |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Bonded IOB | 97 | 0 | 0 | 100 | 97.00 |
|
||||
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 0 | 96 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 0 | 100 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 0 | 100 | 0.00 |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
+-----------------------------+------+-------+------------+-----------+--------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------------------------+------+-------+------------+-----------+--------+
|
||||
| Bonded IOB | 223 | 0 | 0 | 100 | 223.00 |
|
||||
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 0 | 96 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 0 | 100 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 0 | 100 | 0.00 |
|
||||
+-----------------------------+------+-------+------------+-----------+--------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
@@ -147,16 +148,17 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| LUT6 | 186 | LUT |
|
||||
| LUT3 | 182 | LUT |
|
||||
| LUT4 | 138 | LUT |
|
||||
| CARRY4 | 104 | CarryLogic |
|
||||
| LUT1 | 66 | LUT |
|
||||
| IBUF | 65 | IO |
|
||||
| FDRE | 64 | Flop & Latch |
|
||||
| LUT2 | 59 | LUT |
|
||||
| LUT5 | 49 | LUT |
|
||||
| OBUF | 32 | IO |
|
||||
| LUT6 | 3246 | LUT |
|
||||
| LUT3 | 2638 | LUT |
|
||||
| LUT4 | 2484 | LUT |
|
||||
| CARRY4 | 1613 | CarryLogic |
|
||||
| LUT2 | 1000 | LUT |
|
||||
| LUT5 | 799 | LUT |
|
||||
| LUT1 | 165 | LUT |
|
||||
| IBUF | 159 | IO |
|
||||
| FDRE | 128 | Flop & Latch |
|
||||
| OBUF | 64 | IO |
|
||||
| DSP48E1 | 13 | Block Arithmetic |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
+153
-61
@@ -10,7 +10,7 @@
|
||||
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source regler.tcl -notrace
|
||||
create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1260.457 ; gain = 7.594
|
||||
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 8.066
|
||||
Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp
|
||||
INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis
|
||||
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
|
||||
@@ -23,27 +23,37 @@ WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis b
|
||||
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 12584
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 25492
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43]
|
||||
WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:97]
|
||||
WARNING: [Synth 8-6014] Unused sequential element e_k2_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:98]
|
||||
INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:43]
|
||||
INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]
|
||||
WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:110]
|
||||
WARNING: [Synth 8-6014] Unused sequential element u_var_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:121]
|
||||
INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]
|
||||
WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.043 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1261.043 ; gain = 0.000
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
@@ -54,47 +64,51 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1273.594 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1273.594 ; gain = 0.000
|
||||
WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
|
||||
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z010clg400-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
3 Input 32 Bit Adders := 2
|
||||
2 Input 32 Bit Adders := 1
|
||||
2 Input 31 Bit Adders := 1
|
||||
2 Input 148 Bit Adders := 2
|
||||
3 Input 64 Bit Adders := 1
|
||||
2 Input 64 Bit Adders := 1
|
||||
2 Input 20 Bit Adders := 2
|
||||
2 Input 10 Bit Adders := 1
|
||||
+---Registers :
|
||||
32 Bit Registers := 2
|
||||
64 Bit Registers := 1
|
||||
+---Multipliers :
|
||||
1x32 Multipliers := 1
|
||||
41x64 Multipliers := 1
|
||||
10x64 Multipliers := 1
|
||||
+---Muxes :
|
||||
2 Input 32 Bit Muxes := 1
|
||||
2 Input 31 Bit Muxes := 1
|
||||
2 Input 148 Bit Muxes := 2
|
||||
2 Input 20 Bit Muxes := 2
|
||||
2 Input 10 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
@@ -111,26 +125,102 @@ Finished Part Resource Summary
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
DSP Report: Generating DSP I_k5, operation Mode is: (A:0xf4240)*B.
|
||||
DSP Report: operator I_k5 is absorbed into DSP I_k5.
|
||||
DSP Report: operator I_k5 is absorbed into DSP I_k5.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: operator I_k4 is absorbed into DSP I_k4.
|
||||
DSP Report: Generating DSP u_reg1, operation Mode is: A*B.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: Generating DSP u_reg1, operation Mode is: A*B.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
DSP Report: operator u_reg1 is absorbed into DSP u_reg1.
|
||||
WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 1273.594 ; gain = 12.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
|
||||
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
|
||||
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|regler | (A:0xf4240)*B | 21 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | (PCIN>>17)+A*B | 24 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | PCIN+A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | (PCIN>>17)+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | PCIN+A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | (PCIN>>17)+A*B | 13 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|regler | (PCIN>>17)+A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|
||||
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1288.984 ; gain = 27.941
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1297.449 ; gain = 36.406
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1260.457 ; gain = 0.000
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 1507.957 ; gain = 246.914
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
@@ -148,37 +238,37 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -191,42 +281,44 @@ Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |CARRY4 | 104|
|
||||
|3 |LUT1 | 66|
|
||||
|4 |LUT2 | 59|
|
||||
|5 |LUT3 | 182|
|
||||
|6 |LUT4 | 138|
|
||||
|7 |LUT5 | 49|
|
||||
|8 |LUT6 | 186|
|
||||
|9 |FDRE | 64|
|
||||
|10 |IBUF | 65|
|
||||
|11 |OBUF | 32|
|
||||
+------+-------+------+
|
||||
+------+--------+------+
|
||||
| |Cell |Count |
|
||||
+------+--------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |CARRY4 | 1613|
|
||||
|3 |DSP48E1 | 13|
|
||||
|4 |LUT1 | 165|
|
||||
|5 |LUT2 | 1000|
|
||||
|6 |LUT3 | 2638|
|
||||
|7 |LUT4 | 2484|
|
||||
|8 |LUT5 | 799|
|
||||
|9 |LUT6 | 3246|
|
||||
|10 |FDRE | 128|
|
||||
|11 |IBUF | 159|
|
||||
|12 |OBUF | 64|
|
||||
+------+--------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1274.391 ; gain = 13.934
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 11 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 1517.203 ; gain = 243.609
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1286.504 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 104 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.125 . Memory (MB): peak = 1517.203 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 1626 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
|
||||
WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1290.160 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1517.203 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Synth Design complete, checksum: 235c9ea4
|
||||
Synth Design complete, checksum: b5ea81b7
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
21 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.160 ; gain = 29.703
|
||||
synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 1517.203 ; gain = 256.160
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 13 12:53:45 2022...
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon May 23 22:59:52 2022...
|
||||
+2
-2
@@ -2,8 +2,8 @@
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Fri May 13 12:52:57 2022
|
||||
# Process ID: 2508
|
||||
# Start of session at: Mon May 23 22:58:42 2022
|
||||
# Process ID: 23388
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
|
||||
# Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds
|
||||
|
||||
BIN
Binary file not shown.
+1
-1
@@ -6,7 +6,7 @@ REM Filename : compile.bat
|
||||
REM Simulator : Xilinx Vivado Simulator
|
||||
REM Description : Script for compiling the simulation design source files
|
||||
REM
|
||||
REM Generated by Vivado on Fri May 13 13:48:21 +0200 2022
|
||||
REM Generated by Vivado on Mon May 23 23:00:16 +0200 2022
|
||||
REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
REM
|
||||
REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pt1'
|
||||
+3
-3
@@ -6,7 +6,7 @@ REM Filename : elaborate.bat
|
||||
REM Simulator : Xilinx Vivado Simulator
|
||||
REM Description : Script for elaborating the compiled design
|
||||
REM
|
||||
REM Generated by Vivado on Fri May 13 13:48:23 +0200 2022
|
||||
REM Generated by Vivado on Mon May 23 23:00:17 +0200 2022
|
||||
REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
REM
|
||||
REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
@@ -15,8 +15,8 @@ REM usage: elaborate.bat
|
||||
REM
|
||||
REM ****************************************************************************
|
||||
REM elaborate design
|
||||
echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
if "%errorlevel%"=="0" goto SUCCESS
|
||||
if "%errorlevel%"=="1" goto END
|
||||
:END
|
||||
|
||||
+11
-5
@@ -1,11 +1,17 @@
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling package std.standard
|
||||
Compiling package std.textio
|
||||
Compiling package ieee.std_logic_1164
|
||||
Compiling package ieee.numeric_std
|
||||
Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
|
||||
Built simulation snapshot pwm_test_db_behav
|
||||
+1
-1
@@ -8,4 +8,4 @@ if { [string length $curr_wave] == 0 } {
|
||||
}
|
||||
}
|
||||
|
||||
run 5 s
|
||||
run 10 s
|
||||
BIN
Binary file not shown.
+1
-1
@@ -6,7 +6,7 @@ REM Filename : simulate.bat
|
||||
REM Simulator : Xilinx Vivado Simulator
|
||||
REM Description : Script for simulating the design by launching the simulator
|
||||
REM
|
||||
REM Generated by Vivado on Fri May 13 12:56:57 +0200 2022
|
||||
REM Generated by Vivado on Mon May 23 23:00:20 +0200 2022
|
||||
REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
REM
|
||||
REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
|
||||
File renamed without changes.
BIN
Binary file not shown.
+1
-1
@@ -1 +1 @@
|
||||
--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "ieee_proposed" -L "secureip" -L "xpm" --snapshot "pwm_test_db_behav" "xil_defaultlib.pwm_test_db" -log "elaborate.log"
|
||||
--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "pwm_test_db_behav" "xil_defaultlib.pwm_test_db" -log "elaborate.log"
|
||||
BIN
Binary file not shown.
+8
-8
@@ -54,21 +54,21 @@
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern int main(int, char**);
|
||||
IKI_DLLESPEC extern void execute_51(char*, char *);
|
||||
IKI_DLLESPEC extern void execute_52(char*, char *);
|
||||
IKI_DLLESPEC extern void execute_46(char*, char *);
|
||||
IKI_DLLESPEC extern void execute_48(char*, char *);
|
||||
IKI_DLLESPEC extern void execute_50(char*, char *);
|
||||
IKI_DLLESPEC extern void execute_40(char*, char *);
|
||||
IKI_DLLESPEC extern void execute_41(char*, char *);
|
||||
IKI_DLLESPEC extern void execute_37(char*, char *);
|
||||
IKI_DLLESPEC extern void execute_39(char*, char *);
|
||||
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
|
||||
IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
|
||||
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
funcp funcTab[7] = {(funcp)execute_51, (funcp)execute_52, (funcp)execute_46, (funcp)execute_48, (funcp)execute_50, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
|
||||
funcp funcTab[7] = {(funcp)execute_40, (funcp)execute_41, (funcp)execute_37, (funcp)execute_39, (funcp)transaction_0, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback};
|
||||
const int NumRelocateId= 7;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc", (void **)funcTab, 7);
|
||||
iki_vhdl_file_variable_register(dp + 6536);
|
||||
iki_vhdl_file_variable_register(dp + 6592);
|
||||
iki_vhdl_file_variable_register(dp + 6264);
|
||||
iki_vhdl_file_variable_register(dp + 6320);
|
||||
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
+2
-2
@@ -1,8 +1,8 @@
|
||||
|
||||
{
|
||||
crc : 2044015283218523224 ,
|
||||
crc : 6733451111524596900 ,
|
||||
ccp_crc : 0 ,
|
||||
cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" ,
|
||||
cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" ,
|
||||
buildDate : "Oct 19 2021" ,
|
||||
buildTime : "03:16:22" ,
|
||||
linkCmd : "C:\\Xilinx\\Vivado\\2021.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/pwm_test_db_behav/xsimk.exe\" \"xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj\" \"xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2021.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" ,
|
||||
|
||||
BIN
Binary file not shown.
BIN
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BIN
Binary file not shown.
+2
-2
@@ -29,7 +29,7 @@ SCOPE_NAME_COLUMN_WIDTH=157
|
||||
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
|
||||
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
|
||||
OBJECT_NAME_COLUMN_WIDTH=156
|
||||
OBJECT_VALUE_COLUMN_WIDTH=75
|
||||
OBJECT_VALUE_COLUMN_WIDTH=49
|
||||
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
|
||||
PROCESS_NAME_COLUMN_WIDTH=75
|
||||
PROCESS_TYPE_COLUMN_WIDTH=75
|
||||
@@ -37,7 +37,7 @@ FRAME_INDEX_COLUMN_WIDTH=75
|
||||
FRAME_NAME_COLUMN_WIDTH=75
|
||||
FRAME_FILE_NAME_COLUMN_WIDTH=75
|
||||
FRAME_LINE_NUM_COLUMN_WIDTH=156
|
||||
LOCAL_NAME_COLUMN_WIDTH=75
|
||||
LOCAL_NAME_COLUMN_WIDTH=49
|
||||
LOCAL_VALUE_COLUMN_WIDTH=75
|
||||
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
|
||||
PROTO_NAME_COLUMN_WIDTH=0
|
||||
|
||||
BIN
Binary file not shown.
+5
-5
@@ -1,7 +1,7 @@
|
||||
Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 53693
|
||||
Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 57651
|
||||
Design successfully loaded
|
||||
Design Loading Memory Usage: 7256 KB (Peak: 7256 KB)
|
||||
Design Loading CPU Usage: 15 ms
|
||||
Design Loading Memory Usage: 7284 KB (Peak: 7284 KB)
|
||||
Design Loading CPU Usage: 61 ms
|
||||
Simulation completed
|
||||
Simulation Memory Usage: 7792 KB (Peak: 7792 KB)
|
||||
Simulation CPU Usage: 15 ms
|
||||
Simulation Memory Usage: 15804 KB (Peak: 15804 KB)
|
||||
Simulation CPU Usage: 7905 ms
|
||||
BIN
Binary file not shown.
BIN
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BIN
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+3
-4
@@ -2,7 +2,6 @@
|
||||
2020.2
|
||||
Oct 19 2021
|
||||
03:16:22
|
||||
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652442389,vhdl,,,,pwm_test_db,,,,,,,,
|
||||
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1651498208,vhdl,,,,pt1,,,,,,,,
|
||||
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1652437038,vhdl,,,,regler,,,,,,,,
|
||||
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd,1652437027,vhdl,,,,wendetangente,,,,,,,,
|
||||
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1653337595,vhdl,,,,pwm_test_db,,,,,,,,
|
||||
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1653339512,vhdl,,,,pt1,,,,,,,,
|
||||
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1653338461,vhdl,,,,regler,,,,,,,,
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pt1'
|
||||
BIN
Binary file not shown.
+44
-31
@@ -21,9 +21,8 @@
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
library ieee_proposed;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
|
||||
|
||||
--use IEEE.STD_LOGIC_1164.ALL;
|
||||
@@ -44,60 +43,73 @@ end pwm_test_db;
|
||||
architecture Behavioral of pwm_test_db is
|
||||
|
||||
component regler is
|
||||
Port ( clk : in STD_LOGIC; --Clk -> Gibt Abtastzeit vor
|
||||
w : in integer := 0; --Sollwert
|
||||
y : in integer := 0; --Istwert
|
||||
u : inout integer := 0); --Stellgöße
|
||||
Port ( clk : in STD_LOGIC; --Clk -> Gibt abtastzeit vor
|
||||
w : in signed(63 downto 0) := (others => '0'); --Sollwert
|
||||
y : in signed(63 downto 0) := (others => '0'); --Istwert
|
||||
u : inout signed(63 downto 0) := (others => '0'); --Stellgöße
|
||||
KR : in signed(9 downto 0) := to_signed(1,10); -- Verstärkung
|
||||
T : in signed(9 downto 0) := to_signed(1000, 10); -- Abtastzeit in us 1000us
|
||||
TV : signed(9 downto 0) := (others => '0'); -- Vorhaltezeit für Differenzierer interesannt
|
||||
TN : in signed(9 downto 0) := to_signed(1,10)); -- Nachstellzeit
|
||||
end component;
|
||||
|
||||
component pt1 is
|
||||
Port ( clk : in STD_LOGIC;
|
||||
u : in integer;
|
||||
y : inout integer);
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
u : in signed(63 downto 0) := to_signed(1,64);
|
||||
y : inout signed(63 downto 0) := to_signed(1,64); -- muss vielleicht initalisiert werden vorher!?
|
||||
a : in signed(9 downto 0) := to_signed(1,10);
|
||||
k : in signed(9 downto 0) := to_signed(1,10);
|
||||
stepWidth : signed(9 downto 0) := to_signed(10,10)); --in us -> 10us
|
||||
end component;
|
||||
|
||||
|
||||
component wendeTangente is
|
||||
Port ( a : in sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen
|
||||
b : in sfixed (7 downto -6);
|
||||
c : out sfixed (7 downto -6));
|
||||
end component;
|
||||
|
||||
|
||||
signal clk : std_logic := '0';
|
||||
signal clk_100 : std_logic := '0';
|
||||
|
||||
signal w : integer := 1000000;
|
||||
signal u : integer := 0;
|
||||
signal y : integer := 0;
|
||||
signal w : signed(63 downto 0) := to_signed(1000000, 64);
|
||||
signal u : signed(63 downto 0) := to_signed(0, 64);
|
||||
signal y : signed(63 downto 0) := to_signed(0, 64);
|
||||
signal cnt : integer := 0;
|
||||
signal risingEdge : std_logic := '0';
|
||||
|
||||
--Streckenparameter
|
||||
signal a : signed(9 downto 0) := to_signed(1, 10);
|
||||
signal k : signed(9 downto 0) := to_signed(1, 10);
|
||||
signal stepWidth : signed(9 downto 0) := to_signed(10, 10);
|
||||
|
||||
--Reglerparameter
|
||||
signal KR : signed(9 downto 0) := to_signed(1, 10); -- Verstärkung
|
||||
signal T : signed(9 downto 0) := to_signed(1000, 10); -- Abtastzeit in ns = 1ms = 1000000ns
|
||||
signal TV : signed(9 downto 0) := to_signed(0, 10); -- Vorhaltezeit für Differenzierer interesannt
|
||||
signal TN : signed(9 downto 0) := to_signed(100000, 10); -- Nachstellzeit in us
|
||||
|
||||
|
||||
--wendetangenten test
|
||||
signal a : sfixed(7 downto -6) := to_sfixed (-3.125, 7, -6);
|
||||
signal b : sfixed(7 downto -6) := to_sfixed (5.1111, 7, -6);
|
||||
signal c : sfixed(7 downto -6);
|
||||
|
||||
begin
|
||||
|
||||
uut_regler: regler PORT MAP (
|
||||
clk => clk,
|
||||
clk => clk_100,
|
||||
w => w,
|
||||
y => y,
|
||||
u => u
|
||||
u => u,
|
||||
KR => KR,
|
||||
T => T,
|
||||
TV => TV,
|
||||
TN => TN
|
||||
);
|
||||
|
||||
uut_pt1: pt1 PORT MAP (
|
||||
clk => clk,
|
||||
u => u,
|
||||
y => y
|
||||
y => y,
|
||||
a => a,
|
||||
k => k,
|
||||
stepWidth => stepWidth
|
||||
);
|
||||
|
||||
uutWendeTangente: wendeTangente PORT MAP(
|
||||
a => a,
|
||||
b => b,
|
||||
c => c
|
||||
);
|
||||
|
||||
--generate clock
|
||||
clk <= not clk after 5 us;
|
||||
@@ -105,7 +117,8 @@ clk <= not clk after 5 us;
|
||||
|
||||
process
|
||||
begin
|
||||
w <= 1000000;
|
||||
--w <= 100000000;
|
||||
w <= to_signed(1000000, 64); --muss >= 1000000 sein!
|
||||
|
||||
-- if rising_edge(clk) and ( cnt >= 100) then
|
||||
-- clk_100 <= not clk_100;
|
||||
@@ -116,7 +129,7 @@ begin
|
||||
cnt <= cnt+1;
|
||||
risingEdge <= '1';
|
||||
clk_100 <= '0';
|
||||
--a <= a + to_sfixed(1.111, 7, -6);
|
||||
|
||||
end if;
|
||||
|
||||
if clk = '0' then
|
||||
|
||||
+18
-6
@@ -21,6 +21,7 @@
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
@@ -34,28 +35,39 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
entity pt1 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
u : in integer := 0;
|
||||
y : inout integer := 0); -- muss vielleicht initalisiert werden vorher!?
|
||||
u : in signed(63 downto 0) := to_signed(0, 64);
|
||||
y : inout signed(63 downto 0) := to_signed(0, 64); -- muss vielleicht initalisiert werden vorher!?
|
||||
a : in signed(9 downto 0) := to_signed(1, 10);
|
||||
k : in signed(9 downto 0) := to_signed(1, 10);
|
||||
stepWidth : signed(9 downto 0) := to_signed(10, 10)); --in us -> 10us
|
||||
end pt1;
|
||||
|
||||
architecture Behavioral of pt1 is
|
||||
|
||||
signal stepWidth : integer := 10000; -- in ns -> 10 us später berechnet aus Clk und Prescaler
|
||||
|
||||
--signal stepWidth : integer := 10; -- in us -> 10 us später berechnet aus Clk und Prescaler
|
||||
signal prescaler : signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit
|
||||
|
||||
-- Konstanten Streckenparameter
|
||||
signal a : integer := 1;
|
||||
signal k : integer := 2;
|
||||
--signal a : integer := 1;
|
||||
--signal k : integer := 1;
|
||||
|
||||
|
||||
-- signal u : integer := 100000; -- Eingangswert Strecke jetzt u aus port
|
||||
-- signal x : integer := 0; -- Ausgangssignal Strecke -> Stellgröße jetzt y aus port
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
process(clk)
|
||||
|
||||
variable y_var : signed(83 downto 0) := to_signed(0, 84);
|
||||
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
y <= y + stepWidth*(k*u-a*y)/1000; -- durch 1000 wg. milisekunden abtastzeit
|
||||
y_var := y + stepWidth * (k * u - a * y) / prescaler; -- durch 1000 wg. milisekunden abtastzeit
|
||||
y <= y_var(63 downto 0);
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
+45
-18
@@ -21,6 +21,7 @@
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
--use IEEE.MATH_REAL.ALL;
|
||||
--use IEEE.float_pkg.ALL;
|
||||
|
||||
@@ -35,22 +36,27 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity regler is
|
||||
Port ( clk : in STD_LOGIC; --Clk -> Gibt abtastzeit vor
|
||||
w : in integer := 0; --Sollwert
|
||||
y : in integer := 0; --Istwert
|
||||
u : inout integer := 0); --Stellgöße
|
||||
w : in signed(63 downto 0) := (others => '0'); --Sollwert
|
||||
y : in signed(63 downto 0) := (others => '0'); --Istwert
|
||||
u : inout signed(63 downto 0) := (others => '0'); --Stellgöße
|
||||
KR : in signed(9 downto 0) := to_signed(1, 10); -- Verstärkung
|
||||
T : in signed(9 downto 0) := to_signed(1000, 10); -- Abtastzeit in us 1000us
|
||||
TV : signed(9 downto 0) := (others => '0'); -- Vorhaltezeit für Differenzierer interesannt
|
||||
TN : in signed(9 downto 0) := to_signed(1, 10)); -- Nachstellzeit
|
||||
end regler;
|
||||
|
||||
architecture Behavioral of regler is
|
||||
|
||||
|
||||
--signal stepWidth : integer := 1; -- 10 us später berechnet aus Clk und Prescaler
|
||||
signal prescaler : signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit 1000000
|
||||
|
||||
|
||||
-- Parameter aus Sprungantwort etc.
|
||||
signal KR : integer := 1; -- Verstärkung
|
||||
signal T : integer := 1; -- Abtastzeit in ns = 1ms = 1000000ns
|
||||
signal TV : integer := 0; -- Vorhaltezeit für Differenzierer interesannt
|
||||
signal TN : integer := 10; -- Nachstellzeit
|
||||
--signal KR : integer := 1; -- Verstärkung
|
||||
--signal T : integer := 1000; -- Abtastzeit in ns = 1ms = 1000000ns
|
||||
--signal TV : integer := 0; -- Vorhaltezeit für Differenzierer interesannt
|
||||
--signal TN : integer := 10; -- Nachstellzeit
|
||||
|
||||
-- Konstanten Reglerparameter
|
||||
--signal a1 : integer ;
|
||||
@@ -58,17 +64,20 @@ signal TN : integer := 10; -- Nachstellzeit
|
||||
--signal b1 : integer;
|
||||
--signal b2 : integer;
|
||||
|
||||
signal a1 : integer := 1;
|
||||
signal b0 : integer := KR*(1+TV/T);
|
||||
signal b1 : integer := -KR *(1 - T / TN + 2 * TV / T );
|
||||
signal b2 : integer := KR * TV/T;
|
||||
--signal a1 : signed(63 downto 0) := to_signed(1, 64);
|
||||
--signal b0 : signed(63 downto 0) := KR *(1 + TV / T);
|
||||
--signal b1 : signed(63 downto 0) := -KR *(1 - T / TN + 2 * TV / T );
|
||||
--signal b2 : signed(63 downto 0) := KR * TV/T;
|
||||
|
||||
|
||||
--interne Signale signal
|
||||
--signal u_k1 : integer := 0; -- = uk-1 = u (wurde nicht geändert)
|
||||
--signal e_k : integer := 0; -- aktuelle Reglerdiffferenz
|
||||
signal e_k1 : integer := 0; -- letzte ""
|
||||
signal e_k2 : integer := 0; -- vorletzte ""
|
||||
signal e_k1 : signed(63 downto 0) := to_signed(0, 64); -- letzte ""
|
||||
signal e_k2 : signed(63 downto 0) := to_signed(0, 64); -- vorletzte ""
|
||||
|
||||
|
||||
signal I_k : signed(147 downto 0) := to_signed(0, 148); -- I-Anteil
|
||||
|
||||
|
||||
-- signal u : integer := 100000; -- Eingangswert Strecke
|
||||
@@ -81,7 +90,11 @@ begin
|
||||
|
||||
|
||||
process(clk)
|
||||
variable e_k : integer;
|
||||
|
||||
variable e_k : signed(63 downto 0) := to_signed(0, 64); -- aktuelle Reglerabweichung
|
||||
--variable I_k : signed(148 downto 0) := to_signed(0, 64); -- I-Anteil
|
||||
--variable I_k1 : integer := 0; -- letzer I-Anteil
|
||||
variable u_var : signed(147 downto 0) := to_signed(0, 148);
|
||||
|
||||
begin
|
||||
|
||||
@@ -93,11 +106,25 @@ process(clk)
|
||||
-- b1 <= -KR *(1 - T / TN + 2 * TV / T );
|
||||
-- b2 <= KR * TV/T;
|
||||
|
||||
--u <= e; -- Regler überbrücken!
|
||||
|
||||
e_k := w - y; --Reglerdifferenzbilden
|
||||
u <= (a1*u+b0*e_k+b1*e_k1+b2*e_k2)/1000; --Stellgröße u berechnen
|
||||
e_k2 <= e_k1;
|
||||
e_k1 <= e_k;
|
||||
|
||||
|
||||
-- PID-Regler ---------------------------------------
|
||||
--u <= (a1*u+b0*e_k+b1*e_k1+b2*e_k2)/1000; --Stellgröße u berechnen, PID-Regler
|
||||
|
||||
--e_k2 <= e_k1;
|
||||
--e_k1 <= e_k;
|
||||
|
||||
-- PI-Regler ----------------------------------------
|
||||
I_k <= I_k + T * 1 / TN * prescaler * e_k / prescaler; -- I-Anteil berechnen
|
||||
u_var := KR * e_k + I_k;
|
||||
u <= u_var(63 downto 0);
|
||||
|
||||
-----------------------------------------------------
|
||||
--u <= w; -- Regler überbrücken!
|
||||
|
||||
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
-61
@@ -1,61 +0,0 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 13.05.2022 11:46:14
|
||||
-- Design Name:
|
||||
-- Module Name: wendeTangente - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
library ieee_proposed;
|
||||
use ieee_proposed.fixed_pkg.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity wendeTangente is
|
||||
Port ( a : in sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen
|
||||
b : in sfixed (7 downto -6);
|
||||
c : out sfixed (7 downto -6));
|
||||
end wendeTangente;
|
||||
|
||||
architecture Behavioral of wendeTangente is
|
||||
|
||||
|
||||
--signal a, b, c : sfixed (7 downto -6); -- 14 Bit breit, 6 Nachkommastellen
|
||||
|
||||
|
||||
begin
|
||||
|
||||
process(a,b)
|
||||
|
||||
begin
|
||||
|
||||
c <= a+b;
|
||||
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
@@ -56,7 +56,7 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="zybo-z7-10"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="119"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="161"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
@@ -107,13 +107,6 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/wendeTangente.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/imports/fixedPoint/fixed_pkg.vhdl">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="Library" Val="ieee_proposed"/>
|
||||
@@ -201,7 +194,7 @@
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/pwm_test_db_func_synth.wcfg"/>
|
||||
<Option Name="xsim.simulate.runtime" Val="5 s"/>
|
||||
<Option Name="xsim.simulate.runtime" Val="10 s"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
|
||||
+14
-45
@@ -10,39 +10,32 @@
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0.000000000 ms"></ZoomStartTime>
|
||||
<ZoomEndTime time="2,416.176243694 ms"></ZoomEndTime>
|
||||
<Cursor1Time time="0.000000000 ms"></Cursor1Time>
|
||||
<ZoomStartTime time="0.000000 us"></ZoomStartTime>
|
||||
<ZoomEndTime time="5.000001 us"></ZoomEndTime>
|
||||
<Cursor1Time time="5.000000 us"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="136"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="82"></ValueColumnWidth>
|
||||
<ValueColumnWidth column_width="70"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="8" />
|
||||
<WVObjectSize size="5" />
|
||||
<wvobject fp_name="/pwm_test_db/clk" type="logic">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/pwm_test_db/u" type="other">
|
||||
<obj_property name="ElementShortName">u</obj_property>
|
||||
<obj_property name="ObjectShortName">u</obj_property>
|
||||
<wvobject fp_name="/pwm_test_db/u" type="array">
|
||||
<obj_property name="ElementShortName">u[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">u[63:0]</obj_property>
|
||||
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ANALOG</obj_property>
|
||||
<obj_property name="CellHeight">100</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/pwm_test_db/y" type="other">
|
||||
<obj_property name="ElementShortName">y</obj_property>
|
||||
<obj_property name="ObjectShortName">y</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ANALOG</obj_property>
|
||||
<obj_property name="AnalogYRangeType">ANALOG_YRANGETYPE_FIXED</obj_property>
|
||||
<obj_property name="AnalogYRangeMin">0</obj_property>
|
||||
<obj_property name="AnalogYRRangeMax">0</obj_property>
|
||||
<obj_property name="CustomSignalColor">#00FF00</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="CellHeight">150</obj_property>
|
||||
<wvobject fp_name="/pwm_test_db/y" type="array">
|
||||
<obj_property name="ElementShortName">y[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">y[63:0]</obj_property>
|
||||
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||
<obj_property name="AnalogInterpolation">ANALOG_INTERPOLATION_LINEAR</obj_property>
|
||||
<obj_property name="AnalogOffscale">ANALOG_OFFSCALE_HIDE</obj_property>
|
||||
<obj_property name="AnalogHorizLine">0.000000</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ANALOG</obj_property>
|
||||
<obj_property name="CellHeight">100</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/pwm_test_db/clk_100" type="logic">
|
||||
<obj_property name="ElementShortName">clk_100</obj_property>
|
||||
@@ -52,28 +45,4 @@
|
||||
<obj_property name="ElementShortName">cnt</obj_property>
|
||||
<obj_property name="ObjectShortName">cnt</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/pwm_test_db/uutWendeTangente/a" type="array">
|
||||
<obj_property name="ElementShortName">a[7:-6]</obj_property>
|
||||
<obj_property name="ObjectShortName">a[7:-6]</obj_property>
|
||||
<obj_property name="Radix">REALRADIX</obj_property>
|
||||
<obj_property name="radix_realType">SIGNEDFIXEDPOINTRADIX</obj_property>
|
||||
<obj_property name="radix_fractionWidth">28</obj_property>
|
||||
<obj_property name="radix_otherWidth">0</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/pwm_test_db/uutWendeTangente/b" type="array">
|
||||
<obj_property name="ElementShortName">b[7:-6]</obj_property>
|
||||
<obj_property name="ObjectShortName">b[7:-6]</obj_property>
|
||||
<obj_property name="Radix">REALRADIX</obj_property>
|
||||
<obj_property name="radix_realType">SIGNEDFIXEDPOINTRADIX</obj_property>
|
||||
<obj_property name="radix_fractionWidth">28</obj_property>
|
||||
<obj_property name="radix_otherWidth">0</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/pwm_test_db/uutWendeTangente/c" type="array">
|
||||
<obj_property name="ElementShortName">c[7:-6]</obj_property>
|
||||
<obj_property name="ObjectShortName">c[7:-6]</obj_property>
|
||||
<obj_property name="Radix">REALRADIX</obj_property>
|
||||
<obj_property name="radix_realType">SIGNEDFIXEDPOINTRADIX</obj_property>
|
||||
<obj_property name="radix_fractionWidth">28</obj_property>
|
||||
<obj_property name="radix_otherWidth">0</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
@@ -2,10 +2,10 @@
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Fri May 13 14:02:42 2022
|
||||
# Process ID: 17732
|
||||
# Start of session at: Mon May 23 20:31:11 2022
|
||||
# Process ID: 10504
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18808 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent7676 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
@@ -13,3 +13,83 @@
|
||||
start_gui
|
||||
open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
|
||||
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
|
||||
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
|
||||
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} 64
|
||||
remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} -line 64
|
||||
add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} 64
|
||||
remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} -line 64
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
@@ -2,10 +2,10 @@
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Fri May 13 14:02:42 2022
|
||||
# Process ID: 17732
|
||||
# Start of session at: Mon May 23 20:31:11 2022
|
||||
# Process ID: 10504
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18808 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent7676 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
@@ -66,5 +66,541 @@ Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
|
||||
open_project: Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.184 ; gain = 0.000
|
||||
open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 1582.152 ; gain = 0.000
|
||||
update_compile_order -fileset sources_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 20:59:31 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:01:23 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:13:32 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:15:40 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:18:26 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:20:30 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:21:45 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:23:09 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:24:17 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:25:12 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:26:12 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 21:27:34 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 22:11:01 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 22:12:13 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 22:14:47 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pt1'
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'regler'
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
|
||||
ERROR: [VRFC 10-3214] character 'A' is not in element type 'std_ulogic' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:63]
|
||||
ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:43]
|
||||
INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd' ignored due to errors
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
||||
INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log'
|
||||
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
|
||||
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
||||
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pt1'
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'regler'
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
ERROR: [VRFC 10-664] expression has 1 elements ; expected 10 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:50]
|
||||
ERROR: [VRFC 10-664] expression has 1 elements ; expected 10 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:53]
|
||||
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit pwm_test_db in library work failed.
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
|
||||
INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
|
||||
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
|
||||
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
||||
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
ERROR: [VRFC 10-664] expression has 1 elements ; expected 10 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:42]
|
||||
ERROR: [VRFC 10-664] expression has 1 elements ; expected 10 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:45]
|
||||
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit pwm_test_db in library work failed.
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
||||
INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
|
||||
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
|
||||
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
||||
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pt1'
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'regler'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
ERROR: [VRFC 10-3311] expression has 10 elements ; formal 'stepwidth' expects 64 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:110]
|
||||
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit pwm_test_db in library work failed.
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
|
||||
INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
|
||||
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
|
||||
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
||||
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1582.152 ; gain = 0.000
|
||||
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pt1'
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
ERROR: [VRFC 10-664] expression has 10 elements ; expected 64 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:59]
|
||||
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit pwm_test_db in library work failed.
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
|
||||
INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
|
||||
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
|
||||
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
||||
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
ERROR: [VRFC 10-664] expression has 10 elements ; expected 64 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:60]
|
||||
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit pwm_test_db in library work failed.
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
|
||||
INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'
|
||||
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.
|
||||
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
||||
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling package std.standard
|
||||
Compiling package std.textio
|
||||
Compiling package ieee.std_logic_1164
|
||||
Compiling package ieee.numeric_std
|
||||
Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
|
||||
Built simulation snapshot pwm_test_db_behav
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
|
||||
INFO: [USF-XSim-4] XSim::Simulate design
|
||||
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [USF-XSim-98] *** Running xsim
|
||||
with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
|
||||
INFO: [USF-XSim-8] Loading simulator feature
|
||||
Time resolution is 1 ps
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
# set curr_wave [current_wave_config]
|
||||
# if { [string length $curr_wave] == 0 } {
|
||||
# if { [llength [get_objects]] > 0} {
|
||||
# add_wave /
|
||||
# set_property needs_save false [current_wave_config]
|
||||
# } else {
|
||||
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
# }
|
||||
# }
|
||||
# run 10 s
|
||||
ERROR: Array sizes do not match, left array has 64 elements, right array has 84 elements
|
||||
Time: 5 us Iteration: 0 Process: /pwm_test_db/uut_pt1/line__61
|
||||
File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd
|
||||
|
||||
HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd:64
|
||||
INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
|
||||
INFO: [USF-XSim-97] XSim simulation ran for 10 s
|
||||
launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1582.152 ; gain = 0.000
|
||||
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
|
||||
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
|
||||
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
|
||||
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
|
||||
close_sim
|
||||
INFO: [Simtcl 6-16] Simulation closed
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
||||
INFO: [USF-XSim-4] XSim::Simulate design
|
||||
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [USF-XSim-98] *** Running xsim
|
||||
with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
|
||||
INFO: [USF-XSim-8] Loading simulator feature
|
||||
Time resolution is 1 ps
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
# set curr_wave [current_wave_config]
|
||||
# if { [string length $curr_wave] == 0 } {
|
||||
# if { [llength [get_objects]] > 0} {
|
||||
# add_wave /
|
||||
# set_property needs_save false [current_wave_config]
|
||||
# } else {
|
||||
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
# }
|
||||
# }
|
||||
# run 10 s
|
||||
ERROR: Array sizes do not match, left array has 64 elements, right array has 84 elements
|
||||
Time: 5 us Iteration: 0 Process: /pwm_test_db/uut_pt1/line__61
|
||||
File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd
|
||||
|
||||
HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd:64
|
||||
INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
|
||||
INFO: [USF-XSim-97] XSim simulation ran for 10 s
|
||||
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1582.152 ; gain = 0.000
|
||||
add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} 64
|
||||
remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} -line 64
|
||||
add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} 64
|
||||
remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} -line 64
|
||||
reset_run synth_1
|
||||
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
|
||||
WARNING: [Vivado 12-1017] Problems encountered:
|
||||
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
|
||||
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 22:30:42 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
close_sim
|
||||
INFO: [Simtcl 6-16] Simulation closed
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
|
||||
INFO: [USF-XSim-4] XSim::Simulate design
|
||||
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [USF-XSim-98] *** Running xsim
|
||||
with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
|
||||
INFO: [USF-XSim-8] Loading simulator feature
|
||||
Time resolution is 1 ps
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
# set curr_wave [current_wave_config]
|
||||
# if { [string length $curr_wave] == 0 } {
|
||||
# if { [llength [get_objects]] > 0} {
|
||||
# add_wave /
|
||||
# set_property needs_save false [current_wave_config]
|
||||
# } else {
|
||||
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
# }
|
||||
# }
|
||||
# run 10 s
|
||||
ERROR: Array sizes do not match, left array has 64 elements, right array has 84 elements
|
||||
Time: 5 us Iteration: 0 Process: /pwm_test_db/uut_pt1/line__61
|
||||
File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd
|
||||
|
||||
HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd:64
|
||||
INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
|
||||
INFO: [USF-XSim-97] XSim simulation ran for 10 s
|
||||
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1582.152 ; gain = 0.000
|
||||
reset_run synth_1
|
||||
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
|
||||
WARNING: [Vivado 12-1017] Problems encountered:
|
||||
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
|
||||
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Mon May 23 22:43:21 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
close_sim
|
||||
INFO: [Simtcl 6-16] Simulation closed
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pt1'
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'regler'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling package std.standard
|
||||
Compiling package std.textio
|
||||
Compiling package ieee.std_logic_1164
|
||||
Compiling package ieee.numeric_std
|
||||
Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
|
||||
Built simulation snapshot pwm_test_db_behav
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
|
||||
INFO: [USF-XSim-4] XSim::Simulate design
|
||||
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [USF-XSim-98] *** Running xsim
|
||||
with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
|
||||
INFO: [USF-XSim-8] Loading simulator feature
|
||||
Time resolution is 1 ps
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
# set curr_wave [current_wave_config]
|
||||
# if { [string length $curr_wave] == 0 } {
|
||||
# if { [llength [get_objects]] > 0} {
|
||||
# add_wave /
|
||||
# set_property needs_save false [current_wave_config]
|
||||
# } else {
|
||||
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
# }
|
||||
# }
|
||||
# run 10 s
|
||||
ERROR: Array sizes do not match, left array has 148 elements, right array has 84 elements
|
||||
Time: 5 us Iteration: 0 Process: /pwm_test_db/uut_pt1/line__63
|
||||
File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd
|
||||
|
||||
HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd:69
|
||||
INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
|
||||
INFO: [USF-XSim-97] XSim simulation ran for 10 s
|
||||
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1582.152 ; gain = 0.000
|
||||
close_sim
|
||||
INFO: [Simtcl 6-16] Simulation closed
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon May 23 22:51:46 2022...
|
||||
@@ -1,34 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed May 4 17:59:18 2022
|
||||
# Process ID: 14848
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18128 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
@@ -1,40 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed May 11 13:29:39 2022
|
||||
# Process ID: 16520
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent13076 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
#----------------------------------------------------------start_gui
|
||||
open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
r
|
||||
update_compile_order -fileset sources_1
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
@@ -1,356 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed May 11 13:29:39 2022
|
||||
# Process ID: 16520
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent13076 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
#----------------------------------------------------------start_gui
|
||||
open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
|
||||
Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
|
||||
'
|
||||
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
|
||||
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
|
||||
INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
|
||||
open_project: Time (s): cpu = 00:00:43 ; elapsed = 00:00:21 . Memory (MB): peak = 1254.160 ; gain = 0.000
|
||||
update_compile_order -fileset sources_1
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'regler'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling package std.standard
|
||||
Compiling package std.textio
|
||||
Compiling package ieee.std_logic_1164
|
||||
Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
|
||||
Built simulation snapshot pwm_test_db_behav
|
||||
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1254.160 ; gain = 0.000
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '7' seconds
|
||||
INFO: [USF-XSim-4] XSim::Simulate design
|
||||
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [USF-XSim-98] *** Running xsim
|
||||
with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
|
||||
INFO: [USF-XSim-8] Loading simulator feature
|
||||
Time resolution is 1 ps
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
# set curr_wave [current_wave_config]
|
||||
# if { [string length $curr_wave] == 0 } {
|
||||
# if { [llength [get_objects]] > 0} {
|
||||
# add_wave /
|
||||
# set_property needs_save false [current_wave_config]
|
||||
# } else {
|
||||
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
# }
|
||||
# }
|
||||
# run 5 s
|
||||
xsim: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1254.160 ; gain = 0.000
|
||||
INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
|
||||
INFO: [USF-XSim-97] XSim simulation ran for 5 s
|
||||
launch_simulation: Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1254.160 ; gain = 0.000
|
||||
reset_run synth_1
|
||||
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
|
||||
WARNING: [Vivado 12-1017] Problems encountered:
|
||||
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
|
||||
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Wed May 11 14:33:13 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
close_sim
|
||||
INFO: [Simtcl 6-16] Simulation closed
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'regler'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling package std.standard
|
||||
Compiling package std.textio
|
||||
Compiling package ieee.std_logic_1164
|
||||
Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
|
||||
Built simulation snapshot pwm_test_db_behav
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
|
||||
INFO: [USF-XSim-4] XSim::Simulate design
|
||||
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [USF-XSim-98] *** Running xsim
|
||||
with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
|
||||
INFO: [USF-XSim-8] Loading simulator feature
|
||||
Time resolution is 1 ps
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
# set curr_wave [current_wave_config]
|
||||
# if { [string length $curr_wave] == 0 } {
|
||||
# if { [llength [get_objects]] > 0} {
|
||||
# add_wave /
|
||||
# set_property needs_save false [current_wave_config]
|
||||
# } else {
|
||||
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
# }
|
||||
# }
|
||||
# run 5 s
|
||||
INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
|
||||
INFO: [USF-XSim-97] XSim simulation ran for 5 s
|
||||
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 1254.160 ; gain = 0.000
|
||||
reset_run synth_1
|
||||
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
|
||||
WARNING: [Vivado 12-1017] Problems encountered:
|
||||
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
|
||||
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Wed May 11 14:37:39 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
close_sim
|
||||
INFO: [Simtcl 6-16] Simulation closed
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'regler'
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling package std.standard
|
||||
Compiling package std.textio
|
||||
Compiling package ieee.std_logic_1164
|
||||
Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
|
||||
Built simulation snapshot pwm_test_db_behav
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
|
||||
INFO: [USF-XSim-4] XSim::Simulate design
|
||||
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [USF-XSim-98] *** Running xsim
|
||||
with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
|
||||
INFO: [USF-XSim-8] Loading simulator feature
|
||||
Time resolution is 1 ps
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
# set curr_wave [current_wave_config]
|
||||
# if { [string length $curr_wave] == 0 } {
|
||||
# if { [llength [get_objects]] > 0} {
|
||||
# add_wave /
|
||||
# set_property needs_save false [current_wave_config]
|
||||
# } else {
|
||||
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
# }
|
||||
# }
|
||||
# run 5 s
|
||||
INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
|
||||
INFO: [USF-XSim-97] XSim simulation ran for 5 s
|
||||
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 1254.160 ; gain = 0.000
|
||||
reset_run synth_1
|
||||
INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
|
||||
WARNING: [Vivado 12-1017] Problems encountered:
|
||||
1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
|
||||
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Wed May 11 14:51:19 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
close_sim
|
||||
INFO: [Simtcl 6-16] Simulation closed
|
||||
launch_simulation
|
||||
Command: launch_simulation
|
||||
INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'
|
||||
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
||||
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
||||
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
||||
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
||||
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...
|
||||
INFO: [USF-XSim-97] Finding global include files...
|
||||
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
||||
INFO: [USF-XSim-2] XSim::Compile design
|
||||
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-3107] analyzing entity 'regler'
|
||||
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
|
||||
INFO: [USF-XSim-3] XSim::Elaborate design
|
||||
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]
|
||||
WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling package std.standard
|
||||
Compiling package std.textio
|
||||
Compiling package ieee.std_logic_1164
|
||||
Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
|
||||
Built simulation snapshot pwm_test_db_behav
|
||||
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
||||
INFO: [USF-XSim-4] XSim::Simulate design
|
||||
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'
|
||||
INFO: [USF-XSim-98] *** Running xsim
|
||||
with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"
|
||||
INFO: [USF-XSim-8] Loading simulator feature
|
||||
Time resolution is 1 ps
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
# set curr_wave [current_wave_config]
|
||||
# if { [string length $curr_wave] == 0 } {
|
||||
# if { [llength [get_objects]] > 0} {
|
||||
# add_wave /
|
||||
# set_property needs_save false [current_wave_config]
|
||||
# } else {
|
||||
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
# }
|
||||
# }
|
||||
# run 5 s
|
||||
INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.
|
||||
INFO: [USF-XSim-97] XSim simulation ran for 5 s
|
||||
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 1254.160 ; gain = 0.000
|
||||
close_sim
|
||||
INFO: [Simtcl 6-16] Simulation closed
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed May 11 14:59:27 2022...
|
||||
+3
-5
@@ -2,10 +2,10 @@
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Fri May 13 11:28:18 2022
|
||||
# Process ID: 3672
|
||||
# Start of session at: Fri May 13 14:02:42 2022
|
||||
# Process ID: 17732
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11452 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18808 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
@@ -13,5 +13,3 @@
|
||||
start_gui
|
||||
open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
launch_runs impl_1 -jobs 6
|
||||
ns synth_1 -jobs 6
|
||||
+8
-20
@@ -2,10 +2,10 @@
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Fri May 13 11:28:18 2022
|
||||
# Process ID: 3672
|
||||
# Start of session at: Fri May 13 14:02:42 2022
|
||||
# Process ID: 17732
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11452 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18808 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
@@ -37,7 +37,6 @@ WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
||||
INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save.
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
|
||||
@@ -59,26 +58,15 @@ WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 avai
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save.
|
||||
INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
|
||||
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
|
||||
INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
|
||||
WARNING: [Project 1-312] File not found as 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp'; using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp' instead.
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
WARNING: [Project 1-312] File not found as 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp'; using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp' instead.
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
|
||||
open_project: Time (s): cpu = 00:00:42 ; elapsed = 00:00:21 . Memory (MB): peak = 1576.332 ; gain = 0.000
|
||||
open_project: Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.184 ; gain = 0.000
|
||||
update_compile_order -fileset sources_1
|
||||
WARNING: [Common 17-9] Error reading message records.
|
||||
WARNING: [Common 17-9] Error reading message records.
|
||||
WARNING: [Common 17-9] Error reading message records.
|
||||
launch_runs impl_1 -jobs 6
|
||||
[Fri May 13 11:32:24 2022] Launched impl_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log
|
||||
Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
|
||||
|
||||
launch_runs synth_1 -jobs 6
|
||||
[Fri May 13 11:29:15 2022] Launched synth_1...
|
||||
Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 13 14:58:35 2022...
|
||||
@@ -0,0 +1,153 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed May 18 19:29:49 2022
|
||||
# Process ID: 18960
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3712 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
set_property -name {xsim.simulate.runtime} -value {10 s} -objects [get_filesets sim_1]
|
||||
save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 6
|
||||
wait_on_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
reset_run synth_1
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg
|
||||
source pwm_test_db.tcl
|
||||
close_sim
|
||||
File diff suppressed because it is too large.
Load diff
Binary file not shown.
@@ -0,0 +1,76 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed May 18 14:57:25 2022
|
||||
# Process ID: 19676
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent4628 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
|
||||
Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
|
||||
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available
|
||||
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
|
||||
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.
|
||||
INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
|
||||
open_project: Time (s): cpu = 00:00:30 ; elapsed = 00:00:11 . Memory (MB): peak = 1575.129 ; gain = 0.000
|
||||
update_compile_order -fileset sources_1
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed May 18 15:37:11 2022...
|
||||
Line truncated
|
||||
INFO: [Simtcl 6-16] Simulation closed
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed May 18 15:37:09 2022...
|
||||
@@ -1,154 +0,0 @@
|
||||
/*
|
||||
|
||||
Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]
|
||||
SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
|
||||
Process ID (PID): 17732
|
||||
License: Customer
|
||||
Mode: GUI Mode
|
||||
|
||||
Current time: Fri May 13 14:02:56 CEST 2022
|
||||
Time zone: Central European Standard Time (Europe/Berlin)
|
||||
|
||||
OS: Windows 10
|
||||
OS Version: 10.0
|
||||
OS Architecture: amd64
|
||||
Available processors (cores): 12
|
||||
|
||||
Screen size: 1920x1080
|
||||
Screen resolution (DPI): 100
|
||||
Available screens: 2
|
||||
Default font: family=Dialog,name=Dialog,style=plain,size=12
|
||||
Scale size: 12
|
||||
|
||||
Java version: 11.0.11 64-bit
|
||||
Java home: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9
|
||||
Java executable: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe
|
||||
Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]
|
||||
Java initial memory (-Xms): 256 MB
|
||||
Java maximum memory (-Xmx): 3 GB
|
||||
|
||||
|
||||
User name: Felix
|
||||
User home directory: C:/Users/Felix
|
||||
User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
User country: DE
|
||||
User language: de
|
||||
User locale: de_DE
|
||||
|
||||
RDI_BASEROOT: C:/Xilinx/Vivado
|
||||
HDI_APPROOT: C:/Xilinx/Vivado/2021.2
|
||||
RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data
|
||||
RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin
|
||||
|
||||
Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml
|
||||
Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/
|
||||
Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts
|
||||
PlanAhead jar file: C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar
|
||||
Vivado log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
Vivado journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
|
||||
Engine tmp dir: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-17732-DESKTOP-PAACOM8
|
||||
|
||||
Xilinx Environment Variables
|
||||
----------------------------
|
||||
TWINCATSDK: C:\TwinCAT\3.1\SDK\
|
||||
XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
|
||||
XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
|
||||
XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2
|
||||
XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2
|
||||
XILINX_VIVADO: C:/Xilinx/Vivado/2021.2
|
||||
XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2
|
||||
|
||||
|
||||
GUI allocated memory: 342 MB
|
||||
GUI max memory: 3,072 MB
|
||||
Engine allocated memory: 1,325 MB
|
||||
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
*/
|
||||
|
||||
// TclEventType: START_GUI
|
||||
// Tcl Message: start_gui
|
||||
// TclEventType: PROJECT_OPEN_DIALOG
|
||||
// Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2
|
||||
// TclEventType: DEBUG_PROBE_SET_CHANGE
|
||||
// TclEventType: FLOW_ADDED
|
||||
// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,325 MB. GUI used memory: 56 MB. Current time: 5/13/22, 2:02:57 PM CEST
|
||||
// TclEventType: MSGMGR_MOVEMSG
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: FILE_SET_NEW
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// TclEventType: RUN_CURRENT
|
||||
// TclEventType: PROJECT_DASHBOARD_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_NEW
|
||||
// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
|
||||
// Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
|
||||
// Tcl Message: Scanning sources... Finished scanning sources
|
||||
// TclEventType: PROJECT_NEW
|
||||
// [GUI Memory]: 77 MB (+78665kb) [00:00:15]
|
||||
// [Engine Memory]: 1,325 MB (+1237477kb) [00:00:15]
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 3112 ms.
|
||||
// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
|
||||
// [GUI Memory]: 102 MB (+21713kb) [00:00:18]
|
||||
// Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1
|
||||
// Tcl Message: open_project: Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.184 ; gain = 0.000
|
||||
dismissDialog("Open Project"); // bA
|
||||
// Tcl Message: update_compile_order -fileset sources_1
|
||||
// PAPropertyPanels.initPanels (pwm_test.vhd) elapsed time: 0.2s
|
||||
// Elapsed time: 11 seconds
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false); // D
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, regler(Behavioral) (pwm_test.vhd)]", 3, false, false, false, false, false, true); // D - Double Click
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 1801 ms.
|
||||
// [GUI Memory]: 134 MB (+27930kb) [00:00:32]
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false); // D
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, pt1(Behavioral) (pt1.vhd)]", 4, false, false, false, false, false, true); // D - Double Click
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 1441 ms.
|
||||
// Elapsed time: 10 seconds
|
||||
selectCodeEditor("pt1.vhd", 88, 451); // be
|
||||
selectCodeEditor("pt1.vhd", 11, 348, false, false, false, true, false); // be - Popup Trigger
|
||||
selectMenuItem(RDIResourceCommand.RDICommands_COPY, "Copy"); // ao
|
||||
// Elapsed time: 24 seconds
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false); // D
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, wendeTangente(Behavioral) (wendeTangente.vhd)]", 5, false, false, false, false, false, true); // D - Double Click
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 1130 ms.
|
||||
dismissDialog("Opening Editor"); // bA
|
||||
selectCodeEditor("wendeTangente.vhd", 126, 259); // be
|
||||
typeControlKey((HResource) null, "wendeTangente.vhd", 'c'); // be
|
||||
// Elapsed time: 82 seconds
|
||||
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 7); // D
|
||||
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 8); // D
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd)]", 10, true); // D - Node
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, pwm_test_db(Behavioral) (pwm_test_db.vhd), uut_regler : regler(Behavioral) (pwm_test.vhd)]", 11, false, false, false, false, false, true); // D - Double Click
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 1115 ms.
|
||||
// [GUI Memory]: 145 MB (+4836kb) [00:02:44]
|
||||
dismissDialog("Opening Editor"); // bA
|
||||
selectCodeEditor("pwm_test_db.vhd", 149, 169); // be
|
||||
typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
|
||||
// Elapsed time: 45 seconds
|
||||
selectCodeEditor("pwm_test_db.vhd", 251, 110); // be
|
||||
typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
|
||||
selectCodeEditor("pwm_test_db.vhd", 83, 268); // be
|
||||
typeControlKey((HResource) null, "pwm_test_db.vhd", 'c'); // be
|
||||
// Elapsed time: 50 seconds
|
||||
selectCodeEditor("pwm_test_db.vhd", 217, 345); // be
|
||||
// Elapsed time: 732 seconds
|
||||
selectCodeEditor("pwm_test_db.vhd", 229, 347); // be
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,325 MB. GUI used memory: 81 MB. Current time: 5/13/22, 2:32:57 PM CEST
|
||||
@@ -1,141 +0,0 @@
|
||||
/*
|
||||
|
||||
Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]
|
||||
SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
|
||||
Process ID (PID): 18360
|
||||
License: Customer
|
||||
Mode: GUI Mode
|
||||
|
||||
Current time: Fri May 13 11:28:40 CEST 2022
|
||||
Time zone: Central European Standard Time (Europe/Berlin)
|
||||
|
||||
OS: Windows 10
|
||||
OS Version: 10.0
|
||||
OS Architecture: amd64
|
||||
Available processors (cores): 12
|
||||
|
||||
Screen size: 1920x1080
|
||||
Screen resolution (DPI): 100
|
||||
Available screens: 2
|
||||
Default font: family=Dialog,name=Dialog,style=plain,size=12
|
||||
Scale size: 12
|
||||
|
||||
Java version: 11.0.11 64-bit
|
||||
Java home: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9
|
||||
Java executable: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe
|
||||
Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]
|
||||
Java initial memory (-Xms): 256 MB
|
||||
Java maximum memory (-Xmx): 3 GB
|
||||
|
||||
|
||||
User name: Felix
|
||||
User home directory: C:/Users/Felix
|
||||
User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
User country: DE
|
||||
User language: de
|
||||
User locale: de_DE
|
||||
|
||||
RDI_BASEROOT: C:/Xilinx/Vivado
|
||||
HDI_APPROOT: C:/Xilinx/Vivado/2021.2
|
||||
RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data
|
||||
RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin
|
||||
|
||||
Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml
|
||||
Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/
|
||||
Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts
|
||||
PlanAhead jar file: C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar
|
||||
Vivado log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
Vivado journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
|
||||
Engine tmp dir: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-18360-DESKTOP-PAACOM8
|
||||
|
||||
Xilinx Environment Variables
|
||||
----------------------------
|
||||
TWINCATSDK: C:\TwinCAT\3.1\SDK\
|
||||
XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
|
||||
XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
|
||||
XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2
|
||||
XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2
|
||||
XILINX_VIVADO: C:/Xilinx/Vivado/2021.2
|
||||
XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2
|
||||
|
||||
|
||||
GUI allocated memory: 256 MB
|
||||
GUI max memory: 3,072 MB
|
||||
Engine allocated memory: 1,262 MB
|
||||
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
*/
|
||||
|
||||
// TclEventType: START_GUI
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 1129 ms.
|
||||
// Tcl Message: start_gui
|
||||
// TclEventType: PROJECT_OPEN_DIALOG
|
||||
// Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2
|
||||
// TclEventType: DEBUG_PROBE_SET_CHANGE
|
||||
// TclEventType: FLOW_ADDED
|
||||
// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,262 MB. GUI used memory: 55 MB. Current time: 5/13/22, 11:28:41 AM CEST
|
||||
// TclEventType: MSGMGR_MOVEMSG
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: FILE_SET_NEW
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// TclEventType: RUN_CURRENT
|
||||
// TclEventType: PROJECT_DASHBOARD_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_NEW
|
||||
// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
|
||||
// Tcl Message: Scanning sources... Finished scanning sources
|
||||
// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
// TclEventType: PROJECT_NEW
|
||||
// [GUI Memory]: 78 MB (+79097kb) [00:00:27]
|
||||
// [Engine Memory]: 1,262 MB (+1171794kb) [00:00:27]
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 5264 ms.
|
||||
// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
|
||||
// [GUI Memory]: 105 MB (+24789kb) [00:00:32]
|
||||
// Tcl Message: open_project: Time (s): cpu = 00:00:37 ; elapsed = 00:00:17 . Memory (MB): peak = 1250.551 ; gain = 0.000
|
||||
// Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1
|
||||
dismissDialog("Open Project"); // bA
|
||||
// Tcl Message: update_compile_order -fileset sources_1
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// [GUI Memory]: 111 MB (+540kb) [00:01:34]
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// TclEventType: RUN_STEP_COMPLETED
|
||||
// Elapsed time: 205 seconds
|
||||
selectButton(RDIResource.BaseDialog_OK, "OK"); // a
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
|
||||
selectButton(RDIResource.BaseDialog_OK, "OK"); // a
|
||||
dismissDialog("Launch Runs"); // f
|
||||
// TclEventType: RUN_LAUNCH
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: launch_runs impl_1 -jobs 6
|
||||
// Tcl Message: [Fri May 13 11:32:24 2022] Launched impl_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// TclEventType: RUN_STEP_COMPLETED
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,262 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:32:53 AM CEST
|
||||
// TclEventType: RUN_FAILED
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// TclEventType: RUN_STEP_COMPLETED
|
||||
// Elapsed time: 58 seconds
|
||||
selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a
|
||||
// 'c' command handler elapsed time: 59 seconds
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,262 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:33:24 AM CEST
|
||||
@@ -1,151 +0,0 @@
|
||||
/*
|
||||
|
||||
Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]
|
||||
SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
|
||||
Process ID (PID): 3672
|
||||
License: Customer
|
||||
Mode: GUI Mode
|
||||
|
||||
Current time: Fri May 13 11:28:40 CEST 2022
|
||||
Time zone: Central European Standard Time (Europe/Berlin)
|
||||
|
||||
OS: Windows 10
|
||||
OS Version: 10.0
|
||||
OS Architecture: amd64
|
||||
Available processors (cores): 12
|
||||
|
||||
Screen size: 1920x1080
|
||||
Screen resolution (DPI): 100
|
||||
Available screens: 2
|
||||
Default font: family=Dialog,name=Dialog,style=plain,size=12
|
||||
Scale size: 12
|
||||
|
||||
Java version: 11.0.11 64-bit
|
||||
Java home: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9
|
||||
Java executable: C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe
|
||||
Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]
|
||||
Java initial memory (-Xms): 256 MB
|
||||
Java maximum memory (-Xmx): 3 GB
|
||||
|
||||
|
||||
User name: Felix
|
||||
User home directory: C:/Users/Felix
|
||||
User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim
|
||||
User country: DE
|
||||
User language: de
|
||||
User locale: de_DE
|
||||
|
||||
RDI_BASEROOT: C:/Xilinx/Vivado
|
||||
HDI_APPROOT: C:/Xilinx/Vivado/2021.2
|
||||
RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data
|
||||
RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin
|
||||
|
||||
Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml
|
||||
Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/
|
||||
Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts
|
||||
PlanAhead jar file: C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar
|
||||
Vivado log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
|
||||
Vivado journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
|
||||
Engine tmp dir: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-3672-DESKTOP-PAACOM8
|
||||
|
||||
Xilinx Environment Variables
|
||||
----------------------------
|
||||
TWINCATSDK: C:\TwinCAT\3.1\SDK\
|
||||
XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
|
||||
XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE
|
||||
XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2
|
||||
XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2
|
||||
XILINX_VIVADO: C:/Xilinx/Vivado/2021.2
|
||||
XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2
|
||||
|
||||
|
||||
GUI allocated memory: 256 MB
|
||||
GUI max memory: 3,072 MB
|
||||
Engine allocated memory: 1,300 MB
|
||||
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
*/
|
||||
|
||||
// TclEventType: START_GUI
|
||||
// Tcl Message: start_gui
|
||||
// TclEventType: PROJECT_OPEN_DIALOG
|
||||
// Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2
|
||||
// TclEventType: DEBUG_PROBE_SET_CHANGE
|
||||
// TclEventType: FLOW_ADDED
|
||||
// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 57 MB. Current time: 5/13/22, 11:28:41 AM CEST
|
||||
// TclEventType: MSGMGR_MOVEMSG
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: FILE_SET_NEW
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// TclEventType: RUN_CURRENT
|
||||
// TclEventType: PROJECT_DASHBOARD_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_NEW
|
||||
// Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
|
||||
// Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'
|
||||
// Tcl Message: INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save.
|
||||
// Tcl Message: INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.
|
||||
// Tcl Message: Scanning sources... Finished scanning sources
|
||||
// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
// TclEventType: PROJECT_NEW
|
||||
// [GUI Memory]: 79 MB (+80353kb) [00:00:27]
|
||||
// [Engine Memory]: 1,300 MB (+1211828kb) [00:00:27]
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 7148 ms.
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 1355 ms.
|
||||
// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
|
||||
// [GUI Memory]: 107 MB (+24993kb) [00:00:34]
|
||||
// Tcl Message: open_project: Time (s): cpu = 00:00:42 ; elapsed = 00:00:21 . Memory (MB): peak = 1576.332 ; gain = 0.000
|
||||
// Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1
|
||||
dismissDialog("Open Project"); // bA
|
||||
// Tcl Message: update_compile_order -fileset sources_1
|
||||
// Elapsed time: 10 seconds
|
||||
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
|
||||
selectButton("OptionPane.button", "OK"); // JButton
|
||||
// TclEventType: RUN_MODIFY
|
||||
// TclEventType: RUN_RESET
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// TclEventType: RUN_RESET
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: reset_run synth_1
|
||||
// Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
selectButton(RDIResource.BaseDialog_OK, "OK"); // a
|
||||
dismissDialog("Launch Runs"); // f
|
||||
// TclEventType: RUN_LAUNCH
|
||||
// TclEventType: RUN_MODIFY
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// Tcl Message: launch_runs synth_1 -jobs 6
|
||||
// Tcl Message: [Fri May 13 11:29:15 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:29:44 AM CEST
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// TclEventType: RUN_STATUS_CHANGE
|
||||
// TclEventType: RUN_STEP_COMPLETED
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:30:15 AM CEST
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:30:45 AM CEST
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:32:14 AM CEST
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:32:45 AM CEST
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:33:15 AM CEST
|
||||
// Elapsed time: 245 seconds
|
||||
selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a
|
||||
// 'k' command handler elapsed time: 249 seconds
|
||||
closeMainWindow("Coraz7_Test - [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr] - Vivado 2021.2"); // bb
|
||||
// HOptionPane Warning: 'A background task is running. Please wait until it completes to exit Vivado. If you choose to abort background task and exit immediately, you will lose all unsaved changes to project. (Background Task)'
|
||||
@@ -0,0 +1,2 @@
|
||||
[InternetShortcut]
|
||||
URL=https://freemodelfoundry.com/fphdl/Fixed_ug.pdf
|
||||
BIN
Binary file not shown.
@@ -0,0 +1,2 @@
|
||||
[InternetShortcut]
|
||||
URL=https://people-ece.vse.gmu.edu/coursewebpages/ECE/ECE448/S20/labs/sfixed_example/Fixed-point_types_in_Vivado.pdf
|
||||
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